x86/msr: Clean up MSR field declarations

 * Consistently use ULL for the benefit of 32bit builds
 * Drop leading MSR_ prefixes from bit names
 * Drop unnecessary bit-position defines

Signed-off-by: Andrew Cooper <andrew.cooper3@citrix.com>

diff --git a/arch/x86/apic.c b/arch/x86/apic.c
index 4bd8f941430ca7c6b2063cc5164178686ed8705a..3560fdd91192c7a8749d1ed22bd43ca444850b77 100644 (file)
--- a/arch/x86/apic.c
+++ b/arch/x86/apic.c
@@ -14,15 +14,15 @@ enum apic_mode cur_apic_mode;
 
 static enum apic_mode apicbase_to_mode(uint64_t apicbase)
 {
-    switch ( apicbase & (MSR_APICBASE_EXTD | MSR_APICBASE_ENABLE) )
+    switch ( apicbase & (APICBASE_EXTD | APICBASE_ENABLE) )
     {
     case 0:
         return APIC_MODE_DISABLED;
 
-    case MSR_APICBASE_ENABLE:
+    case APICBASE_ENABLE:
         return APIC_MODE_XAPIC;
 
-    case MSR_APICBASE_EXTD | MSR_APICBASE_ENABLE:
+    case APICBASE_EXTD | APICBASE_ENABLE:
         return APIC_MODE_X2APIC;
 
     default:
@@ -75,15 +75,15 @@ int apic_init(enum apic_mode mode)
     if ( mode != cur_apic_mode )
     {
         msrval = rdmsr(MSR_APICBASE) &
-            ~(MSR_APICBASE_EXTD | MSR_APICBASE_ENABLE);
+            ~(APICBASE_EXTD | APICBASE_ENABLE);
 
         wrmsr(MSR_APICBASE, msrval);
 
         if ( mode == APIC_MODE_XAPIC || mode == APIC_MODE_X2APIC )
-            wrmsr(MSR_APICBASE, msrval | MSR_APICBASE_ENABLE);
+            wrmsr(MSR_APICBASE, msrval | APICBASE_ENABLE);
 
         if ( mode == APIC_MODE_X2APIC )
-            wrmsr(MSR_APICBASE, msrval | MSR_APICBASE_ENABLE | MSR_APICBASE_EXTD);
+            wrmsr(MSR_APICBASE, msrval | APICBASE_ENABLE | APICBASE_EXTD);
 
         cur_apic_mode = mode;
     }

diff --git a/arch/x86/hvm/head.S b/arch/x86/hvm/head.S
index 5a444171ee015a1f3dbb06649f505d0e7151b274..f7dc72b58ab9ec68538f0087969ab6f72d181d80 100644 (file)
--- a/arch/x86/hvm/head.S
+++ b/arch/x86/hvm/head.S
@@ -43,7 +43,7 @@ GLOBAL(_start)                  /* HVM common setup. */
 #ifdef __x86_64__               /* EFER.LME = 1 */
         mov $MSR_EFER, %ecx
         rdmsr
-        bts $_EFER_LME, %eax
+        or  $EFER_LME, %eax
         wrmsr
 #endif /* __x86_64__ */
 

diff --git a/arch/x86/include/arch/msr-index.h b/arch/x86/include/arch/msr-index.h
index 6e7e144638ccfd16844346f9779035e949c66505..be7a6d9de0fedddce8df3acf65c8dc79f40c2590 100644 (file)
--- a/arch/x86/include/arch/msr-index.h
+++ b/arch/x86/include/arch/msr-index.h
@@ -9,27 +9,24 @@
 #include <xtf/numbers.h>
 
 #define MSR_APICBASE                    0x0000001b
-#define MSR_APICBASE_BSP                (_AC(1, L) << 8)
-#define MSR_APICBASE_EXTD               (_AC(1, L) << 10)
-#define MSR_APICBASE_ENABLE             (_AC(1, L) << 11)
+#define APICBASE_BSP                    (_AC(1, ULL) <<  8)
+#define APICBASE_EXTD                   (_AC(1, ULL) << 10)
+#define APICBASE_ENABLE                 (_AC(1, ULL) << 11)
 
 #define MSR_FEATURE_CONTROL             0x0000003a
 
 #define MSR_PMC(n)                     (0x000000c1 + (n))
 
 #define MSR_INTEL_PLATFORM_INFO         0x000000ce
-#define _MSR_PLATFORM_INFO_CPUID_FAULTING       31
-#define MSR_PLATFORM_INFO_CPUID_FAULTING        (1ULL << _MSR_PLATFORM_INFO_CPUID_FAULTING)
+#define PLATFORM_INFO_CPUID_FAULTING    (_AC(1, ULL) << 31)
 
 #define MSR_INTEL_MISC_FEATURES_ENABLES 0x00000140
-#define _MSR_MISC_FEATURES_CPUID_FAULTING        0
-#define MSR_MISC_FEATURES_CPUID_FAULTING         (1ULL << _MSR_MISC_FEATURES_CPUID_FAULTING)
+#define MISC_FEATURES_CPUID_FAULTING    (_AC(1, ULL) <<  0)
 
 #define MSR_PERFEVTSEL(n)              (0x00000186 + (n))
 
 #define MSR_DEBUGCTL                    0x000001d9
-#define _MSR_DEBUGCTL_LBR               0 /* Last Branch Record. */
-#define MSR_DEBUGCTL_LBR                (_AC(1, L) << _MSR_DEBUGCTL_LBR)
+#define DEBUGCTL_LBR                    (_AC(1, ULL) <<  0) /* Last Branch Record */
 
 #define MSR_FIXED_CTR(n)               (0x00000309 + (n))
 #define MSR_PERF_CAPABILITIES           0x00000345
@@ -44,23 +41,15 @@
 
 #define MSR_X2APIC_REGS                 0x00000800
 
-#define MSR_EFER                        0xc0000080 /* Extended Feature register. */
-#define _EFER_SCE                       0  /* SYSCALL Enable. */
-#define EFER_SCE                        (_AC(1, L) << _EFER_SCE)
-#define _EFER_LME                       8  /* Long mode enable. */
-#define EFER_LME                        (_AC(1, L) << _EFER_LME)
-#define _EFER_LMA                       10 /* Long mode Active. */
-#define EFER_LMA                        (_AC(1, L) << _EFER_LMA)
-#define _EFER_NXE                       11 /* No-Execute Enable. */
-#define EFER_NXE                        (_AC(1, L) << _EFER_NXE)
-#define _EFER_SVME                      12 /* Secure Virtual Machine Enable. */
-#define EFER_SVME                       (_AC(1, L) << _EFER_SVME)
-#define _EFER_LMSLE                     13 /* Long Mode Segment Limit Enable. */
-#define EFER_LMSLE                      (_AC(1, L) << _EFER_LMSLE)
-#define _EFER_FFXSR                     14 /* Fast FXSAVE/FXRSTOR. */
-#define EFER_FFXSR                      (_AC(1, L) << _EFER_FFXSR)
-#define _EFER_TCE                       15 /* Translation Cache Extension. */
-#define EFER_TCE                        (_AC(1, L) << _EFER_TCE)
+#define MSR_EFER                        0xc0000080 /* Extended Feature Enable Register */
+#define EFER_SCE                        (_AC(1, ULL) <<  0) /* SYSCALL Enable */
+#define EFER_LME                        (_AC(1, ULL) <<  8) /* Long Mode Enable */
+#define EFER_LMA                        (_AC(1, ULL) << 10) /* Long Mode Active */
+#define EFER_NXE                        (_AC(1, ULL) << 11) /* No Execute Enable */
+#define EFER_SVME                       (_AC(1, ULL) << 12) /* Secure Virtual Machine Enable */
+#define EFER_LMSLE                      (_AC(1, ULL) << 13) /* Long Mode Segment Limit Enable */
+#define EFER_FFXSR                      (_AC(1, ULL) << 14) /* Fast FXSAVE/FXRSTOR */
+#define EFER_TCE                        (_AC(1, ULL) << 15) /* Translation Cache Extension */
 
 #define MSR_STAR                        0xc0000081
 #define MSR_LSTAR                       0xc0000082

diff --git a/tests/cpuid-faulting/main.c b/tests/cpuid-faulting/main.c
index b10df04fca788066079c06b26cf7620f60c2a0e1..ecad92d2733e53ed537889a4d8ae09ed23765ac7 100644 (file)
--- a/tests/cpuid-faulting/main.c
+++ b/tests/cpuid-faulting/main.c
@@ -95,7 +95,7 @@ void test_main(void)
 
     /* Probe for CPUID Faulting support. */
     if ( rdmsr_safe(MSR_INTEL_PLATFORM_INFO, &platform_info) ||
-         !(platform_info & MSR_PLATFORM_INFO_CPUID_FAULTING) )
+         !(platform_info & PLATFORM_INFO_CPUID_FAULTING) )
         return xtf_skip("Skip: CPUID Faulting unavailable\n");
 
     if ( rdmsr_safe(MSR_INTEL_MISC_FEATURES_ENABLES, &features_enable) )
@@ -103,7 +103,7 @@ void test_main(void)
 
     /* Attempt to enable CPUID Faulting. */
     if ( wrmsr_safe(MSR_INTEL_MISC_FEATURES_ENABLES,
-                    features_enable | MSR_MISC_FEATURES_CPUID_FAULTING) )
+                    features_enable | MISC_FEATURES_CPUID_FAULTING) )
         return xtf_failure("Fail: Unable to enable CPUID Faulting\n");
 
     /* Faulting active.  CPUID should fault ouside of the kernel. */

diff --git a/tests/lbr-tsx-vmentry/main.c b/tests/lbr-tsx-vmentry/main.c
index 75f8059562db699bccfab1688de98f2ab26715d6..b137f63a288993b26db669420aaaffa2be287d02 100644 (file)
--- a/tests/lbr-tsx-vmentry/main.c
+++ b/tests/lbr-tsx-vmentry/main.c
@@ -59,7 +59,7 @@ void test_main(void)
     /* Probe for, and enable Last Branch Record. */
     if ( rdmsr_safe(MSR_DEBUGCTL, &dbgctl) )
         return xtf_skip("Skip: MSR_DEBUGCTL not available\n");
-    else if ( wrmsr_safe(MSR_DEBUGCTL, dbgctl | MSR_DEBUGCTL_LBR) )
+    else if ( wrmsr_safe(MSR_DEBUGCTL, dbgctl | DEBUGCTL_LBR) )
         return xtf_skip("Skip: MSR_DEBUGCTL.LBR not available\n");
 
     /* Construct a function pointer to int3_stub() via its upper alias. */