Except for the whitelisted FSGSBASE feature.
Signed-off-by: Keir Fraser <keir@xen.org>
xen-unstable changeset: 23461:
5839e797a130
xen-unstable date: Thu Jun 02 14:39:50 2011 +0100
#define X86_FEATURE_TBM (6*32+21) /* trailing bit manipulations */
#define X86_FEATURE_TOPOEXT (6*32+22) /* topology extensions CPUID leafs */
+/* Intel-defined CPU features, CPUID level 0x00000007:0 (ebx), word 9 */
+#define X86_FEATURE_FSGSBASE (7*32+ 0) /* {RD,WR}{FS,GS}BASE instructions */
+
#endif /* __LIBXC_CPUFEATURE_H */
set_bit(X86_FEATURE_HYPERVISOR, regs[2]);
break;
+ case 7:
+ if ( input[1] == 0 )
+ regs[1] &= bitmaskof(X86_FEATURE_FSGSBASE);
+ else
+ regs[1] = 0;
+ regs[0] = regs[2] = regs[3] = 0;
+ break;
+
case 0x0000000d:
xc_cpuid_config_xsave(xch, domid, xfeature_mask, input, regs);
break;
input[0] = 0x80000000u;
input[1] = XEN_CPUID_INPUT_UNUSED;
- if ( (input[0] == 4) || (input[0] == 0xd) )
+ if ( (input[0] == 4) || (input[0] == 7) || (input[0] == 0xd) )
input[1] = 0;
if ( (input[0] & 0x80000000u) && (input[0] > ext_max) )
__clear_bit(X86_FEATURE_X2APIC % 32, &c);
__set_bit(X86_FEATURE_HYPERVISOR % 32, &c);
break;
+ case 7:
+ if ( regs->ecx == 0 )
+ b &= cpufeat_mask(X86_FEATURE_FSGSBASE);
+ else
+ b = 0;
+ a = c = d = 0;
+ break;
case 0x80000001:
/* Modify Feature Information. */
if ( is_pv_32bit_vcpu(current) )