CHERRY-PICK: arm: exynos: Fix the ISP Power down sequence

This totally moves the ISP power down configuration to its own
function so we can make sure power sequencing is exactly as the
Samsung HW team suggests.  At the moment we're not using the ISP for
anything, so this should be fine.

Following is the suggested power down sequence for ISP:
- 0x10042288 --> 0x10000 (ISP A5 Disable WFE)
- 0x10042280 --> 0x0 (ISP A5 Power Off)
- 0x10041584 --> 0x0 (SYS_PWR_CFG off for CMU_RESET_ISP)
- 0x10044020 --> 0x0 (ISP Block Power Off)

Before this patch our order looks more like:
- 0x10044020 --> 0x0 (ISP Block Power Off)
- 0x10042280 --> 0x0 (ISP A5 Power Off)
- 0x10042288 --> 0x0 (ISP A5 Disable WFI / WFE)
- 0x10041584 --> 0x0 (SYS_PWR_CFG off for CMU_RESET_ISP)

We now match the suggested order except that we actually write
0x10042288 as 0x0 to disable WFE and WFI.  This matches what was set
to the register before this patch and has been OKed by the Samsung LSI
hardware team.

BUG=chrome-os-partner:15327
BUG=chrome-os-partner:17442
TEST=Revert 0.8 ABB (see Ic48ee710b623d72670db965700c215dfe280d6ea)
and then use suspend_at_boot.conf script from chrome-os-partner:15327
comment #71 to test on a device that had suspend/resume problems
without this.

Change-Id: I3ce50683e50dabd42d49d5c3d33c36dd1d24dced
Original-Change-Id:  Ia3bb141a6c94a6b3656944b6b3a2f1e0645adf8d
Signed-off-by: Abhilash Kesavan <a.kesavan@samsung.com>
Signed-off-by: Doug Anderson <dianders@chromium.org>
(cherry picked from commit 2b3c6353074a62f8b58e6abd53f9821aaa391b32)

Reviewed-on: https://gerrit.chromium.org/gerrit/42238

diff --git a/arch/arm/boot/dts/exynos5250.dtsi b/arch/arm/boot/dts/exynos5250.dtsi
index 2da632ec7ee29ec7076b4ab12fc631b623236e1a..4f2c964adef3bcd4de40a5fd6437625077b0b680 100644 (file)
--- a/arch/arm/boot/dts/exynos5250.dtsi
+++ b/arch/arm/boot/dts/exynos5250.dtsi
@@ -732,11 +732,6 @@
                #size-cells = <1>;
                ranges;
 
-               isp_arm_pd: pd@0x10042280 {
-                       compatible = "samsung,exynos4210-pd";
-                       reg = <0x10042280 0x20>;
-               };
-
                usbotg_pd: pd@0x10042E00 {
                        compatible = "samsung,exynos4210-pd";
                        reg = <0x10042E00 0x20>;
@@ -792,11 +787,6 @@
                        reg = <0x10044000 0x20>;
                };
 
-               isp_pd: pd@0x10044020 {
-                       compatible = "samsung,exynos4210-pd";
-                       reg = <0x10044020 0x20>;
-               };
-
                mfc_pd: pd@0x10044040 {
                        compatible = "samsung,exynos4210-pd";
                        reg = <0x10044040 0x20>;

diff --git a/arch/arm/mach-exynos/include/mach/regs-pmu.h b/arch/arm/mach-exynos/include/mach/regs-pmu.h
index e3b2302656f7d77592f98d744cb959f036ef9388..41645462dd7cb585b72d2ef27617f10eece43bd4 100644 (file)
--- a/arch/arm/mach-exynos/include/mach/regs-pmu.h
+++ b/arch/arm/mach-exynos/include/mach/regs-pmu.h
@@ -356,6 +356,8 @@
 #define EXYNOS5_ARM_CORE0_OPTION                       S5P_PMUREG(0x2008)
 #define EXYNOS5_ARM_CORE1_OPTION                       S5P_PMUREG(0x2088)
 #define EXYNOS5_FSYS_ARM_OPTION                                S5P_PMUREG(0x2208)
+#define EXYNOS5_ISP_ARM_CONFIGURATION                  S5P_PMUREG(0x2280)
+#define EXYNOS5_ISP_ARM_STATUS                         S5P_PMUREG(0x2284)
 #define EXYNOS5_ISP_ARM_OPTION                         S5P_PMUREG(0x2288)
 #define EXYNOS5_ARM_COMMON_OPTION                      S5P_PMUREG(0x2408)
 #define EXYNOS5_TOP_PWR_OPTION                         S5P_PMUREG(0x2C48)
@@ -366,6 +368,7 @@
 #define EXYNOS5_ISP_STATUS                             S5P_PMUREG(0x4024)
 #define EXYNOS5_GSCL_OPTION                            S5P_PMUREG(0x4008)
 #define EXYNOS5_ISP_CONFIGURATION                      S5P_PMUREG(0x4020)
+#define EXYNOS5_ISP_STATUS                             S5P_PMUREG(0x4024)
 #define EXYNOS5_ISP_OPTION                             S5P_PMUREG(0x4028)
 #define EXYNOS5_MFC_OPTION                             S5P_PMUREG(0x4048)
 #define EXYNOS5_G3D_CONFIGURATION                      S5P_PMUREG(0x4060)

diff --git a/arch/arm/mach-exynos/pmu.c b/arch/arm/mach-exynos/pmu.c
index 8c3824d846716ffebfc521b323c0fbf65e36abc6..2ee95702c318ace34fca918694b8e7a1df573e45 100644 (file)
--- a/arch/arm/mach-exynos/pmu.c
+++ b/arch/arm/mach-exynos/pmu.c
@@ -303,7 +303,7 @@ static struct exynos4_pmu_conf exynos5250_pmu_config[] = {
        { EXYNOS5_CMU_SYSCLK_MAU_SYS_PWR_REG,           { 0x1, 0x1, 0x0} },
        { EXYNOS5_CMU_SYSCLK_GPS_SYS_PWR_REG,           { 0x1, 0x0, 0x0} },
        { EXYNOS5_CMU_RESET_GSCL_SYS_PWR_REG,           { 0x1, 0x0, 0x0} },
-       { EXYNOS5_CMU_RESET_ISP_SYS_PWR_REG,            { 0x1, 0x0, 0x0} },
+       /* CMU_RESET_ISP_SYS_PWR_REG handled in exynos5250_disable_isp() */
        { EXYNOS5_CMU_RESET_MFC_SYS_PWR_REG,            { 0x1, 0x0, 0x0} },
        { EXYNOS5_CMU_RESET_G3D_SYS_PWR_REG,            { 0x1, 0x0, 0x0} },
        { EXYNOS5_CMU_RESET_DISP1_SYS_PWR_REG,          { 0x1, 0x0, 0x0} },
@@ -329,7 +329,6 @@ void __iomem *exynos5_list_both_cnt_feed[] = {
 void __iomem *exynos5_list_diable_wfi_wfe[] = {
        EXYNOS5_ARM_CORE1_OPTION,
        EXYNOS5_FSYS_ARM_OPTION,
-       EXYNOS5_ISP_ARM_OPTION,
 };
 
 static void exynos5_power_off(void)
@@ -410,6 +409,47 @@ void exynos4_sys_powerdown_conf(enum sys_powerdown mode)
                                exynos4_pmu_config[i].reg);
 }
 
+#define ISP_DISABLE_TRIES                      10
+
+/*
+ * Disable the image signal processor.
+ *
+ * We currently have no code in the kernel to manage the state of the ISP.
+ *
+ * The ISP's power sequencing code needs to be run in a very specific order
+ * and shouldn't necessarily be intertwined with the power on/power off code
+ * of the main CPU core.  Until there is kernel code to manage the ISP, we'll
+ * just hardcode powering off the ISP here.
+ */
+static void exynos5250_disable_isp(void)
+{
+       int i;
+
+       /* Make sure ISP ARM is disabled; don't use WFI or WFE */
+       __raw_writel(0, EXYNOS5_ISP_ARM_OPTION);
+
+       /* Put the ISP ARM in reset */
+       __raw_writel(0x0, EXYNOS5_ISP_ARM_CONFIGURATION);
+       for (i = 0; i < ISP_DISABLE_TRIES; i++) {
+               if (!(__raw_readl(EXYNOS5_ISP_ARM_STATUS) & 0x1))
+                       break;
+               usleep_range(80, 100);
+       }
+       WARN_ON(i == ISP_DISABLE_TRIES);
+
+       /* Reset the ISP CMU block in power-off/low power state */
+       __raw_writel(0x0, EXYNOS5_CMU_RESET_ISP_SYS_PWR_REG);
+
+       /* Turn off power to the ISP in normal mode */
+       __raw_writel(0x0, EXYNOS5_ISP_CONFIGURATION);
+       for (i = 0; i < ISP_DISABLE_TRIES; i++) {
+               if (!(__raw_readl(EXYNOS5_ISP_STATUS) & 0x7))
+                       break;
+               usleep_range(80, 100);
+       }
+       WARN_ON(i == ISP_DISABLE_TRIES);
+}
+
 static int __init exynos4_pmu_init(void)
 {
        exynos4_pmu_config = exynos4210_pmu_config;
@@ -421,6 +461,8 @@ static int __init exynos4_pmu_init(void)
                exynos4_pmu_config = exynos4212_pmu_config;
                pr_info("EXYNOS4212 PMU Initialize\n");
        } else if (soc_is_exynos5250()) {
+               exynos5250_disable_isp();
+
                exynos4_pmu_config = exynos5250_pmu_config;
                pm_power_off = exynos5_power_off;
                pr_info("EXYNOS5250 PMU Initialize\n");