printk("Test PV %%dr7 IO breakpoints\n");
if ( !(cr4 & X86_CR4_DE) )
- write_cr4(cr4 |= X86_CR4_DE);
+ write_cr4(cr4 | X86_CR4_DE);
/* Active IO breakpoint in %dr0. */
io0 = DR7_SYM(0, G, IO, 32) | X86_DR7_GE | X86_DR7_DEFAULT;
write_dr7(io0);
/* Clear %cr4.de, after which IO breakpoints are invalid. */
- write_cr4(cr4 &= ~X86_CR4_DE);
+ write_cr4(cr4);
/* Attempt to reload an IO breakpoint in %dr0, which should fail ... */
exinfo_t fault = 0;
{
xtf_failure("Fail: Initial CR4.FSGSBASE state should be clear\n");
- if ( pv_write_cr4_safe(cr4 &= ~X86_CR4_FSGSBASE) )
+ /* Try turning CR4.FSGSBASE off, to continue the test. */
+ cr4 &= ~X86_CR4_FSGSBASE;
+ if ( pv_write_cr4_safe(cr4) )
return xtf_failure("Fail: Fault while trying to clear CR4.FSGSBASE\n");
}
if ( !cpu_has_fsgsbase )
{
/* If the FSGSBASE feature isn't visible, check we can't turn it on. */
- if ( !pv_write_cr4_safe(cr4 |= X86_CR4_FSGSBASE) )
+ if ( !pv_write_cr4_safe(cr4 | X86_CR4_FSGSBASE) )
xtf_failure("Fail: Able to set CR4.FSGSBASE without the feature\n");
return;
}
/* Check we can turn CR4.FSGSBASE on. */
- if ( pv_write_cr4_safe(cr4 |= X86_CR4_FSGSBASE) )
+ if ( pv_write_cr4_safe(cr4 | X86_CR4_FSGSBASE) )
xtf_failure("Fail: Unable to enable CR4.FSGSBASE\n");
/* Check that {RD,WR}{FS,GS}BASE instructions are enabled. */
test_wrfsbase_values();
/* Check we can turn CR4.FSGSBASE off again. */
- if ( pv_write_cr4_safe(cr4 &= ~X86_CR4_FSGSBASE) )
+ if ( pv_write_cr4_safe(cr4) )
xtf_failure("Fail: Unable to enable CR4.FSGSBASE\n");
/* Check that {RD,WR}{FS,GS}BASE instructions are disabled again. */
*/
wrmsr_safe(MSR_DEBUGCTL, val |= DEBUGCTL_TR);
wrmsr_safe(MSR_DEBUGCTL, val |= DEBUGCTL_BTS);
- wrmsr_safe(MSR_DEBUGCTL, val |= DEBUGCTL_BTINT);
+ wrmsr_safe(MSR_DEBUGCTL, val | DEBUGCTL_BTINT);
/*
* If we're still alive, generate a billion jumps to check that BTS really