}
}
-static uint64_t cs_read(void *opaque, target_phys_addr_t addr, unsigned size)
+static uint64_t cs_read (void *opaque, target_phys_addr_t addr, unsigned size)
{
CSState *s = opaque;
uint32_t saddr, iaddr, ret;
return ret;
}
-static void cs_write(void *opaque, target_phys_addr_t addr,
- uint64_t val64, unsigned size)
+static void cs_write (void *opaque, target_phys_addr_t addr,
+ uint64_t val64, unsigned size)
{
CSState *s = opaque;
uint32_t saddr, iaddr, val;
isa_init_irq (dev, &s->pic, s->irq);
- memory_region_init_io(&s->ioports, &cs_ioport_ops, s, "cs4231a", 4);
- isa_register_ioport(dev, &s->ioports, s->port);
+ memory_region_init_io (&s->ioports, &cs_ioport_ops, s, "cs4231a", 4);
+ isa_register_ioport (dev, &s->ioports, s->port);
DMA_register_channel (s->dma, cs_dma_read, s);
static int gus_initfn (ISADevice *dev)
{
- GUSState *s = DO_UPCAST(GUSState, dev, dev);
+ GUSState *s = DO_UPCAST (GUSState, dev, dev);
struct audsettings as;
AUD_register_card ("gus", &s->card);
register_ioport_write (s->port, 1, 1, gus_writeb, s);
register_ioport_write (s->port, 1, 2, gus_writew, s);
- isa_init_ioport_range(dev, s->port, 2);
+ isa_init_ioport_range (dev, s->port, 2);
register_ioport_read ((s->port + 0x100) & 0xf00, 1, 1, gus_readb, s);
register_ioport_read ((s->port + 0x100) & 0xf00, 1, 2, gus_readw, s);
- isa_init_ioport_range(dev, (s->port + 0x100) & 0xf00, 2);
+ isa_init_ioport_range (dev, (s->port + 0x100) & 0xf00, 2);
register_ioport_write (s->port + 6, 10, 1, gus_writeb, s);
register_ioport_write (s->port + 6, 10, 2, gus_writew, s);
register_ioport_read (s->port + 6, 10, 1, gus_readb, s);
register_ioport_read (s->port + 6, 10, 2, gus_readw, s);
- isa_init_ioport_range(dev, s->port + 6, 10);
-
+ isa_init_ioport_range (dev, s->port + 6, 10);
register_ioport_write (s->port + 0x100, 8, 1, gus_writeb, s);
register_ioport_write (s->port + 0x100, 8, 2, gus_writew, s);
register_ioport_read (s->port + 0x100, 8, 1, gus_readb, s);
register_ioport_read (s->port + 0x100, 8, 2, gus_readw, s);
- isa_init_ioport_range(dev, s->port + 0x100, 8);
+ isa_init_ioport_range (dev, s->port + 0x100, 8);
DMA_register_channel (s->emu.gusdma, GUS_read_DMA, s);
s->emu.himemaddr = s->himem;
for (i = 0; i < ARRAY_SIZE (dsp_write_ports); i++) {
register_ioport_write (s->port + dsp_write_ports[i], 1, 1, dsp_write, s);
- isa_init_ioport(dev, s->port + dsp_write_ports[i]);
+ isa_init_ioport (dev, s->port + dsp_write_ports[i]);
}
for (i = 0; i < ARRAY_SIZE (dsp_read_ports); i++) {
register_ioport_read (s->port + dsp_read_ports[i], 1, 1, dsp_read, s);
- isa_init_ioport(dev, s->port + dsp_read_ports[i]);
+ isa_init_ioport (dev, s->port + dsp_read_ports[i]);
}
register_ioport_write (s->port + 0x4, 1, 1, mixer_write_indexb, s);
register_ioport_write (s->port + 0x4, 1, 2, mixer_write_indexw, s);
- isa_init_ioport(dev, s->port + 0x4);
+ isa_init_ioport (dev, s->port + 0x4);
register_ioport_read (s->port + 0x5, 1, 1, mixer_read, s);
register_ioport_write (s->port + 0x5, 1, 1, mixer_write_datab, s);
- isa_init_ioport(dev, s->port + 0x5);
+ isa_init_ioport (dev, s->port + 0x5);
DMA_register_channel (s->hdma, SB_read_DMA, s);
DMA_register_channel (s->dma, SB_read_DMA, s);