This patch moves page tables and vectors to their own section, in order
to avoid big alignment gaps in the middle of .text or .data. We also
remove all .org directives, as they are not needed.
Signed-off-by: Jean-Philippe Brucker <jean-philippe.brucker@arm.com>
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
b start_el3
.ltorg
-
- .org 0x100
#define BLOCK_DEV_1GB(_pa) (DEV_ATTR_UPPER | BLOCK_1GB_PA(_pa) | \
DEV_ATTR_LOWER | BLOCK_VALID)
- .data
+ .section .pgtables, "w"
#define BLOCK_INVALID (0 << 0)
dsb sy
isb
- adr x0, pgtable_l1
+ ldr x0, =pgtable_l1
msr ttbr0_el3, x0
ldr x0, =MAIR_ATTR
SECTIONS
{
. = PHYS_OFFSET;
- .text : { boot.o }
- .text : { cache.o }
- .text : { GIC }
- .text : { mmu.o }
- .text : { ns.o }
- .text : { BOOTMETHOD }
+ .text : { boot.o(.text .data) }
+ .text : { cache.o(.text .data) }
+ .text : { GIC(.text .data) }
+ .text : { mmu.o(.text .data) }
+ .text : { ns.o(.text) }
+ .text : { BOOTMETHOD(.text .data) }
+ .text : { *(.vectors) }
+ .text : { *(.pgtables) }
. = PHYS_OFFSET + MBOX_OFFSET;
mbox = .;
.mbox : { QUAD(0x0) }
b \label
.endm
- .data
+ .section .vectors, "w"
.align 11
vector:
ventry err_exception
ventry err_exception
+ .data
/*
* Array of the CPU ID (MPIDR & MPIDR_ID_BITS) of each CPU in the system.
* The index into the array is used as a logical id, and an index into
ret
setup_vector:
- adr x0, vector
+ ldr x0, =vector
msr VBAR_EL3, x0
isb
ret
b kernel
.ltorg
-
- .org 0x80