xen/arm: Restricted access to IFSR32_EL2 and FPEXC32_EL2

IFSR32_EL1 and FPEXC32_EL1 registers are accessible in
aarch64 mode only if aarch32 mode is support in EL1.
So allow access to these registers only for 32-bit domains.

Signed-off-by: Vijaya Kumar K <Vijaya.Kumar@caviumnetworks.com>
Acked-by: Ian Campbell <ian.campbell@citrix.com>

diff --git a/xen/arch/arm/arm64/vfp.c b/xen/arch/arm/arm64/vfp.c
index 3cd2b1bac0cad725f7fee5af14ad920766238d93..999a0d58a57e7acfb860cf07763cf85d2d82389c 100644 (file)
--- a/xen/arch/arm/arm64/vfp.c
+++ b/xen/arch/arm/arm64/vfp.c
@@ -28,7 +28,8 @@ void vfp_save_state(struct vcpu *v)
 
     v->arch.vfp.fpsr = READ_SYSREG32(FPSR);
     v->arch.vfp.fpcr = READ_SYSREG32(FPCR);
-    v->arch.vfp.fpexc32_el2 = READ_SYSREG32(FPEXC32_EL2);
+    if ( is_32bit_domain(v->domain) )
+        v->arch.vfp.fpexc32_el2 = READ_SYSREG32(FPEXC32_EL2);
 }
 
 void vfp_restore_state(struct vcpu *v)
@@ -56,5 +57,6 @@ void vfp_restore_state(struct vcpu *v)
 
     WRITE_SYSREG32(v->arch.vfp.fpsr, FPSR);
     WRITE_SYSREG32(v->arch.vfp.fpcr, FPCR);
-    WRITE_SYSREG32(v->arch.vfp.fpexc32_el2, FPEXC32_EL2);
+    if ( is_32bit_domain(v->domain) )
+        WRITE_SYSREG32(v->arch.vfp.fpexc32_el2, FPEXC32_EL2);
 }

diff --git a/xen/arch/arm/traps.c b/xen/arch/arm/traps.c
index 25fa8a0904f7c9098a599c799a60f10ff1d0faec..cda0523d6801d629d2b301cf3331481aca4ade13 100644 (file)
--- a/xen/arch/arm/traps.c
+++ b/xen/arch/arm/traps.c
@@ -37,6 +37,7 @@
 #include <asm/cpregs.h>
 #include <asm/psci.h>
 #include <asm/mmio.h>
+#include <asm/cpufeature.h>
 
 #include "decode.h"
 #include "vtimer.h"
@@ -789,7 +790,8 @@ void show_registers(struct cpu_user_regs *regs)
 #else
     ctxt.far = READ_SYSREG(FAR_EL1);
     ctxt.esr_el1 = READ_SYSREG(ESR_EL1);
-    ctxt.ifsr32_el2 = READ_SYSREG(IFSR32_EL2);
+    if ( is_32bit_domain(current->domain) )
+        ctxt.ifsr32_el2 = READ_SYSREG(IFSR32_EL2);
 #endif
     ctxt.vttbr_el2 = READ_SYSREG64(VTTBR_EL2);