#define ARCH_TIMER_REG_FREQ 1
#define ARCH_TIMER_REG_TVAL 2
+#undef VTIMER
+
static void arch_timer_reg_write(int reg, u32 val)
{
switch (reg) {
case ARCH_TIMER_REG_CTRL:
- asm volatile("mcr p15, 0, %0, c14, c2, 1" : : "r" (val));
+#ifndef VTIMER
+ asm volatile("mcr p15, 0, %0, c14, c2, 1" : : "r" (val)); /*CNTP_CTL*/
+#else
+ asm volatile("mcr p15, 0, %0, c14, c3, 1" : : "r" (val)); /*CNTV_CTL*/
+#endif
break;
case ARCH_TIMER_REG_TVAL:
- asm volatile("mcr p15, 0, %0, c14, c2, 0" : : "r" (val));
+#ifndef VTIMER
+ asm volatile("mcr p15, 0, %0, c14, c2, 0" : : "r" (val)); /*CNTP_TVAL*/
+#else
+ asm volatile("mcr p15, 0, %0, c14, c3, 0" : : "r" (val)); /*CNTV_TVAL*/
+#endif
break;
}
switch (reg) {
case ARCH_TIMER_REG_CTRL:
- asm volatile("mrc p15, 0, %0, c14, c2, 1" : "=r" (val));
+#ifndef VTIMER
+ asm volatile("mrc p15, 0, %0, c14, c2, 1" : "=r" (val)); /*CNTP_CTL*/
+#else
+ asm volatile("mrc p15, 0, %0, c14, c3, 1" : "=r" (val)); /*CNTV_CTL*/
+#endif
break;
case ARCH_TIMER_REG_FREQ:
- asm volatile("mrc p15, 0, %0, c14, c0, 0" : "=r" (val));
+ asm volatile("mrc p15, 0, %0, c14, c0, 0" : "=r" (val)); /*CNTFRQ*/
break;
case ARCH_TIMER_REG_TVAL:
- asm volatile("mrc p15, 0, %0, c14, c2, 0" : "=r" (val));
+#ifndef VTIMER
+ asm volatile("mrc p15, 0, %0, c14, c2, 0" : "=r" (val));/*CNTP_TVAL*/
+#else
+ asm volatile("mrc p15, 0, %0, c14, c3, 0" : "=r" (val)); /*CNTV_TVAL*/
+#endif
break;
default:
BUG();
int __init arch_timer_register(struct arch_timer *at)
{
- if (at->res[0].start <= 0 || !(at->res[0].flags & IORESOURCE_IRQ))
- return -EINVAL;
-
- arch_timer_ppi = at->res[0].start;
-
- if (at->res[1].start > 0 || (at->res[1].flags & IORESOURCE_IRQ))
- arch_timer_ppi2 = at->res[1].start;
+ arch_timer_ppi = 27;
+ arch_timer_ppi2 = 30;
return arch_timer_common_register();
}