}
res = map_mmio_regions(d,
paddr_to_pfn(addr & PAGE_MASK),
- paddr_to_pfn_aligned(addr + size),
+ DIV_ROUND_UP(size, PAGE_SIZE),
paddr_to_pfn(addr & PAGE_MASK));
if ( res )
{
* The second page is always mapped at +4K irrespective of the
* GIC_64K_STRIDE quirk. The DTB passed to the guest reflects this.
*/
- ret = map_mmio_regions(d, paddr_to_pfn(d->arch.vgic.cbase),
- paddr_to_pfn_aligned(d->arch.vgic.cbase + PAGE_SIZE),
- paddr_to_pfn(gicv2.vbase));
+ ret = map_mmio_regions(d, paddr_to_pfn(d->arch.vgic.cbase), 1,
+ paddr_to_pfn(gicv2.vbase));
if ( ret )
return ret;
if ( !platform_has_quirk(PLATFORM_QUIRK_GIC_64K_STRIDE) )
ret = map_mmio_regions(d, paddr_to_pfn(d->arch.vgic.cbase + PAGE_SIZE),
- paddr_to_pfn_aligned(d->arch.vgic.cbase +
- (2 * PAGE_SIZE)),
- paddr_to_pfn(gicv2.vbase + PAGE_SIZE));
+ 2, paddr_to_pfn(gicv2.vbase + PAGE_SIZE));
else
ret = map_mmio_regions(d, paddr_to_pfn(d->arch.vgic.cbase + PAGE_SIZE),
- paddr_to_pfn_aligned(d->arch.vgic.cbase +
- (2 * PAGE_SIZE)),
- paddr_to_pfn(gicv2.vbase + 16*PAGE_SIZE));
+ 2, paddr_to_pfn(gicv2.vbase + 16*PAGE_SIZE));
return ret;
}
int map_mmio_regions(struct domain *d,
unsigned long start_gfn,
- unsigned long end_gfn,
+ unsigned long nr_mfns,
unsigned long mfn)
{
return apply_p2m_changes(d, INSERT,
pfn_to_paddr(start_gfn),
- pfn_to_paddr(end_gfn),
+ pfn_to_paddr(start_gfn + nr_mfns),
pfn_to_paddr(mfn),
MATTR_DEV, p2m_mmio_direct);
}
static int exynos5_specific_mapping(struct domain *d)
{
/* Map the chip ID */
- map_mmio_regions(d, paddr_to_pfn(EXYNOS5_PA_CHIPID),
- paddr_to_pfn_aligned(EXYNOS5_PA_CHIPID + PAGE_SIZE),
+ map_mmio_regions(d, paddr_to_pfn(EXYNOS5_PA_CHIPID), 1,
paddr_to_pfn(EXYNOS5_PA_CHIPID));
/* Map the PWM region */
- map_mmio_regions(d, paddr_to_pfn(EXYNOS5_PA_TIMER),
- paddr_to_pfn_aligned(EXYNOS5_PA_TIMER + (PAGE_SIZE * 2)),
+ map_mmio_regions(d, paddr_to_pfn(EXYNOS5_PA_TIMER), 2,
paddr_to_pfn(EXYNOS5_PA_TIMER));
return 0;
static int omap5_specific_mapping(struct domain *d)
{
/* Map the PRM module */
- map_mmio_regions(d, paddr_to_pfn(OMAP5_PRM_BASE),
- paddr_to_pfn_aligned(OMAP5_PRM_BASE + (PAGE_SIZE * 2)),
+ map_mmio_regions(d, paddr_to_pfn(OMAP5_PRM_BASE), 2,
paddr_to_pfn(OMAP5_PRM_BASE));
/* Map the PRM_MPU */
- map_mmio_regions(d, paddr_to_pfn(OMAP5_PRCM_MPU_BASE),
- paddr_to_pfn_aligned(OMAP5_PRCM_MPU_BASE + PAGE_SIZE),
+ map_mmio_regions(d, paddr_to_pfn(OMAP5_PRCM_MPU_BASE), 1,
paddr_to_pfn(OMAP5_PRCM_MPU_BASE));
/* Map the Wakeup Gen */
- map_mmio_regions(d, paddr_to_pfn(OMAP5_WKUPGEN_BASE),
- paddr_to_pfn_aligned(OMAP5_WKUPGEN_BASE + PAGE_SIZE),
+ map_mmio_regions(d, paddr_to_pfn(OMAP5_WKUPGEN_BASE), 1,
paddr_to_pfn(OMAP5_WKUPGEN_BASE));
/* Map the on-chip SRAM */
- map_mmio_regions(d, paddr_to_pfn(OMAP5_SRAM_PA),
- paddr_to_pfn_aligned(OMAP5_SRAM_PA + (PAGE_SIZE * 32)),
+ map_mmio_regions(d, paddr_to_pfn(OMAP5_SRAM_PA), 32,
paddr_to_pfn(OMAP5_SRAM_PA));
return 0;
}
static int map_one_mmio(struct domain *d, const char *what,
- paddr_t start, paddr_t end)
+ unsigned long start, unsigned long end)
{
int ret;
printk("Additional MMIO %"PRIpaddr"-%"PRIpaddr" (%s)\n",
start, end, what);
- ret = map_mmio_regions(d, paddr_to_pfn(start),
- paddr_to_pfn_aligned(end),
- paddr_to_pfn(start));
+ ret = map_mmio_regions(d, start, end - start + 1, start);
if ( ret )
printk("Failed to map %s @ %"PRIpaddr" to dom%d\n",
what, start, d->domain_id);
int ret;
/* Map the PCIe bus resources */
- ret = map_one_mmio(d, "PCI MEM REGION", 0xe000000000UL, 0xe010000000UL);
+ ret = map_one_mmio(d, "PCI MEM REGION", paddr_to_pfn(0xe000000000UL),
+ paddr_to_pfn(0xe010000000UL));
if ( ret )
goto err;
- ret = map_one_mmio(d, "PCI IO REGION", 0xe080000000UL, 0xe080010000UL);
+ ret = map_one_mmio(d, "PCI IO REGION", paddr_to_pfn(0xe080000000UL),
+ paddr_to_pfn(0xe080010000UL));
if ( ret )
goto err;
- ret = map_one_mmio(d, "PCI CFG REGION", 0xe0d0000000UL, 0xe0d0200000UL);
+ ret = map_one_mmio(d, "PCI CFG REGION", paddr_to_pfn(0xe0d0000000UL),
+ paddr_to_pfn(0xe0d0200000UL));
if ( ret )
goto err;
- ret = map_one_mmio(d, "PCI MSI REGION", 0xe010000000UL, 0xe010800000UL);
+ ret = map_one_mmio(d, "PCI MSI REGION", paddr_to_pfn(0xe010000000UL),
+ paddr_to_pfn(0xe010800000UL));
if ( ret )
goto err;
/* Setup p2m RAM mapping for domain d from start-end. */
int p2m_populate_ram(struct domain *d, paddr_t start, paddr_t end);
-/* Map MMIO regions in the p2m: start_gfn and end_gfn is the range in the guest
- * physical address space to map, starting from the machine frame number mfn. */
+/* Map MMIO regions in the p2m: start_gfn and nr_mfns describe the range
+ * in the guest physical address space to map, starting from the machine
+ * frame number mfn. */
int map_mmio_regions(struct domain *d,
unsigned long start_gfn,
- unsigned long end_gfn,
+ unsigned long nr_mfns,
unsigned long mfn);
int guest_physmap_add_entry(struct domain *d,