u32 phybatchg;
u32 phytest;
u32 phyclkrst;
- printk(KERN_ALERT "*****Inside samsung_exynos5_usbphy3_enable*****\n");
/* Reset USB 3.0 PHY */
writel(0x0, regs + EXYNOS5_DRD_PHYREG0);
dev_info(sphy->dev, "Already power on PHY\n");
return;
}
- printk(KERN_ALERT "*****Inside samsung_exynos5_usbphy_enable*****\n");
/* Selecting Host/OTG mode; After reset USB2.0PHY_CFG: HOST */
if (sphy->plat && sphy->plat->phy_cfg_sel)
sphy->plat->phy_cfg_sel(sphy->dev, USB_PHY_TYPE_HOST);
dev_err(sphy->dev, "Not a valid cpu_type for USB 3.0\n");
return -ENODEV;
}
- printk(KERN_ALERT "******Inside samsung_usbphy3_init*******\n");
/* setting default phy-type for USB 3.0 */
samsung_usbphy_set_type(&sphy->phy3, USB_PHY_TYPE_DRD);
sphy = phy_to_sphy(phy);
- printk(KERN_ALERT "******Inside samsung_usbphy_init******\n");
/* Enable the phy clock */
ret = clk_prepare_enable(sphy->clk);
if (ret) {