vcpu_kick(target);
}
-static int vlapic_find_highest_isr(struct vlapic *vlapic)
+static int vlapic_find_highest_isr(const struct vlapic *vlapic)
{
return vlapic_find_highest_vector(&vlapic->regs->data[APIC_ISR]);
}
-static uint32_t vlapic_get_ppr(struct vlapic *vlapic)
+static uint32_t vlapic_get_ppr(const struct vlapic *vlapic)
{
uint32_t tpr, isrv, ppr;
int isr;
}
}
-static uint32_t vlapic_get_tmcct(struct vlapic *vlapic)
+static uint32_t vlapic_get_tmcct(const struct vlapic *vlapic)
{
- struct vcpu *v = current;
+ const struct vcpu *v = const_vlapic_vcpu(vlapic);
uint32_t tmcct = 0, tmict = vlapic_get_reg(vlapic, APIC_TMICT);
uint64_t counter_passed;
"timer_divisor: %d", vlapic->hw.timer_divisor);
}
-static uint32_t vlapic_read_aligned(struct vlapic *vlapic, unsigned int offset)
+static uint32_t vlapic_read_aligned(const struct vlapic *vlapic,
+ unsigned int offset)
{
switch ( offset )
{
REGBLOCK(ISR) | REGBLOCK(TMR) | REGBLOCK(IRR)
#undef REGBLOCK
};
- struct vlapic *vlapic = vcpu_vlapic(v);
+ const struct vlapic *vlapic = vcpu_vlapic(v);
uint32_t high = 0, reg = msr - MSR_IA32_APICBASE_MSR, offset = reg << 4;
if ( !vlapic_x2apic_mode(vlapic) ||
pl->last_guest_time = 0;
}
-u64 hvm_get_guest_time_fixed(struct vcpu *v, u64 at_tsc)
+uint64_t hvm_get_guest_time_fixed(const struct vcpu *v, uint64_t at_tsc)
{
struct pl_time *pl = v->domain->arch.hvm_domain.pl_time;
u64 now;
void hvm_init_guest_time(struct domain *d);
void hvm_set_guest_time(struct vcpu *v, u64 guest_time);
-u64 hvm_get_guest_time_fixed(struct vcpu *v, u64 at_tsc);
+uint64_t hvm_get_guest_time_fixed(const struct vcpu *v, uint64_t at_tsc);
#define hvm_get_guest_time(v) hvm_get_guest_time_fixed(v, 0)
int vmsi_deliver(