static void ctxt_switch_from(struct vcpu *p)
{
+ p2m_save_state(p);
+
/* CP 15 */
p->arch.csselr = READ_SYSREG(CSSELR_EL1);
/* Control Registers */
- p->arch.sctlr = READ_SYSREG(SCTLR_EL1);
p->arch.cpacr = READ_SYSREG(CPACR_EL1);
p->arch.contextidr = READ_SYSREG(CONTEXTIDR_EL1);
static void ctxt_switch_to(struct vcpu *n)
{
- register_t hcr;
-
- hcr = READ_SYSREG(HCR_EL2);
- WRITE_SYSREG(hcr & ~HCR_VM, HCR_EL2);
- isb();
-
- p2m_load_VTTBR(n->domain);
- isb();
+ p2m_restore_state(n);
WRITE_SYSREG32(n->domain->arch.vpidr, VPIDR_EL2);
WRITE_SYSREG(n->arch.vmpidr, VMPIDR_EL2);
isb();
/* Control Registers */
- WRITE_SYSREG(n->arch.sctlr, SCTLR_EL1);
WRITE_SYSREG(n->arch.cpacr, CPACR_EL1);
WRITE_SYSREG(n->arch.contextidr, CONTEXTIDR_EL1);
isb();
- if ( is_32bit_domain(n->domain) )
- hcr &= ~HCR_RW;
- else
- hcr |= HCR_RW;
-
- WRITE_SYSREG(hcr, HCR_EL2);
- isb();
-
/* This is could trigger an hardware interrupt from the virtual
* timer. The interrupt needs to be injected into the guest. */
virt_timer_restore(n);
isb(); /* Ensure update is visible */
}
+void p2m_save_state(struct vcpu *p)
+{
+ p->arch.sctlr = READ_SYSREG(SCTLR_EL1);
+}
+
+void p2m_restore_state(struct vcpu *n)
+{
+ register_t hcr;
+
+ hcr = READ_SYSREG(HCR_EL2);
+ WRITE_SYSREG(hcr & ~HCR_VM, HCR_EL2);
+ isb();
+
+ p2m_load_VTTBR(n->domain);
+ isb();
+
+ if ( is_32bit_domain(n->domain) )
+ hcr &= ~HCR_RW;
+ else
+ hcr |= HCR_RW;
+
+ WRITE_SYSREG(n->arch.sctlr, SCTLR_EL1);
+ isb();
+
+ WRITE_SYSREG(hcr, HCR_EL2);
+ isb();
+}
+
static int p2m_first_level_index(paddr_t addr)
{
/*
/* */
void p2m_load_VTTBR(struct domain *d);
+/* Context switch */
+void p2m_save_state(struct vcpu *p);
+void p2m_restore_state(struct vcpu *n);
+
/* Look up the MFN corresponding to a domain's PFN. */
paddr_t p2m_lookup(struct domain *d, paddr_t gpfn, p2m_type_t *t);