xen: arm: make stage 2 page tables walks inner-shareable

The comment was previously incorrect and indicated that these mappings were
unshared (00) when in reality the register was set for outer-shareable (01).

Clarify ORGN0/IRGN0 in the comments while at it.

Signed-off-by: Ian Campbell <ian.campbell@citrix.com>
Acked-by: Julien Grall <julien.grall@linaro.org>

diff --git a/xen/arch/arm/mm.c b/xen/arch/arm/mm.c
index e9b3f349c635f1f119960f7d6c89c5879edcda22..6f1408b107b4f590be14deee70a5c50581c41a47 100644 (file)
--- a/xen/arch/arm/mm.c
+++ b/xen/arch/arm/mm.c
@@ -378,16 +378,17 @@ void __init arch_init_memory(void)
 void __cpuinit setup_virt_paging(void)
 {
     /* Setup Stage 2 address translation */
-    /* SH0=00, ORGN0=IRGN0=01
+    /* SH0=11 (Inner-shareable)
+     * ORGN0=IRGN0=01 (Normal memory, Write-Back Write-Allocate Cacheable)
      * SL0=01 (Level-1)
      * ARVv7: T0SZ=(1)1000 = -8 (32-(-8) = 40 bit physical addresses)
      * ARMv8: T0SZ=01 1000 = 24 (64-24   = 40 bit physical addresses)
      *        PS=010 == 40 bits
      */
 #ifdef CONFIG_ARM_32
-    WRITE_SYSREG32(0x80002558, VTCR_EL2);
+    WRITE_SYSREG32(0x80003558, VTCR_EL2);
 #else
-    WRITE_SYSREG32(0x80022558, VTCR_EL2);
+    WRITE_SYSREG32(0x80023558, VTCR_EL2);
 #endif
     isb();
 }