CHERRY-PICK: arm: exynos: Enable CHIP ID clock

The bootloader may gate the CLK_CHIPID_APBIF which will cause
an invalid value to be read for the Package ID in ASV. Explicitly
enable the clock in the ASV driver.

BUG=chrome-os-partner:16796
TEST=Boot 5 different snows to the login screen. Verify that the clock
is enabled and the appropriate speed group is being selected. Do a few
suspend/resume cycles with reboots.

Change-Id: Id5a0ec599c7aedc9ae98297fbc035fce887c8bd5
Original-Change-Id:  Ib094b748301b7e882a50ae056bd9f0f795c133e5
Signed-off-by: Abhilash Kesavan <a.kesavan@samsung.com>
Signed-off-by: Doug Anderson <dianders@chromium.org>
(cherry picked from commit eeb5bd2fd266d9980fa4ee73be4c37ff732f0f3b)

Reviewed-on: https://gerrit.chromium.org/gerrit/40951
Reviewed-by: Olof Johansson <olofj@chromium.org>

diff --git a/arch/arm/mach-exynos/asv-5250.c b/arch/arm/mach-exynos/asv-5250.c
index 61dd0a1984b6d5844ff0e81cf30f5f16bce80623..b953de8fcbb732c12fe3826c4974e4e0fa74596b 100644 (file)
--- a/arch/arm/mach-exynos/asv-5250.c
+++ b/arch/arm/mach-exynos/asv-5250.c
@@ -394,9 +394,17 @@ static int exynos5250_asv_init(void)
 {
        u32 chip_id;
        struct samsung_asv *exynos_asv;
+       struct clk *chipid_clk;
 
        printk(KERN_INFO  "EXYNOS5250: Adaptive Support Voltage init\n");
 
+       chipid_clk = clk_get(NULL, "chipid_apbif");
+       if (IS_ERR(chipid_clk)) {
+               pr_err("Failed to get chipid clock for ASV\n");
+               return PTR_ERR(chipid_clk);
+       }
+       clk_enable(chipid_clk);
+
        exynos_asv = kzalloc(sizeof(struct samsung_asv), GFP_KERNEL);
        if (!exynos_asv)
                return -ENOMEM;
@@ -450,13 +458,15 @@ static int exynos5250_asv_init(void)
 
                exynos5250_pre_set_abb();
 
-               return 0;
+               goto exit;
        }
 
        exynos_asv->ids_result = (exynos_asv->package_id >> IDS_ARM_OFFSET) & IDS_ARM_MASK;
        exynos_asv->hpm_result = (exynos_asv->package_id >> HPM_OFFSET) & HPM_MASK;
        exynos5250_asv_store_result(exynos_asv);
 
+exit:
+       clk_disable(chipid_clk);
        return 0;
 }
 device_initcall_sync(exynos5250_asv_init);

diff --git a/arch/arm/mach-exynos/clock-exynos5.c b/arch/arm/mach-exynos/clock-exynos5.c
index cedbd96d8f5ce1d3e6f89184c023d18a1b466980..8a95cdb4c22e1dc0b544a19453e3bb6504c25f6d 100644 (file)
--- a/arch/arm/mach-exynos/clock-exynos5.c
+++ b/arch/arm/mach-exynos/clock-exynos5.c
@@ -997,6 +997,10 @@ static struct clk exynos5_init_clocks_off[] = {
                .name           = "g3d",
                .enable         = exynos5_clk_ip_g3d_ctrl,
                .ctrlbit        = ((1 << 1) | (1 << 0)),
+       }, {
+               .name           = "chipid_apbif",
+               .enable         = exynos5_clk_ip_peris_ctrl,
+               .ctrlbit        = (1 << 0),
        }
 };