IntelFsp2Pkg: LoadMicrocodeDefault() causing unnecessary delay.

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4391

FSP should support the scenario that CPU microcode already loaded
before calling LoadMicrocodeDefault(), in this case it should return
directly without spending more time.
Also the LoadMicrocodeDefault() should only attempt to load one version
of the microcode for current CPU and return directly without parsing
rest of the microcode in FV.

This patch also removed unnecessary LoadCheck code after supporting
CPU microcode already loaded scenario.

Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
Cc: Star Zeng <star.zeng@intel.com>
Cc: Ray Ni <ray.ni@intel.com>
Signed-off-by: Chasel Chiu <chasel.chiu@intel.com>
Reviewed-by: Ted Kuo <ted.kuo@intel.com>
Reviewed-by: Nate DeSimone <nathaniel.l.desimone@intel.com>
Reviewed-by: Ray Ni <ray.ni@intel.com>

diff --git a/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryT.nasm b/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryT.nasm
index 2cff8b3643246a45d01a83c13856f8e3052b12f2..900126b93bda42c7fc2158135f9215f8e7704a6c 100644 (file)
--- a/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryT.nasm
+++ b/IntelFsp2Pkg/FspSecCore/Ia32/FspApiEntryT.nasm
@@ -245,6 +245,22 @@ ASM_PFX(LoadMicrocodeDefault):
    cmp    esp, 0\r
    jz     ParamError\r
 \r
+   ;\r
+   ; If microcode already loaded before this function, exit this function with SUCCESS.\r
+   ;\r
+   mov   ecx, MSR_IA32_BIOS_SIGN_ID\r
+   xor   eax, eax               ; Clear EAX\r
+   xor   edx, edx               ; Clear EDX\r
+   wrmsr                        ; Load 0 to MSR at 8Bh\r
+\r
+   mov   eax, 1\r
+   cpuid\r
+   mov   ecx, MSR_IA32_BIOS_SIGN_ID\r
+   rdmsr                         ; Get current microcode signature\r
+   xor   eax, eax\r
+   test  edx, edx\r
+   jnz   Exit2\r
+\r
    ; skip loading Microcode if the MicrocodeCodeSize is zero\r
    ; and report error if size is less than 2k\r
    ; first check UPD header revision\r
@@ -330,7 +346,7 @@ CheckMainHeader:
    cmp   ebx, dword [esi + MicrocodeHdr.MicrocodeHdrProcessor]\r
    jne   LoadMicrocodeDefault1\r
    test  edx, dword [esi + MicrocodeHdr.MicrocodeHdrFlags ]\r
-   jnz   LoadCheck  ; Jif signature and platform ID match\r
+   jnz   LoadMicrocode  ; Jif signature and platform ID match\r
 \r
 LoadMicrocodeDefault1:\r
    ; Check if extended header exists\r
@@ -363,7 +379,7 @@ CheckExtSig:
    cmp   dword [edi + ExtSig.ExtSigProcessor], ebx\r
    jne   LoadMicrocodeDefault2\r
    test  dword [edi + ExtSig.ExtSigFlags], edx\r
-   jnz   LoadCheck      ; Jif signature and platform ID match\r
+   jnz   LoadMicrocode      ; Jif signature and platform ID match\r
 LoadMicrocodeDefault2:\r
    ; Check if any more extended signatures exist\r
    add   edi, ExtSig.size\r
@@ -435,23 +451,7 @@ LoadMicrocodeDefault4:
    ; Is valid Microcode start point ?\r
    cmp   dword [esi + MicrocodeHdr.MicrocodeHdrVersion], 0ffffffffh\r
    jz    Done\r
-\r
-LoadCheck:\r
-   ; Get the revision of the current microcode update loaded\r
-   mov   ecx, MSR_IA32_BIOS_SIGN_ID\r
-   xor   eax, eax               ; Clear EAX\r
-   xor   edx, edx               ; Clear EDX\r
-   wrmsr                        ; Load 0 to MSR at 8Bh\r
-\r
-   mov   eax, 1\r
-   cpuid\r
-   mov   ecx, MSR_IA32_BIOS_SIGN_ID\r
-   rdmsr                        ; Get current microcode signature\r
-\r
-   ; Verify this microcode update is not already loaded\r
-   cmp   dword [esi + MicrocodeHdr.MicrocodeHdrRevision], edx\r
-   je    Continue\r
-\r
+   jmp   CheckMainHeader\r
 LoadMicrocode:\r
    ; EAX contains the linear address of the start of the Update Data\r
    ; EDX contains zero\r
@@ -465,10 +465,12 @@ LoadMicrocode:
    mov   eax, 1\r
    cpuid\r
 \r
-Continue:\r
-   jmp   NextMicrocode\r
-\r
 Done:\r
+   mov   ecx, MSR_IA32_BIOS_SIGN_ID\r
+   xor   eax, eax               ; Clear EAX\r
+   xor   edx, edx               ; Clear EDX\r
+   wrmsr                        ; Load 0 to MSR at 8Bh\r
+\r
    mov   eax, 1\r
    cpuid\r
    mov   ecx, MSR_IA32_BIOS_SIGN_ID\r

diff --git a/IntelFsp2Pkg/FspSecCore/X64/FspApiEntryT.nasm b/IntelFsp2Pkg/FspSecCore/X64/FspApiEntryT.nasm
index b32fa32a89282fbc29d27408dbf95443191da095..698bb063a756283d035b5fdf420a45e9f942166c 100644 (file)
--- a/IntelFsp2Pkg/FspSecCore/X64/FspApiEntryT.nasm
+++ b/IntelFsp2Pkg/FspSecCore/X64/FspApiEntryT.nasm
@@ -141,6 +141,22 @@ ASM_PFX(LoadMicrocodeDefault):
    jz     ParamError\r
    mov    rsp, rcx\r
 \r
+   ;\r
+   ; If microcode already loaded before this function, exit this function with SUCCESS.\r
+   ;\r
+   mov   ecx, MSR_IA32_BIOS_SIGN_ID\r
+   xor   eax, eax               ; Clear EAX\r
+   xor   edx, edx               ; Clear EDX\r
+   wrmsr                        ; Load 0 to MSR at 8Bh\r
+\r
+   mov   eax, 1\r
+   cpuid\r
+   mov   ecx, MSR_IA32_BIOS_SIGN_ID\r
+   rdmsr                         ; Get current microcode signature\r
+   xor   rax, rax\r
+   test  edx, edx\r
+   jnz   Exit2\r
+\r
    ; skip loading Microcode if the MicrocodeCodeSize is zero\r
    ; and report error if size is less than 2k\r
    ; first check UPD header revision\r
@@ -198,7 +214,7 @@ CheckMainHeader:
    cmp   ebx, dword [esi + MicrocodeHdr.MicrocodeHdrProcessor]\r
    jne   LoadMicrocodeDefault1\r
    test  edx, dword [esi + MicrocodeHdr.MicrocodeHdrFlags ]\r
-   jnz   LoadCheck  ; Jif signature and platform ID match\r
+   jnz   LoadMicrocode  ; Jif signature and platform ID match\r
 \r
 LoadMicrocodeDefault1:\r
    ; Check if extended header exists\r
@@ -231,7 +247,7 @@ CheckExtSig:
    cmp   dword [edi + ExtSig.ExtSigProcessor], ebx\r
    jne   LoadMicrocodeDefault2\r
    test  dword [edi + ExtSig.ExtSigFlags], edx\r
-   jnz   LoadCheck      ; Jif signature and platform ID match\r
+   jnz   LoadMicrocode      ; Jif signature and platform ID match\r
 LoadMicrocodeDefault2:\r
    ; Check if any more extended signatures exist\r
    add   edi, ExtSig.size\r
@@ -276,22 +292,7 @@ LoadMicrocodeDefault4:
    ; Is valid Microcode start point ?\r
    cmp   dword [esi + MicrocodeHdr.MicrocodeHdrVersion], 0ffffffffh\r
    jz    Done\r
-\r
-LoadCheck:\r
-   ; Get the revision of the current microcode update loaded\r
-   mov   ecx, MSR_IA32_BIOS_SIGN_ID\r
-   xor   eax, eax               ; Clear EAX\r
-   xor   edx, edx               ; Clear EDX\r
-   wrmsr                        ; Load 0 to MSR at 8Bh\r
-\r
-   mov   eax, 1\r
-   cpuid\r
-   mov   ecx, MSR_IA32_BIOS_SIGN_ID\r
-   rdmsr                        ; Get current microcode signature\r
-\r
-   ; Verify this microcode update is not already loaded\r
-   cmp   dword [esi + MicrocodeHdr.MicrocodeHdrRevision], edx\r
-   je    Continue\r
+   jmp   CheckMainHeader\r
 \r
 LoadMicrocode:\r
    ; EAX contains the linear address of the start of the Update Data\r
@@ -306,10 +307,12 @@ LoadMicrocode:
    mov   eax, 1\r
    cpuid\r
 \r
-Continue:\r
-   jmp   NextMicrocode\r
-\r
 Done:\r
+   mov   ecx, MSR_IA32_BIOS_SIGN_ID\r
+   xor   eax, eax               ; Clear EAX\r
+   xor   edx, edx               ; Clear EDX\r
+   wrmsr                        ; Load 0 to MSR at 8Bh\r
+\r
    mov   eax, 1\r
    cpuid\r
    mov   ecx, MSR_IA32_BIOS_SIGN_ID\r