NTB: MFV 87034511: Correct Number of Scratch Pad Registers

The NTB Xeon hardware has 16 scratch pad registers and 16 back-to-back
scratch pad registers.  Correct the #define to represent this and update
the variable names to reflect their usage.

Authored by:	Jon Mason
Obtained from:	Linux
Sponsored by:	EMC / Isilon Storage Division

diff --git a/sys/dev/ntb/ntb_hw/ntb_regs.h b/sys/dev/ntb/ntb_hw/ntb_regs.h
index bd55a59184ba5a63f6d93c3f78201cefaf19fcd0..178a6e21447dc49abfd1fb393f8afe7d9d37d3b8 100644 (file)
--- a/sys/dev/ntb/ntb_hw/ntb_regs.h
+++ b/sys/dev/ntb/ntb_hw/ntb_regs.h
@@ -37,7 +37,7 @@
 
 #define XEON_MSIX_CNT          4
 #define XEON_MAX_SPADS         16
-#define XEON_MAX_COMPAT_SPADS  8
+#define XEON_MAX_COMPAT_SPADS  16
 /* Reserve the uppermost bit for link interrupt */
 #define XEON_MAX_DB_BITS       15
 #define XEON_DB_BITS_PER_VEC   5