HACK! arm: set v7 translation table entries as uncachable

There appears to be a bug in the model where the MMU does not
correctly see updates to translation table entries if they are marked
as cachable.  This bug only happens when running under the Xen
hypervisor.

As a workaround, mark the entries as uncachable.  This decreases
performance.

[ijc - rebase, applying to both proc-v7-{2,3}level.S]

diff --git a/arch/arm/mm/proc-v7-2level.S b/arch/arm/mm/proc-v7-2level.S
index c663b2eb1dc453f3b9566bd38339caf08b22ef42..0c8eeb8664a1ccfb4d5264f3ddd7124056c56551 100644 (file)
--- a/arch/arm/mm/proc-v7-2level.S
+++ b/arch/arm/mm/proc-v7-2level.S
@@ -20,11 +20,11 @@
 #define TTB_IRGN_WB    ((1 << 0) | (1 << 6))
 
 /* PTWs cacheable, inner WB not shareable, outer WB not shareable */
-#define TTB_FLAGS_UP   TTB_IRGN_WB|TTB_RGN_OC_WB
+#define TTB_FLAGS_UP   TTB_IRGN_NC|TTB_RGN_NC
 #define PMD_FLAGS_UP   PMD_SECT_WB
 
 /* PTWs cacheable, inner WBWA shareable, outer WBWA not shareable */
-#define TTB_FLAGS_SMP  TTB_IRGN_WBWA|TTB_S|TTB_NOS|TTB_RGN_OC_WBWA
+#define TTB_FLAGS_SMP  TTB_IRGN_NC|TTB_S|TTB_NOS|TTB_RGN_NC
 #define PMD_FLAGS_SMP  PMD_SECT_WBWA|PMD_SECT_S
 
 /*

diff --git a/arch/arm/mm/proc-v7-3level.S b/arch/arm/mm/proc-v7-3level.S
index 8de0f1dd1549463e6dae83a50509b6d0f071de4b..5c8dd096f597542325957eff9b343afdb9965a4c 100644 (file)
--- a/arch/arm/mm/proc-v7-3level.S
+++ b/arch/arm/mm/proc-v7-3level.S
@@ -32,11 +32,11 @@
 #define TTB_EAE                (1 << 31)
 
 /* PTWs cacheable, inner WB not shareable, outer WB not shareable */
-#define TTB_FLAGS_UP   (TTB_IRGN_WB|TTB_RGN_OC_WB)
+#define TTB_FLAGS_UP   (TTB_IRGN_NC|TTB_RGN_NC)
 #define PMD_FLAGS_UP   (PMD_SECT_WB)
 
 /* PTWs cacheable, inner WBWA shareable, outer WBWA not shareable */
-#define TTB_FLAGS_SMP  (TTB_IRGN_WBWA|TTB_S|TTB_RGN_OC_WBWA)
+#define TTB_FLAGS_SMP  (TTB_IRGN_NC|TTB_S|TTB_RGN_NC)
 #define PMD_FLAGS_SMP  (PMD_SECT_WBWA|PMD_SECT_S)
 
 /*