}
}
-int force_mwait;
-
static void disable_c1e(void *unused)
{
uint64_t msr_content;
amd_get_topology(c);
/* Pointless to use MWAIT on Family10 as it does not deep sleep. */
- if (c->x86 >= 0x10 && !force_mwait)
+ if (c->x86 == 0x10)
__clear_bit(X86_FEATURE_MWAIT, c->x86_capability);
if (!cpu_has_amd_erratum(c, AMD_ERRATUM_121))
};
/* all the cache descriptor types we care about (no TLB or trace cache entries) */
-static struct _cache_table cache_table[] =
+static const struct _cache_table cache_table[] =
{
{ 0x06, LVL_1_INST, 8 }, /* 4-way set assoc, 32 byte line size */
{ 0x08, LVL_1_INST, 16 }, /* 4-way set assoc, 32 byte line size */
nodemask_t __read_mostly node_online_map = { { [0] = 1UL } };
-int numa_off = 0;
-
-int acpi_numa;
+bool_t numa_off = 0;
+s8 acpi_numa = 0;
int srat_disabled(void)
{
#define ARCH_HAS_POWER_INIT 1
-extern int acpi_numa;
+extern s8 acpi_numa;
extern int acpi_scan_nodes(u64 start, u64 end);
#define NR_NODE_MEMBLKS (MAX_NUMNODES*2)
extern void numa_add_cpu(int cpu);
extern void numa_init_array(void);
-extern int numa_off;
+extern bool_t numa_off;
extern int srat_disabled(void);