#define hwloc_fls32 HWLOC_NAME(fls32)
#define hwloc_weight_long HWLOC_NAME(weight_long)
-#define HWLOC_PCI_CAPABILITY_LIST HWLOC_NAME_CAPS(PCI_CAPABILITY_LIST)
-#define HWLOC_PCI_STATUS_CAP_LIST HWLOC_NAME_CAPS(PCI_STATUS_CAP_LIST)
-#define HWLOC_PCI_CAP_LIST_ID HWLOC_NAME_CAPS(PCI_CAP_LIST_ID)
-#define HWLOC_PCI_CAP_LIST_NEXT HWLOC_NAME_CAPS(PCI_CAP_LIST_NEXT)
-#define HWLOC_PCI_STATUS HWLOC_NAME_CAPS(PCI_STATUS)
#define hwloc_pci_find_cap HWLOC_NAME(pci_find_cap)
+#define hwloc_pci_find_linkspeed HWLOC_NAME(pci_find_linkspeed)
/* private/cpuid.h */
return 0;
}
+#define HWLOC_PCI_EXP_LNKSTA 0x12
+#define HWLOC_PCI_EXP_LNKSTA_SPEED 0x000f
+#define HWLOC_PCI_EXP_LNKSTA_WIDTH 0x03f0
+
+static __hwloc_inline int
+hwloc_pci_find_linkspeed(const unsigned char *config, size_t config_size,
+ unsigned offset, float *linkspeed)
+{
+ unsigned linksta, speed, width;
+ float lanespeed;
+
+ if (offset + HWLOC_PCI_EXP_LNKSTA + 4 >= config_size)
+ return -1;
+
+ memcpy(&linksta, &config[offset + HWLOC_PCI_EXP_LNKSTA], 4);
+ speed = linksta & HWLOC_PCI_EXP_LNKSTA_SPEED; /* PCIe generation */
+ width = (linksta & HWLOC_PCI_EXP_LNKSTA_WIDTH) >> 4; /* how many lanes */
+ /* PCIe Gen1 = 2.5GT/s signal-rate per lane with 8/10 encoding = 0.25GB/s data-rate per lane
+ * PCIe Gen2 = 5 GT/s signal-rate per lane with 8/10 encoding = 0.5 GB/s data-rate per lane
+ * PCIe Gen3 = 8 GT/s signal-rate per lane with 128/130 encoding = 1 GB/s data-rate per lane
+ */
+ lanespeed = speed <= 2 ? 2.5 * speed * 0.8 : 8.0 * 128/130; /* Gbit/s per lane */
+ *linkspeed = lanespeed * width / 8; /* GB/s */
+ return 0;
+}
+
#endif /* HWLOC_PRIVATE_MISC_H */
#define PCI_SUBORDINATE_BUS 0x1a
#endif
-#ifndef PCI_EXP_LNKSTA
-#define PCI_EXP_LNKSTA 18
-#endif
-
-#ifndef PCI_EXP_LNKSTA_SPEED
-#define PCI_EXP_LNKSTA_SPEED 0x000f
-#endif
-#ifndef PCI_EXP_LNKSTA_WIDTH
-#define PCI_EXP_LNKSTA_WIDTH 0x03f0
-#endif
-
#ifndef PCI_CAP_ID_EXP
#define PCI_CAP_ID_EXP 0x10
#endif
#else
offset = hwloc_pci_find_cap(config_space_cache, config_space_cachesize, PCI_CAP_ID_EXP);
#endif /* HWLOC_HAVE_PCI_FIND_CAP */
- if (offset > 0) {
- if (offset + PCI_EXP_LNKSTA + 4 >= config_space_cachesize) {
- fprintf(stderr, "cannot read PCI_EXP_LNKSTA cap at %d (only %d cached)\n", offset + PCI_EXP_LNKSTA, CONFIG_SPACE_CACHESIZE);
- } else {
- unsigned linksta, speed, width;
- float lanespeed;
- memcpy(&linksta, &config_space_cache[offset + PCI_EXP_LNKSTA], 4);
- speed = linksta & PCI_EXP_LNKSTA_SPEED; /* PCIe generation */
- width = (linksta & PCI_EXP_LNKSTA_WIDTH) >> 4; /* how many lanes */
- /* PCIe Gen1 = 2.5GT/s signal-rate per lane with 8/10 encoding = 0.25GB/s data-rate per lane
- * PCIe Gen2 = 5 GT/s signal-rate per lane with 8/10 encoding = 0.5 GB/s data-rate per lane
- * PCIe Gen3 = 8 GT/s signal-rate per lane with 128/130 encoding = 1 GB/s data-rate per lane
- */
- lanespeed = speed <= 2 ? 2.5 * speed * 0.8 : 8.0 * 128/130; /* Gbit/s per lane */
- obj->attr->pcidev.linkspeed = lanespeed * width / 8; /* GB/s */
- }
- }
+ if (offset > 0)
+ hwloc_pci_find_linkspeed(config_space_cache, config_space_cachesize, offset,
+ &obj->attr->pcidev.linkspeed);
if (isbridge) {
HWLOC_BUILD_ASSERT(PCI_PRIMARY_BUS < CONFIG_SPACE_CACHESIZE);