.size = 2,
.init_val = 0x0000,
.ro_mask = 0xFF8E,
- .emu_mask = 0x017F,
+ .emu_mask = 0x017E,
.init = pt_msgctrl_reg_init,
.u.w.read = pt_word_reg_read,
.u.w.write = pt_msgctrl_reg_write,
/* modify emulate register */
writable_mask = reg->emu_mask & ~reg->ro_mask & valid_mask;
+ /* also emulate MSI_ENABLE bit for MSI-INTx translation */
+ if (ptdev->msi_trans_en)
+ writable_mask |= PCI_MSI_FLAGS_ENABLE & valid_mask;
cfg_entry->data = PT_MERGE_VALUE(*value, cfg_entry->data, writable_mask);
/* update the msi_info too */
ptdev->msi->flags |= cfg_entry->data &
/* create value for writing to I/O device register */
val = *value;
throughable_mask = ~reg->emu_mask & valid_mask;
+ /* don't pass through MSI_ENABLE bit for MSI-INTx translation */
+ if (ptdev->msi_trans_en)
+ throughable_mask &= ~PCI_MSI_FLAGS_ENABLE;
*value = PT_MERGE_VALUE(*value, dev_value, throughable_mask);
/* update MSI */
else
ptdev->msi->flags &= ~PCI_MSI_FLAGS_ENABLE;
- /* pass through MSI_ENABLE bit when no MSI-INTx translation */
- if (!ptdev->msi_trans_en) {
- *value &= ~PCI_MSI_FLAGS_ENABLE;
- *value |= val & PCI_MSI_FLAGS_ENABLE;
- }
-
return 0;
}