to match net driver update.
Add support for new SFC9000 series NICs
Signed-off-by: Kieran Mansley <kmansley@solarflare.com>
sfc_resource-objs := resource_driver.o iopage.o efx_vi_shm.o \
driverlink_new.o kernel_proc.o kfifo.o \
- nic.o eventq.o falcon.o falcon_mac.o falcon_hash.o \
+ nic.o eventq.o falcon.o falcon_hash.o \
assert_valid.o buddy.o buffer_table.o filter_resource.o \
iobufset_resource.o resource_manager.o resources.o \
vi_resource_alloc.o vi_resource_event.o vi_resource_flush.o \
* This file contains functions to assert validness of resources and
* resource manager in DEBUG build of the resource driver.
*
- * Copyright 2005-2007: Solarflare Communications Inc,
+ * Copyright 2005-2010: Solarflare Communications Inc,
* 9501 Jeronimo Road, Suite 250,
* Irvine, CA 92618, USA
*
_EFRM_ASSERT(rm, file, line);
_EFRM_ASSERT(rm->rm_name, file, line);
_EFRM_ASSERT(rm->rm_type < EFRM_RESOURCE_NUM, file, line);
- _EFRM_ASSERT(rm->rm_table, file, line);
- _EFRM_ASSERT(rm->rm_table_size > 0, file, line);
_EFRM_ASSERT(rm->rm_dtor, file, line);
}
EXPORT_SYMBOL(efrm_resource_manager_assert_valid);
_EFRM_ASSERT(rs, file, line);
if (ref_count_is_zero >= 0) {
- if (!(ref_count_is_zero || atomic_read(&rs->rs_ref_count) > 0)
- || !(!ref_count_is_zero
- || atomic_read(&rs->rs_ref_count) == 0))
+ if (!(ref_count_is_zero || rs->rs_ref_count > 0)
+ || !(!ref_count_is_zero || rs->rs_ref_count == 0))
EFRM_WARN("%s: check %szero ref=%d " EFRM_RESOURCE_FMT,
__FUNCTION__,
ref_count_is_zero == 0 ? "non-" : "",
- atomic_read(&rs->rs_ref_count),
+ rs->rs_ref_count,
EFRM_RESOURCE_PRI_ARG(rs->rs_handle));
_EFRM_ASSERT(!(ref_count_is_zero == 0) ||
- atomic_read(&rs->rs_ref_count) != 0, file, line);
+ rs->rs_ref_count != 0, file, line);
_EFRM_ASSERT(!(ref_count_is_zero > 0) ||
- atomic_read(&rs->rs_ref_count) == 0, file, line);
+ rs->rs_ref_count == 0, file, line);
}
rm = efrm_rm_table[EFRM_RESOURCE_TYPE(rs->rs_handle)];
+
/****************************************************************************
* Driver for Solarflare network controllers -
* resource management for Xen backend, OpenOnload, etc
*
* This file contains implementation of a buddy allocator.
*
- * Copyright 2005-2007: Solarflare Communications Inc,
+ * Copyright 2005-2010: Solarflare Communications Inc,
* 9501 Jeronimo Road, Suite 250,
* Irvine, CA 92618, USA
*
unsigned order, unsigned addr)
{
list_add(&b->links[addr], &b->free_lists[order]);
- b->orders[addr] = (uint8_t) b->order;
+ b->orders[addr] = (uint8_t) order;
}
static inline void
efrm_buddy_free_list_del(struct efrm_buddy_allocator *b, unsigned addr)
if (!efrm_buddy_addr_in_free_list(b, buddy_addr) ||
b->orders[buddy_addr] != order)
break;
- efrm_buddy_free_list_del(b, addr);
+ efrm_buddy_free_list_del(b, buddy_addr);
if (buddy_addr < addr)
addr = buddy_addr;
++order;
("buddy - free %x merged into order %d", addr, order););
efrm_buddy_free_list_add(b, order, addr);
}
-
-void efrm_buddy_reserve_at_start(struct efrm_buddy_allocator *b, unsigned n)
-{
- int addr;
- unsigned o;
- EFRM_DO_DEBUG(int n_save = n);
-
- DEBUG_ALLOC(EFRM_NOTICE("%s(%u)", __FUNCTION__, n));
- EFRM_ASSERT(b);
- EFRM_ASSERT(n <= 1u << b->order && n > 0);
- /* Whole space must be free. */
- EFRM_ASSERT(!efrm_buddy_free_list_empty(b, b->order));
-
- o = fls(n);
-
- while (n) {
- while (((unsigned)1 << o) > n)
- --o;
- EFRM_ASSERT(((unsigned)1 << o) <= n);
- addr = efrm_buddy_alloc(b, o);
- EFRM_ASSERT(addr + (1 << o) <= n_save);
- n -= 1 << o;
- }
-}
-
-static int
-__efrm_buddy_reserve_at_end(struct efrm_buddy_allocator *b, unsigned order,
- int threshold)
-{
- unsigned o, addr;
-
- DEBUG_ALLOC(EFRM_NOTICE("%s(%u, %d)", __FUNCTION__, order, threshold));
- EFRM_ASSERT(b);
-
- /* Find largest block; there must be one big enough (or caller has
- ** goofed).
- */
- for (o = b->order;; --o) {
- if (efrm_buddy_free_list_empty(b, o))
- continue;
- addr = efrm_buddy_free_list_first(b, o);
- if (addr + (1 << o) <= (unsigned)threshold)
- continue;
- break;
- }
- EFRM_ASSERT(o >= order);
-
- /* Split down (keeping second half) until we reach
- * the requested size. */
- addr = efrm_buddy_free_list_pop(b, o);
-
- while (o-- > order) {
- efrm_buddy_free_list_add(b, o, addr);
- addr += 1 << o;
- }
-
- EFRM_DO_DEBUG(b->orders[addr] = (uint8_t) order);
-
- return addr;
-}
-
-void efrm_buddy_reserve_at_end(struct efrm_buddy_allocator *b, unsigned n)
-{
- int addr, threshold;
- unsigned o;
- EFRM_DO_DEBUG(int n_save = n);
-
- DEBUG_ALLOC(EFRM_NOTICE("%s(%u)", __FUNCTION__, n));
- DEBUG_ALLOC(efrm_buddy_dump(b));
- EFRM_ASSERT(b);
- EFRM_ASSERT(n <= 1u << b->order);
-
- if (!n)
- return;
-
- threshold = (1 << b->order) - n;
- o = fls(n);
-
- while (n) {
- while (((unsigned)1 << o) > n)
- --o;
- EFRM_ASSERT(((unsigned)1 << o) <= n);
- addr = __efrm_buddy_reserve_at_end(b, o, threshold);
- EFRM_ASSERT(addr >= (1 << b->order) - n_save);
- n -= 1 << o;
- }
- DEBUG_ALLOC(efrm_buddy_dump(b));
-}
*
* This file contains abstraction of the buffer table on the NIC.
*
- * Copyright 2005-2007: Solarflare Communications Inc,
+ * Copyright 2005-2010: Solarflare Communications Inc,
* 9501 Jeronimo Road, Suite 250,
* Irvine, CA 92618, USA
*
int efrm_buffer_table_ctor(unsigned low, unsigned high)
{
- int log2_n_entries, rc;
+ int log2_n_entries, rc, i;
EFRM_ASSERT(high > 0);
EFRM_ASSERT(low < high);
- EFRM_TRACE("efrm_buffer_table_ctor: low=%u high=%u", low, high);
- EFRM_NOTICE("efrm_buffer_table_ctor: low=%u high=%u", low, high);
+ EFRM_TRACE("%s: low=%u high=%u", __FUNCTION__, low, high);
+ EFRM_NOTICE("%s: low=%u high=%u", __FUNCTION__, low, high);
log2_n_entries = fls(high - 1);
"failed (%d)", log2_n_entries, rc);
return rc;
}
+ for (i = 0; i < (1 << log2_n_entries); ++i) {
+ rc = efrm_buddy_alloc(&efrm_buffers.buddy, 0);
+ EFRM_ASSERT(rc >= 0);
+ EFRM_ASSERT(rc < (1 << log2_n_entries));
+ }
+ for (i = low; i < (int) high; ++i)
+ efrm_buddy_free(&efrm_buffers.buddy, i, 0);
spin_lock_init(&efrm_buffers.lock);
- efrm_buddy_reserve_at_start(&efrm_buffers.buddy, low);
- efrm_buddy_reserve_at_end(&efrm_buffers.buddy,
- (1 << log2_n_entries) - high);
-
- EFRM_TRACE("efrm_buffer_table_ctor: done");
+ EFRM_TRACE("%s: done", __FUNCTION__);
return 0;
}
spin_lock_destroy(&efrm_buffers.lock);
efrm_buddy_dtor(&efrm_buffers.buddy);
- EFRM_TRACE("efrm_buffer_table_dtor: done");
+ EFRM_TRACE("%s: done", __FUNCTION__);
}
/**********************************************************************/
void
efrm_buffer_table_set(struct efhw_buffer_table_allocation *a,
+ struct efhw_nic *nic,
unsigned i, dma_addr_t dma_addr, int owner)
{
- struct efhw_nic *nic;
- int nic_i;
-
EFRM_ASSERT(a);
EFRM_ASSERT(i < (unsigned)1 << a->order);
- EFRM_FOR_EACH_NIC(nic_i, nic)
- efhw_nic_buffer_table_set(nic, dma_addr, EFHW_NIC_PAGE_SIZE,
- 0, owner, a->base + i);
- /* NB. No commit Caller should call efrm_buffer_table_commit. There
- are underlying hardware constraints regarding the number of
- buffer table entries which can be pushed before commiting. */
+
+ efhw_nic_buffer_table_set(nic, dma_addr, EFHW_NIC_PAGE_SIZE,
+ 0, owner, a->base + i);
}
-unsigned long efrm_buffer_table_size(void)
+
+int efrm_buffer_table_size(void)
{
return efrm_buddy_size(&efrm_buffers.buddy);
}
/**********************************************************************/
int
-efrm_page_register(dma_addr_t dma_addr, int owner,
+efrm_page_register(struct efhw_nic *nic, dma_addr_t dma_addr, int owner,
efhw_buffer_addr_t *buf_addr_out)
{
struct efhw_buffer_table_allocation alloc;
rc = efrm_buffer_table_alloc(0, &alloc);
if (rc == 0) {
- efrm_buffer_table_set(&alloc, 0, dma_addr, owner);
+ efrm_buffer_table_set(&alloc, nic, 0, dma_addr, owner);
efrm_buffer_table_commit();
*buf_addr_out = EFHW_BUFFER_ADDR(alloc.base, 0);
}
*
* This file provides EtherFabric NIC hardware interface.
*
- * Copyright 2005-2007: Solarflare Communications Inc,
+ * Copyright 2005-2010: Solarflare Communications Inc,
* 9501 Jeronimo Road, Suite 250,
* Irvine, CA 92618, USA
*
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
****************************************************************************
*/
-
-#ifndef __CI_DRIVER_EFAB_HARDWARE_H__
+#ifdef __CI_DRIVER_EFAB_HARDWARE_H__
+# error This header should only be included directly in .c files
+#endif
#define __CI_DRIVER_EFAB_HARDWARE_H__
-#include "ci/driver/efab/hardware/workarounds.h"
#include <ci/efhw/hardware_sysdep.h>
*
*---------------------------------------------------------------------------*/
+#ifdef USE_OLD_HWDEFS
+#define FR_AA_TIMER_COMMAND_REG_KER_OFST 0x00000420
+#define FR_BZ_TIMER_COMMAND_REGP0_OFST 0x00000420
+#define FR_AB_TIMER_COMMAND_REGP123_OFST 0x01000420
+#define FR_AA_TIMER_COMMAND_REGP0_OFST 0x00008420
+#define FR_AA_TX_DESC_UPD_REG_KER_OFST 0x00000a10
+#define FR_AB_TX_DESC_UPD_REGP123_OFST 0x01000a10
+#define FR_AA_TX_DESC_UPD_REGP0_OFST 0x00008a10
+#define FR_AA_RX_DESC_UPD_REG_KER_OFST 0x00000830
+#define FR_AA_RX_DESC_UPD_REGP0_OFST 0x00008830
+#define FR_AB_RX_DESC_UPD_REGP123_OFST 0x01000830
+#else
+#include "ci/driver/efab/hardware/host_common.h"
+#include "ci/driver/efab/hardware/host_common_pci_defs.h"
+#include "ci/driver/efab/hardware/host_common_mac.h"
+
+#define FR_AA_TX_PACE_TBL_FIRST_QUEUE 4
+#define FR_BZ_TX_PACE_TBL_FIRST_QUEUE 0
+
+#define GEN_MODE_REG_KER 0xC90 /* here in B0 too, but not in headers? */
+ #define DATAPATH_LOOPBACK_EN_SIENA_LBN 4
+ #define DATAPATH_LOOPBACK_EN_SIENA_WIDTH 1
+
+#define SIENA_USER_EV_DECODE 8
+#define SIENA_EVENT_CODE_USER ((uint64_t)SIENA_USER_EV_DECODE << EV_CODE_LBN)
+
+#define SIENA_USER_EV_QID_LBN 32
+#define SIENA_USER_EV_QID_WIDTH 10
+#define SIENA_USER_EV_REG_VALUE_LBN 0
+#define SIENA_USER_EV_REG_VALUE_WIDTH 32
+
+#define SIENA_EVENT_USER_QID_MASK \
+ (__FALCON_OPEN_MASK(SIENA_USER_EV_QID_WIDTH) << SIENA_USER_EV_QID_LBN)
+#define SIENA_EVENT_USER_EV_REG_VALUE_MASK \
+ (__FALCON_OPEN_MASK(SIENA_USER_EV_REG_VALUE_WIDTH) << \
+ SIENA_USER_EV_REG_VALUE_LBN)
+
+#define SIENA_EVENT_USER_Q_ID(evp) \
+ (((evp)->u64 & SIENA_EVENT_USER_QID_MASK) >> \
+ SIENA_USER_EV_QID_LBN)
+
+#define SIENA_EVENT_USER_EV_REG_VALUE(evp) \
+ (((evp)->u64 & SIENA_EVENT_USER_EV_REG_VALUE_MASK) >> \
+ SIENA_USER_EV_REG_VALUE_LBN)
+
+/* Additional constants relevant to Siena only */
+
+#define SIENA_RX_PKT_NOT_PARSED_CUTOFF 2560
+#define SIENA_PORT1_MCPUIND_MAP_OFFSET 0x800000
+
+#endif
#include <ci/driver/efab/hardware/falcon.h>
+#ifndef __KERNEL__
+#include <ci/driver/efab/hardware/falcon_ul.h>
+#endif
+
/*----------------------------------------------------------------------------
*
* EtherFabric Portable Hardware Layer defines
#define efhw_nic_interrupt_disable(nic) \
((nic)->efhw_func->interrupt_disable(nic))
-#define efhw_nic_set_interrupt_moderation(nic, val) \
- ((nic)->efhw_func->set_interrupt_moderation(nic, val))
+#define efhw_nic_set_interrupt_moderation(nic, evq, val) \
+ ((nic)->efhw_func->set_interrupt_moderation(nic, evq, val))
/*-------------- Event support ------------ */
-#define efhw_nic_event_queue_enable(nic, evq, size, q_base, buf_base) \
- ((nic)->efhw_func->event_queue_enable(nic, evq, size, q_base, \
- buf_base))
+#define efhw_nic_event_queue_enable(nic, evq, size, buf_base, interrupting, dos_p) \
+ ((nic)->efhw_func->event_queue_enable((nic), (evq), (size), \
+ (buf_base), (interrupting), (dos_p)))
#define efhw_nic_event_queue_disable(nic, evq, timer_only) \
((nic)->efhw_func->event_queue_disable(nic, evq, timer_only))
-#define efhw_nic_wakeup_request(nic, q_base, index, evq) \
- ((nic)->efhw_func->wakeup_request(nic, q_base, index, evq))
+#define efhw_nic_wakeup_request(nic, rd_ptr, evq) \
+ ((nic)->efhw_func->wakeup_request((nic), (rd_ptr), (evq)))
#define efhw_nic_sw_event(nic, data, ev) \
((nic)->efhw_func->sw_event(nic, data, ev))
((nic)->efhw_func->ipfilter_set(nic, type, index, dmaq, \
saddr, sport, daddr, dport))
-#define efhw_nic_ipfilter_attach(nic, index, dmaq) \
- ((nic)->efhw_func->ipfilter_attach(nic, index, dmaq))
-
-#define efhw_nic_ipfilter_detach(nic, index) \
- ((nic)->efhw_func->ipfilter_detach(nic, index))
-
#define efhw_nic_ipfilter_clear(nic, index) \
((nic)->efhw_func->ipfilter_clear(nic, index))
+#define efhw_nic_ipfilter_redirect(nic, filter_i, rxq_i) \
+ ((nic)->efhw_func->ipfilter_redirect((nic), (filter_i), (rxq_i)))
+
/*-------------- DMA support ------------ */
#define efhw_nic_dmaq_tx_q_init(nic, dmaq, evq, owner, tag, \
dmaq_size, index, flags) \
#define efhw_nic_buffer_table_commit(nic) \
((nic)->efhw_func->buffer_table_commit(nic))
+/*-------------- New filter API ------------ */
+#define efhw_nic_filter_set(nic, spec, index_out) \
+ ((nic)->efhw_func->filter_set(nic, spec, index_out))
+
+#define efhw_nic_filter_clear(nic, type, index_out) \
+ ((nic)->efhw_func->filter_clear(nic, type, index_out))
+
+
/*----------------------------------------------------------------------------
* Hardware specific portability macros for performance critical code.
*
*
*---------------------------------------------------------------------------*/
-#if defined(__CI_HARDWARE_CONFIG_FALCON__)
-
-/* --- DMA --- */
-#define EFHW_DMA_ADDRMASK (0xffffffffffffffffULL)
-
/* --- Buffers --- */
#define EFHW_BUFFER_ADDR FALCON_BUFFER_4K_ADDR
#define EFHW_BUFFER_PAGE FALCON_BUFFER_4K_PAGE
#define EFHW_BUFFER_OFF FALCON_BUFFER_4K_OFF
-/* --- Filters --- */
-#define EFHW_IP_FILTER_NUM FALCON_FILTER_TBL_NUM
-
-#define EFHW_MAX_PAGE_SIZE FALCON_MAX_PAGE_SIZE
-
-#else
-# error no hardware definition found
-#endif
-
#if PAGE_SIZE <= EFHW_MAX_PAGE_SIZE
#define EFHW_NIC_PAGE_SIZE PAGE_SIZE
#else
#define EFHW_NIC_PAGE_SIZE EFHW_MAX_PAGE_SIZE
#endif
#define EFHW_NIC_PAGE_MASK (~(EFHW_NIC_PAGE_SIZE-1))
-
-#endif /* __CI_DRIVER_EFAB_HARDWARE_H__ */
* This file provides EtherFabric NIC hardware interface common
* definitions.
*
- * Copyright 2005-2007: Solarflare Communications Inc,
+ * Copyright 2005-2010: Solarflare Communications Inc,
* 9501 Jeronimo Road, Suite 250,
* Irvine, CA 92618, USA
*
#define EFHW_4G 0x100000000ULL
#define EFHW_8G 0x200000000ULL
+/* --- DMA --- */
+#define EFHW_DMA_ADDRMASK (0xffffffffffffffffULL)
+
+#define EFHW_IP_FILTER_NUM 8192
+#define EFHW_MAX_PAGE_SIZE (EFHW_8K)
+
#endif /* __CI_DRIVER_EFAB_HARDWARE_COMMON_H__ */
* This file provides EtherFabric NIC - EFXXXX (aka Falcon) specific
* definitions.
*
- * Copyright 2005-2007: Solarflare Communications Inc,
+ * Copyright 2005-2010: Solarflare Communications Inc,
* 9501 Jeronimo Road, Suite 250,
* Irvine, CA 92618, USA
*
#define FALCON_MAX_PAGE_SIZE EFHW_8K
/* include the register definitions */
-#include <ci/driver/efab/hardware/falcon/falcon_core.h>
+#ifdef USE_OLD_HWDEFS
+#include <ci/driver/efab/hardware/falcon/falcon_mac.h>
+#endif
#include <ci/driver/efab/hardware/falcon/falcon_desc.h>
#include <ci/driver/efab/hardware/falcon/falcon_event.h>
-#include <ci/driver/efab/hardware/falcon/falcon_mac.h>
#include <ci/driver/efab/hardware/falcon/falcon_grmon.h>
#include <ci/driver/efab/hardware/falcon/falcon_xgrmon.h>
#include <ci/driver/efab/hardware/falcon/falcon_intr_vec.h>
#define FALCON_DMA_RX_PHYS_DESC_BYTES 8
#define FALCON_DMA_RX_BUF_DESC_BYTES 4
-
/* ---- efhw_event_t helpers --- */
#ifndef EFHW_IS_LITTLE_ENDIAN
#define FALCON_EVENT_RX_FLUSH_Q_ID_MASK \
(__FALCON_OPEN_MASK(DRIVER_EV_RX_DESCQ_ID_WIDTH) << \
DRIVER_EV_RX_DESCQ_ID_LBN)
+#define FALCON_EVENT_RX_FLUSH_FAIL_MASK \
+ (__FALCON_OPEN_MASK(DRIVER_EV_RX_FLUSH_FAIL_WIDTH) << \
+ DRIVER_EV_RX_FLUSH_FAIL_LBN)
#define FALCON_EVENT_DRV_SUBCODE_MASK \
(__FALCON_OPEN_MASK(DRIVER_EV_SUB_CODE_WIDTH) << \
DRIVER_EV_SUB_CODE_LBN)
#define FALCON_EVENT_RX_FLUSH_Q_ID(evp) \
(((evp)->u64 & FALCON_EVENT_RX_FLUSH_Q_ID_MASK) >> \
DRIVER_EV_RX_DESCQ_ID_LBN)
+#define FALCON_EVENT_RX_FLUSH_FAIL(evp) \
+ (((evp)->u64 & FALCON_EVENT_RX_FLUSH_FAIL_MASK) >> \
+ DRIVER_EV_RX_FLUSH_FAIL_LBN)
#define FALCON_EVENT_DRIVER_SUBCODE(evp) \
(((evp)->u64 & FALCON_EVENT_DRV_SUBCODE_MASK) >> \
DRIVER_EV_SUB_CODE_LBN)
*
*---------------------------------------------------------------------------*/
-#define FALCON_DMAQ_NUM (EFHW_4K)
-#define FALCON_EVQ_TBL_NUM (EFHW_4K)
-#define FALCON_TIMERS_NUM (EFHW_4K)
+/* Note: the following constants have moved to values in struct efhw_nic
+ * because they are different between Falcon and Siena:
+ * FALCON_EVQ_TBL_NUM -> nic->num_evqs
+ * FALCON_DMAQ_NUM -> nic->num_dmaqs
+ * FALCON_TIMERS_NUM -> nic->num_times
+ * These replacement constants are used as sanity checks in assertions in
+ * certain functions that don't have access to struct efhw_nic. They may
+ * catch some errors but do *not* guarantee a valid value for Siena.
+ */
+#define FALCON_DMAQ_NUM_SANITY (EFHW_4K)
+#define FALCON_EVQ_TBL_NUM_SANITY (EFHW_4K)
+#define FALCON_TIMERS_NUM_SANITY (EFHW_4K)
/* This value is an upper limit on the total number of filter table
- * entries, including odd and even banks. The actual size of filter table
- * is determined at runtime, as it can vary.
+ * entries. The actual size of filter table is determined at runtime, as
+ * it can vary.
*/
-#define FALCON_FILTER_TBL_NUM (EFHW_16K)
+#define FALCON_FILTER_TBL_NUM (EFHW_8K)
/* max number of buffers which can be pushed before commiting */
#define FALCON_BUFFER_UPD_MAX (128)
} s;
};
+/* Ensure DW3 is written last. Outer locking cannot be relied upon to provide
+ * a write barrier
+ */
static inline void
falcon_write_ddd_d(volatile char __iomem *kva,
uint32_t d0, uint32_t d1, uint32_t d2, uint32_t d3)
writel(d2, kva + 8);
mmiowb();
writel(d3, kva + 12);
+ mmiowb();
}
+/* Ensure DW3 is written last. Outer locking cannot be relied upon to provide
+ * a write barrier
+ */
static inline void falcon_write_q(volatile char __iomem *kva, uint64_t q)
{
union __u64to32 u;
writel(u.s.a, kva);
mmiowb();
writel(u.s.b, kva + 4);
+ mmiowb();
}
static inline void falcon_read_q(volatile char __iomem *addr, uint64_t *q0)
* and we get a self consistent value.
*/
union __u64to32 u;
+ /* The CPU must always waits for a read to complete so locked sequences
+ * of reads cannot be interleaved. Lock is outside this function.
+ */
u.s.a = readl(addr);
- rmb();
+ rmb(); /* to stop compiler/CPU re-ordering these two reads*/
u.s.b = readl(addr + 4);
+ rmb(); /* just be safe: so falcon_read_q() can be composed */
*q0 = u.u64;
}
static inline int falcon_timer_page_addr(uint idx)
{
+#ifdef HEADER_REVIEW
+#warning TBD this needs more clean up; the function does not get a version
+#warning the function makes an index range check; this is device dependent
+#endif
+ EFHW_ASSERT(FR_AA_TIMER_COMMAND_REG_KER_OFST ==
+ (FR_AA_TIMER_COMMAND_REGP0_OFST - 4 * EFHW_8K));
- EFHW_ASSERT(TIMER_CMD_REG_KER_OFST ==
- (TIMER_CMD_REG_PAGE4_OFST - 4 * EFHW_8K));
-
- EFHW_ASSERT(idx < FALCON_TIMERS_NUM);
+ EFHW_ASSERT(idx < FALCON_TIMERS_NUM_SANITY);
+ EFHW_ASSERT(FR_BZ_TIMER_COMMAND_REGP0_OFST==
+ FR_AA_TIMER_COMMAND_REG_KER_OFST);
if (idx < 4)
- return TIMER_CMD_REG_KER_OFST + (idx * EFHW_8K);
+ return FR_AA_TIMER_COMMAND_REG_KER_OFST + (idx * EFHW_8K);
else if (idx < 1024)
- return TIMER_CMD_REG_PAGE4_OFST + ((idx - 4) * EFHW_8K);
+ return FR_AA_TIMER_COMMAND_REGP0_OFST + ((idx - 4) * EFHW_8K);
else
- return TIMER_CMD_REG_PAGE123K_OFST + ((idx - 1024) * EFHW_8K);
+ return FR_AB_TIMER_COMMAND_REGP123_OFST + ((idx - 1024) * EFHW_8K);
}
#define FALCON_TIMER_PAGE_MASK (EFHW_8K-1)
static inline uint falcon_tx_dma_page_addr(uint dmaq_idx)
{
uint page;
+#ifdef HEADER_REVIEW
+#warning TBD this needs more clean up; the function does not get a version
+#warning the function makes an index range check; this is device dependent
+#endif
- EFHW_ASSERT((((TX_DESC_UPD_REG_PAGE123K_OFST) & (EFHW_8K - 1)) ==
- (((TX_DESC_UPD_REG_PAGE4_OFST) & (EFHW_8K - 1)))));
+ EFHW_ASSERT((((FR_AB_TX_DESC_UPD_REGP123_OFST) & (EFHW_8K - 1)) ==
+ (((FR_AA_TX_DESC_UPD_REGP0_OFST) & (EFHW_8K - 1)))));
- EFHW_ASSERT(dmaq_idx < FALCON_DMAQ_NUM);
+ EFHW_ASSERT(dmaq_idx < FALCON_DMAQ_NUM_SANITY);
if (dmaq_idx < 1024)
- page = TX_DESC_UPD_REG_PAGE4_OFST + ((dmaq_idx - 4) * EFHW_8K);
+ page = FR_AA_TX_DESC_UPD_REGP0_OFST + ((dmaq_idx - 4) * EFHW_8K);
else
page =
- TX_DESC_UPD_REG_PAGE123K_OFST +
+ FR_AB_TX_DESC_UPD_REGP123_OFST +
((dmaq_idx - 1024) * EFHW_8K);
return page;
static inline uint falcon_rx_dma_page_addr(uint dmaq_idx)
{
uint page;
+#ifdef HEADER_REVIEW
+#warning TBD this needs more clean up; the function does not get a version
+#warning the function makes an index range check; this is device dependent
+#endif
- EFHW_ASSERT((((RX_DESC_UPD_REG_PAGE123K_OFST) & (EFHW_8K - 1)) ==
- ((RX_DESC_UPD_REG_PAGE4_OFST) & (EFHW_8K - 1))));
+ EFHW_ASSERT((((FR_AB_RX_DESC_UPD_REGP123_OFST) & (EFHW_8K - 1)) ==
+ ((FR_AA_RX_DESC_UPD_REGP0_OFST) & (EFHW_8K - 1))));
- EFHW_ASSERT(dmaq_idx < FALCON_DMAQ_NUM);
+ EFHW_ASSERT(dmaq_idx < FALCON_DMAQ_NUM_SANITY);
if (dmaq_idx < 1024)
- page = RX_DESC_UPD_REG_PAGE4_OFST + ((dmaq_idx - 4) * EFHW_8K);
+ page = FR_AA_RX_DESC_UPD_REGP0_OFST + ((dmaq_idx - 4) * EFHW_8K);
else
page =
- RX_DESC_UPD_REG_PAGE123K_OFST +
+ FR_AB_RX_DESC_UPD_REGP123_OFST +
((dmaq_idx - 1024) * EFHW_8K);
return page;
*
*---------------------------------------------------------------------------*/
-/* Falcon nails down the event queue mappings */
-#define FALCON_EVQ_KERNEL0 (0) /* hardwired for net driver */
-#define FALCON_EVQ_CHAR (4) /* char driver's event queue */
-
-/* reserved by the drivers */
-#define FALCON_EVQ_TBL_RESERVED (8)
+#define FALCON_A_EVQ_CHAR (4) /* min evq accessible via char bar */
/* default DMA-Q sizes */
#define FALCON_DMA_Q_DEFAULT_TX_SIZE 512
+++ /dev/null
-/****************************************************************************
- * Driver for Solarflare network controllers -
- * resource management for Xen backend, OpenOnload, etc
- * (including support for SFE4001 10GBT NIC)
- *
- * This file provides EtherFabric NIC - EFXXXX (aka Falcon) core register
- * definitions.
- *
- * Copyright 2005-2007: Solarflare Communications Inc,
- * 9501 Jeronimo Road, Suite 250,
- * Irvine, CA 92618, USA
- *
- * Developed and maintained by Solarflare Communications:
- * <linux-xen-drivers@solarflare.com>
- * <onload-dev@solarflare.com>
- *
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published
- * by the Free Software Foundation, incorporated herein by reference.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- ****************************************************************************
- */
-
-#define FALCON_EXTENDED_P_BAR 1
-
-/*************---- Bus Interface Unit Registers C Header ----*************/
-#define IOM_IND_ADR_REG_OFST 0x0 /* IO-mapped indirect access address
- register */
- #define IOM_AUTO_ADR_INC_EN_LBN 16
- #define IOM_AUTO_ADR_INC_EN_WIDTH 1
- #define IOM_IND_ADR_LBN 0
- #define IOM_IND_ADR_WIDTH 16
-#define IOM_IND_DAT_REG_OFST 0x4 /* IO-mapped indirect access data register */
- #define IOM_IND_DAT_LBN 0
- #define IOM_IND_DAT_WIDTH 32
-#define ADR_REGION_REG_KER_OFST 0x0 /* Address region register */
-#define ADR_REGION_REG_OFST 0x0 /* Address region register */
- #define ADR_REGION3_LBN 96
- #define ADR_REGION3_WIDTH 18
- #define ADR_REGION2_LBN 64
- #define ADR_REGION2_WIDTH 18
- #define ADR_REGION1_LBN 32
- #define ADR_REGION1_WIDTH 18
- #define ADR_REGION0_LBN 0
- #define ADR_REGION0_WIDTH 18
-#define INT_EN_REG_KER_OFST 0x10 /* Kernel driver Interrupt enable register */
- #define KER_INT_CHAR_LBN 4
- #define KER_INT_CHAR_WIDTH 1
- #define KER_INT_KER_LBN 3
- #define KER_INT_KER_WIDTH 1
- #define ILL_ADR_ERR_INT_EN_KER_LBN 2
- #define ILL_ADR_ERR_INT_EN_KER_WIDTH 1
- #define SRM_PERR_INT_EN_KER_LBN 1
- #define SRM_PERR_INT_EN_KER_WIDTH 1
- #define DRV_INT_EN_KER_LBN 0
- #define DRV_INT_EN_KER_WIDTH 1
-#define INT_EN_REG_CHAR_OFST 0x20 /* Char Driver interrupt enable register */
- #define CHAR_INT_CHAR_LBN 4
- #define CHAR_INT_CHAR_WIDTH 1
- #define CHAR_INT_KER_LBN 3
- #define CHAR_INT_KER_WIDTH 1
- #define ILL_ADR_ERR_INT_EN_CHAR_LBN 2
- #define ILL_ADR_ERR_INT_EN_CHAR_WIDTH 1
- #define SRM_PERR_INT_EN_CHAR_LBN 1
- #define SRM_PERR_INT_EN_CHAR_WIDTH 1
- #define DRV_INT_EN_CHAR_LBN 0
- #define DRV_INT_EN_CHAR_WIDTH 1
-#define INT_ADR_REG_KER_OFST 0x30 /* Interrupt host address for Kernel driver */
- #define INT_ADR_KER_LBN 0
- #define INT_ADR_KER_WIDTH 64
- #define DRV_INT_KER_LBN 32
- #define DRV_INT_KER_WIDTH 1
- #define EV_FF_HALF_INT_KER_LBN 3
- #define EV_FF_HALF_INT_KER_WIDTH 1
- #define EV_FF_FULL_INT_KER_LBN 2
- #define EV_FF_FULL_INT_KER_WIDTH 1
- #define ILL_ADR_ERR_INT_KER_LBN 1
- #define ILL_ADR_ERR_INT_KER_WIDTH 1
- #define SRAM_PERR_INT_KER_LBN 0
- #define SRAM_PERR_INT_KER_WIDTH 1
-#define INT_ADR_REG_CHAR_OFST 0x40 /* Interrupt host address for Char driver */
- #define INT_ADR_CHAR_LBN 0
- #define INT_ADR_CHAR_WIDTH 64
- #define DRV_INT_CHAR_LBN 32
- #define DRV_INT_CHAR_WIDTH 1
- #define EV_FF_HALF_INT_CHAR_LBN 3
- #define EV_FF_HALF_INT_CHAR_WIDTH 1
- #define EV_FF_FULL_INT_CHAR_LBN 2
- #define EV_FF_FULL_INT_CHAR_WIDTH 1
- #define ILL_ADR_ERR_INT_CHAR_LBN 1
- #define ILL_ADR_ERR_INT_CHAR_WIDTH 1
- #define SRAM_PERR_INT_CHAR_LBN 0
- #define SRAM_PERR_INT_CHAR_WIDTH 1
-#define INT_ISR0_B0_OFST 0x90 /* B0 only */
-#define INT_ISR1_B0_OFST 0xA0
-#define INT_ACK_REG_KER_A1_OFST 0x50 /* Kernel interrupt acknowledge register */
- #define RESERVED_LBN 0
- #define RESERVED_WIDTH 32
-#define INT_ACK_REG_CHAR_A1_OFST 0x60 /* CHAR interrupt acknowledge register */
- #define RESERVED_LBN 0
- #define RESERVED_WIDTH 32
-/*************---- Global CSR Registers C Header ----*************/
-#define STRAP_REG_KER_OFST 0x200 /* ASIC strap status register */
-#define STRAP_REG_OFST 0x200 /* ASIC strap status register */
- #define ONCHIP_SRAM_LBN 16
- #define ONCHIP_SRAM_WIDTH 0
- #define STRAP_ISCSI_EN_LBN 3
- #define STRAP_ISCSI_EN_WIDTH 1
- #define STRAP_PINS_LBN 0
- #define STRAP_PINS_WIDTH 3
-#define GPIO_CTL_REG_KER_OFST 0x210 /* GPIO control register */
-#define GPIO_CTL_REG_OFST 0x210 /* GPIO control register */
- #define GPIO_OEN_LBN 24
- #define GPIO_OEN_WIDTH 4
- #define GPIO_OUT_LBN 16
- #define GPIO_OUT_WIDTH 4
- #define GPIO_IN_LBN 8
- #define GPIO_IN_WIDTH 4
- #define GPIO_PWRUP_VALUE_LBN 0
- #define GPIO_PWRUP_VALUE_WIDTH 4
-#define GLB_CTL_REG_KER_OFST 0x220 /* Global control register */
-#define GLB_CTL_REG_OFST 0x220 /* Global control register */
- #define SWRST_LBN 0
- #define SWRST_WIDTH 1
-#define FATAL_INTR_REG_KER_OFST 0x230 /* Fatal interrupt register for Kernel */
- #define PCI_BUSERR_INT_KER_EN_LBN 43
- #define PCI_BUSERR_INT_KER_EN_WIDTH 1
- #define SRAM_OOB_INT_KER_EN_LBN 42
- #define SRAM_OOB_INT_KER_EN_WIDTH 1
- #define BUFID_OOB_INT_KER_EN_LBN 41
- #define BUFID_OOB_INT_KER_EN_WIDTH 1
- #define MEM_PERR_INT_KER_EN_LBN 40
- #define MEM_PERR_INT_KER_EN_WIDTH 1
- #define RBUF_OWN_INT_KER_EN_LBN 39
- #define RBUF_OWN_INT_KER_EN_WIDTH 1
- #define TBUF_OWN_INT_KER_EN_LBN 38
- #define TBUF_OWN_INT_KER_EN_WIDTH 1
- #define RDESCQ_OWN_INT_KER_EN_LBN 37
- #define RDESCQ_OWN_INT_KER_EN_WIDTH 1
- #define TDESCQ_OWN_INT_KER_EN_LBN 36
- #define TDESCQ_OWN_INT_KER_EN_WIDTH 1
- #define EVQ_OWN_INT_KER_EN_LBN 35
- #define EVQ_OWN_INT_KER_EN_WIDTH 1
- #define EVFF_OFLO_INT_KER_EN_LBN 34
- #define EVFF_OFLO_INT_KER_EN_WIDTH 1
- #define ILL_ADR_INT_KER_EN_LBN 33
- #define ILL_ADR_INT_KER_EN_WIDTH 1
- #define SRM_PERR_INT_KER_EN_LBN 32
- #define SRM_PERR_INT_KER_EN_WIDTH 1
- #define PCI_BUSERR_INT_KER_LBN 11
- #define PCI_BUSERR_INT_KER_WIDTH 1
- #define SRAM_OOB_INT_KER_LBN 10
- #define SRAM_OOB_INT_KER_WIDTH 1
- #define BUFID_OOB_INT_KER_LBN 9
- #define BUFID_OOB_INT_KER_WIDTH 1
- #define MEM_PERR_INT_KER_LBN 8
- #define MEM_PERR_INT_KER_WIDTH 1
- #define RBUF_OWN_INT_KER_LBN 7
- #define RBUF_OWN_INT_KER_WIDTH 1
- #define TBUF_OWN_INT_KER_LBN 6
- #define TBUF_OWN_INT_KER_WIDTH 1
- #define RDESCQ_OWN_INT_KER_LBN 5
- #define RDESCQ_OWN_INT_KER_WIDTH 1
- #define TDESCQ_OWN_INT_KER_LBN 4
- #define TDESCQ_OWN_INT_KER_WIDTH 1
- #define EVQ_OWN_INT_KER_LBN 3
- #define EVQ_OWN_INT_KER_WIDTH 1
- #define EVFF_OFLO_INT_KER_LBN 2
- #define EVFF_OFLO_INT_KER_WIDTH 1
- #define ILL_ADR_INT_KER_LBN 1
- #define ILL_ADR_INT_KER_WIDTH 1
- #define SRM_PERR_INT_KER_LBN 0
- #define SRM_PERR_INT_KER_WIDTH 1
-#define FATAL_INTR_REG_OFST 0x240 /* Fatal interrupt register for Char */
- #define PCI_BUSERR_INT_CHAR_EN_LBN 43
- #define PCI_BUSERR_INT_CHAR_EN_WIDTH 1
- #define SRAM_OOB_INT_CHAR_EN_LBN 42
- #define SRAM_OOB_INT_CHAR_EN_WIDTH 1
- #define BUFID_OOB_INT_CHAR_EN_LBN 41
- #define BUFID_OOB_INT_CHAR_EN_WIDTH 1
- #define MEM_PERR_INT_CHAR_EN_LBN 40
- #define MEM_PERR_INT_CHAR_EN_WIDTH 1
- #define RBUF_OWN_INT_CHAR_EN_LBN 39
- #define RBUF_OWN_INT_CHAR_EN_WIDTH 1
- #define TBUF_OWN_INT_CHAR_EN_LBN 38
- #define TBUF_OWN_INT_CHAR_EN_WIDTH 1
- #define RDESCQ_OWN_INT_CHAR_EN_LBN 37
- #define RDESCQ_OWN_INT_CHAR_EN_WIDTH 1
- #define TDESCQ_OWN_INT_CHAR_EN_LBN 36
- #define TDESCQ_OWN_INT_CHAR_EN_WIDTH 1
- #define EVQ_OWN_INT_CHAR_EN_LBN 35
- #define EVQ_OWN_INT_CHAR_EN_WIDTH 1
- #define EVFF_OFLO_INT_CHAR_EN_LBN 34
- #define EVFF_OFLO_INT_CHAR_EN_WIDTH 1
- #define ILL_ADR_INT_CHAR_EN_LBN 33
- #define ILL_ADR_INT_CHAR_EN_WIDTH 1
- #define SRM_PERR_INT_CHAR_EN_LBN 32
- #define SRM_PERR_INT_CHAR_EN_WIDTH 1
- #define FATAL_INTR_REG_EN_BITS 0xffffffffffffffffULL
- #define PCI_BUSERR_INT_CHAR_LBN 11
- #define PCI_BUSERR_INT_CHAR_WIDTH 1
- #define SRAM_OOB_INT_CHAR_LBN 10
- #define SRAM_OOB_INT_CHAR_WIDTH 1
- #define BUFID_OOB_INT_CHAR_LBN 9
- #define BUFID_OOB_INT_CHAR_WIDTH 1
- #define MEM_PERR_INT_CHAR_LBN 8
- #define MEM_PERR_INT_CHAR_WIDTH 1
- #define RBUF_OWN_INT_CHAR_LBN 7
- #define RBUF_OWN_INT_CHAR_WIDTH 1
- #define TBUF_OWN_INT_CHAR_LBN 6
- #define TBUF_OWN_INT_CHAR_WIDTH 1
- #define RDESCQ_OWN_INT_CHAR_LBN 5
- #define RDESCQ_OWN_INT_CHAR_WIDTH 1
- #define TDESCQ_OWN_INT_CHAR_LBN 4
- #define TDESCQ_OWN_INT_CHAR_WIDTH 1
- #define EVQ_OWN_INT_CHAR_LBN 3
- #define EVQ_OWN_INT_CHAR_WIDTH 1
- #define EVFF_OFLO_INT_CHAR_LBN 2
- #define EVFF_OFLO_INT_CHAR_WIDTH 1
- #define ILL_ADR_INT_CHAR_LBN 1
- #define ILL_ADR_INT_CHAR_WIDTH 1
- #define SRM_PERR_INT_CHAR_LBN 0
- #define SRM_PERR_INT_CHAR_WIDTH 1
-#define DP_CTRL_REG_OFST 0x250 /* Datapath control register */
- #define FLS_EVQ_ID_LBN 0
- #define FLS_EVQ_ID_WIDTH 12
-#define MEM_STAT_REG_KER_OFST 0x260 /* Memory status register */
-#define MEM_STAT_REG_OFST 0x260 /* Memory status register */
- #define MEM_PERR_VEC_LBN 53
- #define MEM_PERR_VEC_WIDTH 38
- #define MBIST_CORR_LBN 38
- #define MBIST_CORR_WIDTH 15
- #define MBIST_ERR_LBN 0
- #define MBIST_ERR_WIDTH 38
-#define DEBUG_REG_KER_OFST 0x270 /* Debug register */
-#define DEBUG_REG_OFST 0x270 /* Debug register */
- #define DEBUG_BLK_SEL2_LBN 47
- #define DEBUG_BLK_SEL2_WIDTH 3
- #define DEBUG_BLK_SEL1_LBN 44
- #define DEBUG_BLK_SEL1_WIDTH 3
- #define DEBUG_BLK_SEL0_LBN 41
- #define DEBUG_BLK_SEL0_WIDTH 3
- #define MISC_DEBUG_ADDR_LBN 36
- #define MISC_DEBUG_ADDR_WIDTH 5
- #define SERDES_DEBUG_ADDR_LBN 31
- #define SERDES_DEBUG_ADDR_WIDTH 5
- #define EM_DEBUG_ADDR_LBN 26
- #define EM_DEBUG_ADDR_WIDTH 5
- #define SR_DEBUG_ADDR_LBN 21
- #define SR_DEBUG_ADDR_WIDTH 5
- #define EV_DEBUG_ADDR_LBN 16
- #define EV_DEBUG_ADDR_WIDTH 5
- #define RX_DEBUG_ADDR_LBN 11
- #define RX_DEBUG_ADDR_WIDTH 5
- #define TX_DEBUG_ADDR_LBN 6
- #define TX_DEBUG_ADDR_WIDTH 5
- #define BIU_DEBUG_ADDR_LBN 1
- #define BIU_DEBUG_ADDR_WIDTH 5
- #define DEBUG_EN_LBN 0
- #define DEBUG_EN_WIDTH 1
-#define DRIVER_REG0_KER_OFST 0x280 /* Driver scratch register 0 */
-#define DRIVER_REG0_OFST 0x280 /* Driver scratch register 0 */
- #define DRIVER_DW0_LBN 0
- #define DRIVER_DW0_WIDTH 32
-#define DRIVER_REG1_KER_OFST 0x290 /* Driver scratch register 1 */
-#define DRIVER_REG1_OFST 0x290 /* Driver scratch register 1 */
- #define DRIVER_DW1_LBN 0
- #define DRIVER_DW1_WIDTH 32
-#define DRIVER_REG2_KER_OFST 0x2A0 /* Driver scratch register 2 */
-#define DRIVER_REG2_OFST 0x2A0 /* Driver scratch register 2 */
- #define DRIVER_DW2_LBN 0
- #define DRIVER_DW2_WIDTH 32
-#define DRIVER_REG3_KER_OFST 0x2B0 /* Driver scratch register 3 */
-#define DRIVER_REG3_OFST 0x2B0 /* Driver scratch register 3 */
- #define DRIVER_DW3_LBN 0
- #define DRIVER_DW3_WIDTH 32
-#define DRIVER_REG4_KER_OFST 0x2C0 /* Driver scratch register 4 */
-#define DRIVER_REG4_OFST 0x2C0 /* Driver scratch register 4 */
- #define DRIVER_DW4_LBN 0
- #define DRIVER_DW4_WIDTH 32
-#define DRIVER_REG5_KER_OFST 0x2D0 /* Driver scratch register 5 */
-#define DRIVER_REG5_OFST 0x2D0 /* Driver scratch register 5 */
- #define DRIVER_DW5_LBN 0
- #define DRIVER_DW5_WIDTH 32
-#define DRIVER_REG6_KER_OFST 0x2E0 /* Driver scratch register 6 */
-#define DRIVER_REG6_OFST 0x2E0 /* Driver scratch register 6 */
- #define DRIVER_DW6_LBN 0
- #define DRIVER_DW6_WIDTH 32
-#define DRIVER_REG7_KER_OFST 0x2F0 /* Driver scratch register 7 */
-#define DRIVER_REG7_OFST 0x2F0 /* Driver scratch register 7 */
- #define DRIVER_DW7_LBN 0
- #define DRIVER_DW7_WIDTH 32
-#define ALTERA_BUILD_REG_OFST 0x300 /* Altera build register */
-#define ALTERA_BUILD_REG_OFST 0x300 /* Altera build register */
- #define ALTERA_BUILD_VER_LBN 0
- #define ALTERA_BUILD_VER_WIDTH 32
-
-/* so called CSR spare register
- - contains separate parity enable bits for the various internal memory
- blocks */
-#define MEM_PARITY_ERR_EN_REG_KER 0x310
-#define MEM_PARITY_ALL_BLOCKS_EN_LBN 64
-#define MEM_PARITY_ALL_BLOCKS_EN_WIDTH 38
-#define MEM_PARITY_TX_DATA_EN_LBN 72
-#define MEM_PARITY_TX_DATA_EN_WIDTH 2
-
-/*************---- Event & Timer Module Registers C Header ----*************/
-
-#if FALCON_EXTENDED_P_BAR
-#define EVQ_RPTR_REG_KER_OFST 0x11B00 /* Event queue read pointer register */
-#else
-#define EVQ_RPTR_REG_KER_OFST 0x1B00 /* Event queue read pointer register */
-#endif
-
-#define EVQ_RPTR_REG_OFST 0xFA0000 /* Event queue read pointer register
- array. */
- #define EVQ_RPTR_LBN 0
- #define EVQ_RPTR_WIDTH 15
-
-#if FALCON_EXTENDED_P_BAR
-#define EVQ_PTR_TBL_KER_OFST 0x11A00 /* Event queue pointer table for kernel
- access */
-#else
-#define EVQ_PTR_TBL_KER_OFST 0x1A00 /* Event queue pointer table for kernel
- access */
-#endif
-
-#define EVQ_PTR_TBL_CHAR_OFST 0xF60000 /* Event queue pointer table for char
- direct access */
- #define EVQ_WKUP_OR_INT_EN_LBN 39
- #define EVQ_WKUP_OR_INT_EN_WIDTH 1
- #define EVQ_NXT_WPTR_LBN 24
- #define EVQ_NXT_WPTR_WIDTH 15
- #define EVQ_EN_LBN 23
- #define EVQ_EN_WIDTH 1
- #define EVQ_SIZE_LBN 20
- #define EVQ_SIZE_WIDTH 3
- #define EVQ_BUF_BASE_ID_LBN 0
- #define EVQ_BUF_BASE_ID_WIDTH 20
-#define TIMER_CMD_REG_KER_OFST 0x420 /* Timer table for kernel access.
- Page-mapped */
-#define TIMER_CMD_REG_PAGE4_OFST 0x8420 /* Timer table for user-level access.
- Page-mapped. For lowest 1K queues.
- */
-#define TIMER_CMD_REG_PAGE123K_OFST 0x1000420 /* Timer table for user-level
- access. Page-mapped.
- For upper 3K queues. */
-#define TIMER_TBL_OFST 0xF70000 /* Timer table for char driver direct access */
- #define TIMER_MODE_LBN 12
- #define TIMER_MODE_WIDTH 2
- #define TIMER_VAL_LBN 0
- #define TIMER_VAL_WIDTH 12
- #define TIMER_MODE_INT_HLDOFF 2
- #define EVQ_BUF_SIZE_LBN 0
- #define EVQ_BUF_SIZE_WIDTH 1
-#define DRV_EV_REG_KER_OFST 0x440 /* Driver generated event register */
-#define DRV_EV_REG_OFST 0x440 /* Driver generated event register */
- #define DRV_EV_QID_LBN 64
- #define DRV_EV_QID_WIDTH 12
- #define DRV_EV_DATA_LBN 0
- #define DRV_EV_DATA_WIDTH 64
-#define EVQ_CTL_REG_KER_OFST 0x450 /* Event queue control register */
-#define EVQ_CTL_REG_OFST 0x450 /* Event queue control register */
- #define RX_EVQ_WAKEUP_MASK_B0_LBN 15
- #define RX_EVQ_WAKEUP_MASK_B0_WIDTH 6
- #define EVQ_OWNERR_CTL_LBN 14
- #define EVQ_OWNERR_CTL_WIDTH 1
- #define EVQ_FIFO_AF_TH_LBN 8
- #define EVQ_FIFO_AF_TH_WIDTH 6
- #define EVQ_FIFO_NOTAF_TH_LBN 0
- #define EVQ_FIFO_NOTAF_TH_WIDTH 6
-/*************---- SRAM Module Registers C Header ----*************/
-#define BUF_TBL_CFG_REG_KER_OFST 0x600 /* Buffer table configuration register */
-#define BUF_TBL_CFG_REG_OFST 0x600 /* Buffer table configuration register */
- #define BUF_TBL_MODE_LBN 3
- #define BUF_TBL_MODE_WIDTH 1
-#define SRM_RX_DC_CFG_REG_KER_OFST 0x610 /* SRAM receive descriptor cache
- configuration register */
-#define SRM_RX_DC_CFG_REG_OFST 0x610 /* SRAM receive descriptor cache
- configuration register */
- #define SRM_RX_DC_BASE_ADR_LBN 0
- #define SRM_RX_DC_BASE_ADR_WIDTH 21
-#define SRM_TX_DC_CFG_REG_KER_OFST 0x620 /* SRAM transmit descriptor cache
- configuration register */
-#define SRM_TX_DC_CFG_REG_OFST 0x620 /* SRAM transmit descriptor cache
- configuration register */
- #define SRM_TX_DC_BASE_ADR_LBN 0
- #define SRM_TX_DC_BASE_ADR_WIDTH 21
-#define SRM_CFG_REG_KER_OFST 0x630 /* SRAM configuration register */
-#define SRM_CFG_REG_OFST 0x630 /* SRAM configuration register */
- #define SRAM_OOB_ADR_INTEN_LBN 5
- #define SRAM_OOB_ADR_INTEN_WIDTH 1
- #define SRAM_OOB_BUF_INTEN_LBN 4
- #define SRAM_OOB_BUF_INTEN_WIDTH 1
- #define SRAM_BT_INIT_EN_LBN 3
- #define SRAM_BT_INIT_EN_WIDTH 1
- #define SRM_NUM_BANK_LBN 2
- #define SRM_NUM_BANK_WIDTH 1
- #define SRM_BANK_SIZE_LBN 0
- #define SRM_BANK_SIZE_WIDTH 2
-#define BUF_TBL_UPD_REG_KER_OFST 0x650 /* Buffer table update register */
-#define BUF_TBL_UPD_REG_OFST 0x650 /* Buffer table update register */
- #define BUF_UPD_CMD_LBN 63
- #define BUF_UPD_CMD_WIDTH 1
- #define BUF_CLR_CMD_LBN 62
- #define BUF_CLR_CMD_WIDTH 1
- #define BUF_CLR_END_ID_LBN 32
- #define BUF_CLR_END_ID_WIDTH 20
- #define BUF_CLR_START_ID_LBN 0
- #define BUF_CLR_START_ID_WIDTH 20
-#define SRM_UPD_EVQ_REG_KER_OFST 0x660 /* Buffer table update register */
-#define SRM_UPD_EVQ_REG_OFST 0x660 /* Buffer table update register */
- #define SRM_UPD_EVQ_ID_LBN 0
- #define SRM_UPD_EVQ_ID_WIDTH 12
-#define SRAM_PARITY_REG_KER_OFST 0x670 /* SRAM parity register. */
-#define SRAM_PARITY_REG_OFST 0x670 /* SRAM parity register. */
- #define FORCE_SRAM_PERR_LBN 0
- #define FORCE_SRAM_PERR_WIDTH 1
-
-#if FALCON_EXTENDED_P_BAR
-#define BUF_HALF_TBL_KER_OFST 0x18000 /* Buffer table in half buffer table
- mode direct access by kernel driver */
-#else
-#define BUF_HALF_TBL_KER_OFST 0x8000 /* Buffer table in half buffer table
- mode direct access by kernel driver */
-#endif
-
-
-#define BUF_HALF_TBL_OFST 0x800000 /* Buffer table in half buffer table mode
- direct access by char driver */
- #define BUF_ADR_HBUF_ODD_LBN 44
- #define BUF_ADR_HBUF_ODD_WIDTH 20
- #define BUF_OWNER_ID_HBUF_ODD_LBN 32
- #define BUF_OWNER_ID_HBUF_ODD_WIDTH 12
- #define BUF_ADR_HBUF_EVEN_LBN 12
- #define BUF_ADR_HBUF_EVEN_WIDTH 20
- #define BUF_OWNER_ID_HBUF_EVEN_LBN 0
- #define BUF_OWNER_ID_HBUF_EVEN_WIDTH 12
-
-
-#if FALCON_EXTENDED_P_BAR
-#define BUF_FULL_TBL_KER_OFST 0x18000 /* Buffer table in full buffer table
- mode direct access by kernel driver */
-#else
-#define BUF_FULL_TBL_KER_OFST 0x8000 /* Buffer table in full buffer table mode
- direct access by kernel driver */
-#endif
-
-
-
-
-#define BUF_FULL_TBL_OFST 0x800000 /* Buffer table in full buffer table mode
- direct access by char driver */
- #define IP_DAT_BUF_SIZE_LBN 50
- #define IP_DAT_BUF_SIZE_WIDTH 1
- #define BUF_ADR_REGION_LBN 48
- #define BUF_ADR_REGION_WIDTH 2
- #define BUF_ADR_FBUF_LBN 14
- #define BUF_ADR_FBUF_WIDTH 34
- #define BUF_OWNER_ID_FBUF_LBN 0
- #define BUF_OWNER_ID_FBUF_WIDTH 14
-#define SRM_DBG_REG_OFST 0x3000000 /* SRAM debug access */
- #define SRM_DBG_LBN 0
- #define SRM_DBG_WIDTH 64
-/*************---- RX Datapath Registers C Header ----*************/
-
-#define RX_CFG_REG_KER_OFST 0x800 /* Receive configuration register */
-#define RX_CFG_REG_OFST 0x800 /* Receive configuration register */
-
-#if !defined(FALCON_64K_RXFIFO) && !defined(FALCON_PRE_02020029)
-# if !defined(FALCON_128K_RXFIFO)
-# define FALCON_128K_RXFIFO
-# endif
-#endif
-
-#if defined(FALCON_128K_RXFIFO)
-
-/* new for B0 */
- #define RX_TOEP_TCP_SUPPRESS_B0_LBN 48
- #define RX_TOEP_TCP_SUPPRESS_B0_WIDTH 1
- #define RX_INGR_EN_B0_LBN 47
- #define RX_INGR_EN_B0_WIDTH 1
- #define RX_TOEP_IPV4_B0_LBN 46
- #define RX_TOEP_IPV4_B0_WIDTH 1
- #define RX_HASH_ALG_B0_LBN 45
- #define RX_HASH_ALG_B0_WIDTH 1
- #define RX_HASH_INSERT_HDR_B0_LBN 44
- #define RX_HASH_INSERT_HDR_B0_WIDTH 1
-/* moved for B0 */
- #define RX_DESC_PUSH_EN_B0_LBN 43
- #define RX_DESC_PUSH_EN_B0_WIDTH 1
- #define RX_RDW_PATCH_EN_LBN 42 /* Non head of line blocking */
- #define RX_RDW_PATCH_EN_WIDTH 1
- #define RX_PCI_BURST_SIZE_B0_LBN 39
- #define RX_PCI_BURST_SIZE_B0_WIDTH 3
- #define RX_OWNERR_CTL_B0_LBN 38
- #define RX_OWNERR_CTL_B0_WIDTH 1
- #define RX_XON_TX_TH_B0_LBN 33
- #define RX_XON_TX_TH_B0_WIDTH 5
- #define RX_XOFF_TX_TH_B0_LBN 28
- #define RX_XOFF_TX_TH_B0_WIDTH 5
- #define RX_USR_BUF_SIZE_B0_LBN 19
- #define RX_USR_BUF_SIZE_B0_WIDTH 9
- #define RX_XON_MAC_TH_B0_LBN 10
- #define RX_XON_MAC_TH_B0_WIDTH 9
- #define RX_XOFF_MAC_TH_B0_LBN 1
- #define RX_XOFF_MAC_TH_B0_WIDTH 9
- #define RX_XOFF_MAC_EN_B0_LBN 0
- #define RX_XOFF_MAC_EN_B0_WIDTH 1
-
-#elif !defined(FALCON_PRE_02020029)
-/* new for B0 */
- #define RX_TOEP_TCP_SUPPRESS_B0_LBN 46
- #define RX_TOEP_TCP_SUPPRESS_B0_WIDTH 1
- #define RX_INGR_EN_B0_LBN 45
- #define RX_INGR_EN_B0_WIDTH 1
- #define RX_TOEP_IPV4_B0_LBN 44
- #define RX_TOEP_IPV4_B0_WIDTH 1
- #define RX_HASH_ALG_B0_LBN 43
- #define RX_HASH_ALG_B0_WIDTH 41
- #define RX_HASH_INSERT_HDR_B0_LBN 42
- #define RX_HASH_INSERT_HDR_B0_WIDTH 1
-/* moved for B0 */
- #define RX_DESC_PUSH_EN_B0_LBN 41
- #define RX_DESC_PUSH_EN_B0_WIDTH 1
- #define RX_PCI_BURST_SIZE_B0_LBN 37
- #define RX_PCI_BURST_SIZE_B0_WIDTH 3
- #define RX_OWNERR_CTL_B0_LBN 36
- #define RX_OWNERR_CTL_B0_WIDTH 1
- #define RX_XON_TX_TH_B0_LBN 31
- #define RX_XON_TX_TH_B0_WIDTH 5
- #define RX_XOFF_TX_TH_B0_LBN 26
- #define RX_XOFF_TX_TH_B0_WIDTH 5
- #define RX_USR_BUF_SIZE_B0_LBN 17
- #define RX_USR_BUF_SIZE_B0_WIDTH 9
- #define RX_XON_MAC_TH_B0_LBN 9
- #define RX_XON_MAC_TH_B0_WIDTH 8
- #define RX_XOFF_MAC_TH_B0_LBN 1
- #define RX_XOFF_MAC_TH_B0_WIDTH 8
- #define RX_XOFF_MAC_EN_B0_LBN 0
- #define RX_XOFF_MAC_EN_B0_WIDTH 1
-
-#else
-/* new for B0 */
- #define RX_TOEP_TCP_SUPPRESS_B0_LBN 44
- #define RX_TOEP_TCP_SUPPRESS_B0_WIDTH 1
- #define RX_INGR_EN_B0_LBN 43
- #define RX_INGR_EN_B0_WIDTH 1
- #define RX_TOEP_IPV4_B0_LBN 42
- #define RX_TOEP_IPV4_B0_WIDTH 1
- #define RX_HASH_ALG_B0_LBN 41
- #define RX_HASH_ALG_B0_WIDTH 41
- #define RX_HASH_INSERT_HDR_B0_LBN 40
- #define RX_HASH_INSERT_HDR_B0_WIDTH 1
-/* moved for B0 */
- #define RX_DESC_PUSH_EN_B0_LBN 35
- #define RX_DESC_PUSH_EN_B0_WIDTH 1
- #define RX_PCI_BURST_SIZE_B0_LBN 35
- #define RX_PCI_BURST_SIZE_B0_WIDTH 2
- #define RX_OWNERR_CTL_B0_LBN 34
- #define RX_OWNERR_CTL_B0_WIDTH 1
- #define RX_XON_TX_TH_B0_LBN 29
- #define RX_XON_TX_TH_B0_WIDTH 5
- #define RX_XOFF_TX_TH_B0_LBN 24
- #define RX_XOFF_TX_TH_B0_WIDTH 5
- #define RX_USR_BUF_SIZE_B0_LBN 15
- #define RX_USR_BUF_SIZE_B0_WIDTH 9
- #define RX_XON_MAC_TH_B0_LBN 8
- #define RX_XON_MAC_TH_B0_WIDTH 7
- #define RX_XOFF_MAC_TH_B0_LBN 1
- #define RX_XOFF_MAC_TH_B0_WIDTH 7
- #define RX_XOFF_MAC_EN_B0_LBN 0
- #define RX_XOFF_MAC_EN_B0_WIDTH 1
-
-#endif
-
-/* A0/A1 */
- #define RX_PUSH_EN_A1_LBN 35
- #define RX_PUSH_EN_A1_WIDTH 1
- #define RX_PCI_BURST_SIZE_A1_LBN 31
- #define RX_PCI_BURST_SIZE_A1_WIDTH 3
- #define RX_OWNERR_CTL_A1_LBN 30
- #define RX_OWNERR_CTL_A1_WIDTH 1
- #define RX_XON_TX_TH_A1_LBN 25
- #define RX_XON_TX_TH_A1_WIDTH 5
- #define RX_XOFF_TX_TH_A1_LBN 20
- #define RX_XOFF_TX_TH_A1_WIDTH 5
- #define RX_USR_BUF_SIZE_A1_LBN 11
- #define RX_USR_BUF_SIZE_A1_WIDTH 9
- #define RX_XON_MAC_TH_A1_LBN 6
- #define RX_XON_MAC_TH_A1_WIDTH 5
- #define RX_XOFF_MAC_TH_A1_LBN 1
- #define RX_XOFF_MAC_TH_A1_WIDTH 5
- #define RX_XOFF_MAC_EN_A1_LBN 0
- #define RX_XOFF_MAC_EN_A1_WIDTH 1
-
-#define RX_FILTER_CTL_REG_OFST 0x810 /* Receive filter control registers */
- #define SCATTER_ENBL_NO_MATCH_Q_B0_LBN 40
- #define SCATTER_ENBL_NO_MATCH_Q_B0_WIDTH 1
- #define UDP_FULL_SRCH_LIMIT_LBN 32
- #define UDP_FULL_SRCH_LIMIT_WIDTH 8
- #define NUM_KER_LBN 24
- #define NUM_KER_WIDTH 2
- #define UDP_WILD_SRCH_LIMIT_LBN 16
- #define UDP_WILD_SRCH_LIMIT_WIDTH 8
- #define TCP_WILD_SRCH_LIMIT_LBN 8
- #define TCP_WILD_SRCH_LIMIT_WIDTH 8
- #define TCP_FULL_SRCH_LIMIT_LBN 0
- #define TCP_FULL_SRCH_LIMIT_WIDTH 8
-#define RX_FLUSH_DESCQ_REG_KER_OFST 0x820 /* Receive flush descriptor queue
- register */
-#define RX_FLUSH_DESCQ_REG_OFST 0x820 /* Receive flush descriptor queue
- register */
- #define RX_FLUSH_DESCQ_CMD_LBN 24
- #define RX_FLUSH_DESCQ_CMD_WIDTH 1
- #define RX_FLUSH_EVQ_ID_LBN 12
- #define RX_FLUSH_EVQ_ID_WIDTH 12
- #define RX_FLUSH_DESCQ_LBN 0
- #define RX_FLUSH_DESCQ_WIDTH 12
-#define RX_DESC_UPD_REG_KER_OFST 0x830 /* Kernel receive descriptor update
- register. Page-mapped */
-#define RX_DESC_UPD_REG_PAGE4_OFST 0x8830 /* Char & user receive descriptor
- update register. Page-mapped.
- For lowest 1K queues. */
-#define RX_DESC_UPD_REG_PAGE123K_OFST 0x1000830 /* Char & user receive
- descriptor update register.
- Page-mapped. For upper
- 3K queues. */
- #define RX_DESC_WPTR_LBN 96
- #define RX_DESC_WPTR_WIDTH 12
- #define RX_DESC_PUSH_CMD_LBN 95
- #define RX_DESC_PUSH_CMD_WIDTH 1
- #define RX_DESC_LBN 0
- #define RX_DESC_WIDTH 64
- #define RX_KER_DESC_LBN 0
- #define RX_KER_DESC_WIDTH 64
- #define RX_USR_DESC_LBN 0
- #define RX_USR_DESC_WIDTH 32
-#define RX_DC_CFG_REG_KER_OFST 0x840 /* Receive descriptor cache
- configuration register */
-#define RX_DC_CFG_REG_OFST 0x840 /* Receive descriptor cache
- configuration register */
- #define RX_DC_SIZE_LBN 0
- #define RX_DC_SIZE_WIDTH 2
-#define RX_DC_PF_WM_REG_KER_OFST 0x850 /* Receive descriptor cache pre-fetch
- watermark register */
-#define RX_DC_PF_WM_REG_OFST 0x850 /* Receive descriptor cache pre-fetch
- watermark register */
- #define RX_DC_PF_LWM_LO_LBN 0
- #define RX_DC_PF_LWM_LO_WIDTH 6
-
-#define RX_RSS_TKEY_B0_OFST 0x860 /* RSS Toeplitz hash key (B0 only) */
-
-#define RX_NODESC_DROP_REG 0x880
- #define RX_NODESC_DROP_CNT_LBN 0
- #define RX_NODESC_DROP_CNT_WIDTH 16
-
-#define XM_TX_CFG_REG_OFST 0x1230
- #define XM_AUTO_PAD_LBN 5
- #define XM_AUTO_PAD_WIDTH 1
-
-#define RX_FILTER_TBL0_OFST 0xF00000 /* Receive filter table - even entries */
- #define RSS_EN_0_B0_LBN 110
- #define RSS_EN_0_B0_WIDTH 1
- #define SCATTER_EN_0_B0_LBN 109
- #define SCATTER_EN_0_B0_WIDTH 1
- #define TCP_UDP_0_LBN 108
- #define TCP_UDP_0_WIDTH 1
- #define RXQ_ID_0_LBN 96
- #define RXQ_ID_0_WIDTH 12
- #define DEST_IP_0_LBN 64
- #define DEST_IP_0_WIDTH 32
- #define DEST_PORT_TCP_0_LBN 48
- #define DEST_PORT_TCP_0_WIDTH 16
- #define SRC_IP_0_LBN 16
- #define SRC_IP_0_WIDTH 32
- #define SRC_TCP_DEST_UDP_0_LBN 0
- #define SRC_TCP_DEST_UDP_0_WIDTH 16
-#define RX_FILTER_TBL1_OFST 0xF00010 /* Receive filter table - odd entries */
- #define RSS_EN_1_B0_LBN 110
- #define RSS_EN_1_B0_WIDTH 1
- #define SCATTER_EN_1_B0_LBN 109
- #define SCATTER_EN_1_B0_WIDTH 1
- #define TCP_UDP_1_LBN 108
- #define TCP_UDP_1_WIDTH 1
- #define RXQ_ID_1_LBN 96
- #define RXQ_ID_1_WIDTH 12
- #define DEST_IP_1_LBN 64
- #define DEST_IP_1_WIDTH 32
- #define DEST_PORT_TCP_1_LBN 48
- #define DEST_PORT_TCP_1_WIDTH 16
- #define SRC_IP_1_LBN 16
- #define SRC_IP_1_WIDTH 32
- #define SRC_TCP_DEST_UDP_1_LBN 0
- #define SRC_TCP_DEST_UDP_1_WIDTH 16
-
-#if FALCON_EXTENDED_P_BAR
-#define RX_DESC_PTR_TBL_KER_OFST 0x11800 /* Receive descriptor pointer
- kernel access */
-#else
-#define RX_DESC_PTR_TBL_KER_OFST 0x1800 /* Receive descriptor pointer
- kernel access */
-#endif
-
-
-#define RX_DESC_PTR_TBL_OFST 0xF40000 /* Receive descriptor pointer table */
- #define RX_ISCSI_DDIG_EN_LBN 88
- #define RX_ISCSI_DDIG_EN_WIDTH 1
- #define RX_ISCSI_HDIG_EN_LBN 87
- #define RX_ISCSI_HDIG_EN_WIDTH 1
- #define RX_DESC_PREF_ACT_LBN 86
- #define RX_DESC_PREF_ACT_WIDTH 1
- #define RX_DC_HW_RPTR_LBN 80
- #define RX_DC_HW_RPTR_WIDTH 6
- #define RX_DESCQ_HW_RPTR_LBN 68
- #define RX_DESCQ_HW_RPTR_WIDTH 12
- #define RX_DESCQ_SW_WPTR_LBN 56
- #define RX_DESCQ_SW_WPTR_WIDTH 12
- #define RX_DESCQ_BUF_BASE_ID_LBN 36
- #define RX_DESCQ_BUF_BASE_ID_WIDTH 20
- #define RX_DESCQ_EVQ_ID_LBN 24
- #define RX_DESCQ_EVQ_ID_WIDTH 12
- #define RX_DESCQ_OWNER_ID_LBN 10
- #define RX_DESCQ_OWNER_ID_WIDTH 14
- #define RX_DESCQ_LABEL_LBN 5
- #define RX_DESCQ_LABEL_WIDTH 5
- #define RX_DESCQ_SIZE_LBN 3
- #define RX_DESCQ_SIZE_WIDTH 2
- #define RX_DESCQ_TYPE_LBN 2
- #define RX_DESCQ_TYPE_WIDTH 1
- #define RX_DESCQ_JUMBO_LBN 1
- #define RX_DESCQ_JUMBO_WIDTH 1
- #define RX_DESCQ_EN_LBN 0
- #define RX_DESCQ_EN_WIDTH 1
-
-
-#define RX_RSS_INDIR_TBL_B0_OFST 0xFB0000 /* RSS indirection table (B0 only) */
- #define RX_RSS_INDIR_ENT_B0_LBN 0
- #define RX_RSS_INDIR_ENT_B0_WIDTH 6
-
-/*************---- TX Datapath Registers C Header ----*************/
-#define TX_FLUSH_DESCQ_REG_KER_OFST 0xA00 /* Transmit flush descriptor
- queue register */
-#define TX_FLUSH_DESCQ_REG_OFST 0xA00 /* Transmit flush descriptor queue
- register */
- #define TX_FLUSH_DESCQ_CMD_LBN 12
- #define TX_FLUSH_DESCQ_CMD_WIDTH 1
- #define TX_FLUSH_DESCQ_LBN 0
- #define TX_FLUSH_DESCQ_WIDTH 12
-#define TX_DESC_UPD_REG_KER_OFST 0xA10 /* Kernel transmit descriptor update
- register. Page-mapped */
-#define TX_DESC_UPD_REG_PAGE4_OFST 0x8A10 /* Char & user transmit descriptor
- update register. Page-mapped */
-#define TX_DESC_UPD_REG_PAGE123K_OFST 0x1000A10 /* Char & user transmit
- descriptor update register.
- Page-mapped */
- #define TX_DESC_WPTR_LBN 96
- #define TX_DESC_WPTR_WIDTH 12
- #define TX_DESC_PUSH_CMD_LBN 95
- #define TX_DESC_PUSH_CMD_WIDTH 1
- #define TX_DESC_LBN 0
- #define TX_DESC_WIDTH 95
- #define TX_KER_DESC_LBN 0
- #define TX_KER_DESC_WIDTH 64
- #define TX_USR_DESC_LBN 0
- #define TX_USR_DESC_WIDTH 64
-#define TX_DC_CFG_REG_KER_OFST 0xA20 /* Transmit descriptor cache
- configuration register */
-#define TX_DC_CFG_REG_OFST 0xA20 /* Transmit descriptor cache configuration
- register */
- #define TX_DC_SIZE_LBN 0
- #define TX_DC_SIZE_WIDTH 2
-
-#if FALCON_EXTENDED_P_BAR
-#define TX_DESC_PTR_TBL_KER_OFST 0x11900 /* Transmit descriptor pointer. */
-#else
-#define TX_DESC_PTR_TBL_KER_OFST 0x1900 /* Transmit descriptor pointer. */
-#endif
-
-
-#define TX_DESC_PTR_TBL_OFST 0xF50000 /* Transmit descriptor pointer */
- #define TX_NON_IP_DROP_DIS_B0_LBN 91
- #define TX_NON_IP_DROP_DIS_B0_WIDTH 1
- #define TX_IP_CHKSM_DIS_B0_LBN 90
- #define TX_IP_CHKSM_DIS_B0_WIDTH 1
- #define TX_TCP_CHKSM_DIS_B0_LBN 89
- #define TX_TCP_CHKSM_DIS_B0_WIDTH 1
- #define TX_DESCQ_EN_LBN 88
- #define TX_DESCQ_EN_WIDTH 1
- #define TX_ISCSI_DDIG_EN_LBN 87
- #define TX_ISCSI_DDIG_EN_WIDTH 1
- #define TX_ISCSI_HDIG_EN_LBN 86
- #define TX_ISCSI_HDIG_EN_WIDTH 1
- #define TX_DC_HW_RPTR_LBN 80
- #define TX_DC_HW_RPTR_WIDTH 6
- #define TX_DESCQ_HW_RPTR_LBN 68
- #define TX_DESCQ_HW_RPTR_WIDTH 12
- #define TX_DESCQ_SW_WPTR_LBN 56
- #define TX_DESCQ_SW_WPTR_WIDTH 12
- #define TX_DESCQ_BUF_BASE_ID_LBN 36
- #define TX_DESCQ_BUF_BASE_ID_WIDTH 20
- #define TX_DESCQ_EVQ_ID_LBN 24
- #define TX_DESCQ_EVQ_ID_WIDTH 12
- #define TX_DESCQ_OWNER_ID_LBN 10
- #define TX_DESCQ_OWNER_ID_WIDTH 14
- #define TX_DESCQ_LABEL_LBN 5
- #define TX_DESCQ_LABEL_WIDTH 5
- #define TX_DESCQ_SIZE_LBN 3
- #define TX_DESCQ_SIZE_WIDTH 2
- #define TX_DESCQ_TYPE_LBN 1
- #define TX_DESCQ_TYPE_WIDTH 2
- #define TX_DESCQ_FLUSH_LBN 0
- #define TX_DESCQ_FLUSH_WIDTH 1
-#define TX_CFG_REG_KER_OFST 0xA50 /* Transmit configuration register */
-#define TX_CFG_REG_OFST 0xA50 /* Transmit configuration register */
- #define TX_IP_ID_P1_OFS_LBN 32
- #define TX_IP_ID_P1_OFS_WIDTH 15
- #define TX_IP_ID_P0_OFS_LBN 16
- #define TX_IP_ID_P0_OFS_WIDTH 15
- #define TX_TURBO_EN_LBN 3
- #define TX_TURBO_EN_WIDTH 1
- #define TX_OWNERR_CTL_LBN 2
- #define TX_OWNERR_CTL_WIDTH 2
- #define TX_NON_IP_DROP_DIS_LBN 1
- #define TX_NON_IP_DROP_DIS_WIDTH 1
- #define TX_IP_ID_REP_EN_LBN 0
- #define TX_IP_ID_REP_EN_WIDTH 1
-#define TX_RESERVED_REG_KER_OFST 0xA80 /* Transmit configuration register */
-#define TX_RESERVED_REG_OFST 0xA80 /* Transmit configuration register */
- #define TX_CSR_PUSH_EN_LBN 89
- #define TX_CSR_PUSH_EN_WIDTH 1
- #define TX_RX_SPACER_LBN 64
- #define TX_RX_SPACER_WIDTH 8
- #define TX_SW_EV_EN_LBN 59
- #define TX_SW_EV_EN_WIDTH 1
- #define TX_RX_SPACER_EN_LBN 57
- #define TX_RX_SPACER_EN_WIDTH 1
- #define TX_CSR_PREF_WD_TMR_LBN 24
- #define TX_CSR_PREF_WD_TMR_WIDTH 16
- #define TX_CSR_ONLY1TAG_LBN 21
- #define TX_CSR_ONLY1TAG_WIDTH 1
- #define TX_PREF_THRESHOLD_LBN 19
- #define TX_PREF_THRESHOLD_WIDTH 2
- #define TX_ONE_PKT_PER_Q_LBN 18
- #define TX_ONE_PKT_PER_Q_WIDTH 1
- #define TX_DIS_NON_IP_EV_LBN 17
- #define TX_DIS_NON_IP_EV_WIDTH 1
- #define TX_DMA_SPACER_LBN 8
- #define TX_DMA_SPACER_WIDTH 8
- #define TX_FLUSH_MIN_LEN_EN_B0_LBN 7
- #define TX_FLUSH_MIN_LEN_EN_B0_WIDTH 1
- #define TX_TCP_DIS_A1_LBN 7
- #define TX_TCP_DIS_A1_WIDTH 1
- #define TX_IP_DIS_A1_LBN 6
- #define TX_IP_DIS_A1_WIDTH 1
- #define TX_MAX_CPL_LBN 2
- #define TX_MAX_CPL_WIDTH 2
- #define TX_MAX_PREF_LBN 0
- #define TX_MAX_PREF_WIDTH 2
-#define TX_VLAN_REG_OFST 0xAE0 /* Transmit VLAN tag register */
- #define TX_VLAN_EN_LBN 127
- #define TX_VLAN_EN_WIDTH 1
- #define TX_VLAN7_PORT1_EN_LBN 125
- #define TX_VLAN7_PORT1_EN_WIDTH 1
- #define TX_VLAN7_PORT0_EN_LBN 124
- #define TX_VLAN7_PORT0_EN_WIDTH 1
- #define TX_VLAN7_LBN 112
- #define TX_VLAN7_WIDTH 12
- #define TX_VLAN6_PORT1_EN_LBN 109
- #define TX_VLAN6_PORT1_EN_WIDTH 1
- #define TX_VLAN6_PORT0_EN_LBN 108
- #define TX_VLAN6_PORT0_EN_WIDTH 1
- #define TX_VLAN6_LBN 96
- #define TX_VLAN6_WIDTH 12
- #define TX_VLAN5_PORT1_EN_LBN 93
- #define TX_VLAN5_PORT1_EN_WIDTH 1
- #define TX_VLAN5_PORT0_EN_LBN 92
- #define TX_VLAN5_PORT0_EN_WIDTH 1
- #define TX_VLAN5_LBN 80
- #define TX_VLAN5_WIDTH 12
- #define TX_VLAN4_PORT1_EN_LBN 77
- #define TX_VLAN4_PORT1_EN_WIDTH 1
- #define TX_VLAN4_PORT0_EN_LBN 76
- #define TX_VLAN4_PORT0_EN_WIDTH 1
- #define TX_VLAN4_LBN 64
- #define TX_VLAN4_WIDTH 12
- #define TX_VLAN3_PORT1_EN_LBN 61
- #define TX_VLAN3_PORT1_EN_WIDTH 1
- #define TX_VLAN3_PORT0_EN_LBN 60
- #define TX_VLAN3_PORT0_EN_WIDTH 1
- #define TX_VLAN3_LBN 48
- #define TX_VLAN3_WIDTH 12
- #define TX_VLAN2_PORT1_EN_LBN 45
- #define TX_VLAN2_PORT1_EN_WIDTH 1
- #define TX_VLAN2_PORT0_EN_LBN 44
- #define TX_VLAN2_PORT0_EN_WIDTH 1
- #define TX_VLAN2_LBN 32
- #define TX_VLAN2_WIDTH 12
- #define TX_VLAN1_PORT1_EN_LBN 29
- #define TX_VLAN1_PORT1_EN_WIDTH 1
- #define TX_VLAN1_PORT0_EN_LBN 28
- #define TX_VLAN1_PORT0_EN_WIDTH 1
- #define TX_VLAN1_LBN 16
- #define TX_VLAN1_WIDTH 12
- #define TX_VLAN0_PORT1_EN_LBN 13
- #define TX_VLAN0_PORT1_EN_WIDTH 1
- #define TX_VLAN0_PORT0_EN_LBN 12
- #define TX_VLAN0_PORT0_EN_WIDTH 1
- #define TX_VLAN0_LBN 0
- #define TX_VLAN0_WIDTH 12
-#define TX_FIL_CTL_REG_OFST 0xAF0 /* Transmit filter control register */
- #define TX_MADR1_FIL_EN_LBN 65
- #define TX_MADR1_FIL_EN_WIDTH 1
- #define TX_MADR0_FIL_EN_LBN 64
- #define TX_MADR0_FIL_EN_WIDTH 1
- #define TX_IPFIL31_PORT1_EN_LBN 63
- #define TX_IPFIL31_PORT1_EN_WIDTH 1
- #define TX_IPFIL31_PORT0_EN_LBN 62
- #define TX_IPFIL31_PORT0_EN_WIDTH 1
- #define TX_IPFIL30_PORT1_EN_LBN 61
- #define TX_IPFIL30_PORT1_EN_WIDTH 1
- #define TX_IPFIL30_PORT0_EN_LBN 60
- #define TX_IPFIL30_PORT0_EN_WIDTH 1
- #define TX_IPFIL29_PORT1_EN_LBN 59
- #define TX_IPFIL29_PORT1_EN_WIDTH 1
- #define TX_IPFIL29_PORT0_EN_LBN 58
- #define TX_IPFIL29_PORT0_EN_WIDTH 1
- #define TX_IPFIL28_PORT1_EN_LBN 57
- #define TX_IPFIL28_PORT1_EN_WIDTH 1
- #define TX_IPFIL28_PORT0_EN_LBN 56
- #define TX_IPFIL28_PORT0_EN_WIDTH 1
- #define TX_IPFIL27_PORT1_EN_LBN 55
- #define TX_IPFIL27_PORT1_EN_WIDTH 1
- #define TX_IPFIL27_PORT0_EN_LBN 54
- #define TX_IPFIL27_PORT0_EN_WIDTH 1
- #define TX_IPFIL26_PORT1_EN_LBN 53
- #define TX_IPFIL26_PORT1_EN_WIDTH 1
- #define TX_IPFIL26_PORT0_EN_LBN 52
- #define TX_IPFIL26_PORT0_EN_WIDTH 1
- #define TX_IPFIL25_PORT1_EN_LBN 51
- #define TX_IPFIL25_PORT1_EN_WIDTH 1
- #define TX_IPFIL25_PORT0_EN_LBN 50
- #define TX_IPFIL25_PORT0_EN_WIDTH 1
- #define TX_IPFIL24_PORT1_EN_LBN 49
- #define TX_IPFIL24_PORT1_EN_WIDTH 1
- #define TX_IPFIL24_PORT0_EN_LBN 48
- #define TX_IPFIL24_PORT0_EN_WIDTH 1
- #define TX_IPFIL23_PORT1_EN_LBN 47
- #define TX_IPFIL23_PORT1_EN_WIDTH 1
- #define TX_IPFIL23_PORT0_EN_LBN 46
- #define TX_IPFIL23_PORT0_EN_WIDTH 1
- #define TX_IPFIL22_PORT1_EN_LBN 45
- #define TX_IPFIL22_PORT1_EN_WIDTH 1
- #define TX_IPFIL22_PORT0_EN_LBN 44
- #define TX_IPFIL22_PORT0_EN_WIDTH 1
- #define TX_IPFIL21_PORT1_EN_LBN 43
- #define TX_IPFIL21_PORT1_EN_WIDTH 1
- #define TX_IPFIL21_PORT0_EN_LBN 42
- #define TX_IPFIL21_PORT0_EN_WIDTH 1
- #define TX_IPFIL20_PORT1_EN_LBN 41
- #define TX_IPFIL20_PORT1_EN_WIDTH 1
- #define TX_IPFIL20_PORT0_EN_LBN 40
- #define TX_IPFIL20_PORT0_EN_WIDTH 1
- #define TX_IPFIL19_PORT1_EN_LBN 39
- #define TX_IPFIL19_PORT1_EN_WIDTH 1
- #define TX_IPFIL19_PORT0_EN_LBN 38
- #define TX_IPFIL19_PORT0_EN_WIDTH 1
- #define TX_IPFIL18_PORT1_EN_LBN 37
- #define TX_IPFIL18_PORT1_EN_WIDTH 1
- #define TX_IPFIL18_PORT0_EN_LBN 36
- #define TX_IPFIL18_PORT0_EN_WIDTH 1
- #define TX_IPFIL17_PORT1_EN_LBN 35
- #define TX_IPFIL17_PORT1_EN_WIDTH 1
- #define TX_IPFIL17_PORT0_EN_LBN 34
- #define TX_IPFIL17_PORT0_EN_WIDTH 1
- #define TX_IPFIL16_PORT1_EN_LBN 33
- #define TX_IPFIL16_PORT1_EN_WIDTH 1
- #define TX_IPFIL16_PORT0_EN_LBN 32
- #define TX_IPFIL16_PORT0_EN_WIDTH 1
- #define TX_IPFIL15_PORT1_EN_LBN 31
- #define TX_IPFIL15_PORT1_EN_WIDTH 1
- #define TX_IPFIL15_PORT0_EN_LBN 30
- #define TX_IPFIL15_PORT0_EN_WIDTH 1
- #define TX_IPFIL14_PORT1_EN_LBN 29
- #define TX_IPFIL14_PORT1_EN_WIDTH 1
- #define TX_IPFIL14_PORT0_EN_LBN 28
- #define TX_IPFIL14_PORT0_EN_WIDTH 1
- #define TX_IPFIL13_PORT1_EN_LBN 27
- #define TX_IPFIL13_PORT1_EN_WIDTH 1
- #define TX_IPFIL13_PORT0_EN_LBN 26
- #define TX_IPFIL13_PORT0_EN_WIDTH 1
- #define TX_IPFIL12_PORT1_EN_LBN 25
- #define TX_IPFIL12_PORT1_EN_WIDTH 1
- #define TX_IPFIL12_PORT0_EN_LBN 24
- #define TX_IPFIL12_PORT0_EN_WIDTH 1
- #define TX_IPFIL11_PORT1_EN_LBN 23
- #define TX_IPFIL11_PORT1_EN_WIDTH 1
- #define TX_IPFIL11_PORT0_EN_LBN 22
- #define TX_IPFIL11_PORT0_EN_WIDTH 1
- #define TX_IPFIL10_PORT1_EN_LBN 21
- #define TX_IPFIL10_PORT1_EN_WIDTH 1
- #define TX_IPFIL10_PORT0_EN_LBN 20
- #define TX_IPFIL10_PORT0_EN_WIDTH 1
- #define TX_IPFIL9_PORT1_EN_LBN 19
- #define TX_IPFIL9_PORT1_EN_WIDTH 1
- #define TX_IPFIL9_PORT0_EN_LBN 18
- #define TX_IPFIL9_PORT0_EN_WIDTH 1
- #define TX_IPFIL8_PORT1_EN_LBN 17
- #define TX_IPFIL8_PORT1_EN_WIDTH 1
- #define TX_IPFIL8_PORT0_EN_LBN 16
- #define TX_IPFIL8_PORT0_EN_WIDTH 1
- #define TX_IPFIL7_PORT1_EN_LBN 15
- #define TX_IPFIL7_PORT1_EN_WIDTH 1
- #define TX_IPFIL7_PORT0_EN_LBN 14
- #define TX_IPFIL7_PORT0_EN_WIDTH 1
- #define TX_IPFIL6_PORT1_EN_LBN 13
- #define TX_IPFIL6_PORT1_EN_WIDTH 1
- #define TX_IPFIL6_PORT0_EN_LBN 12
- #define TX_IPFIL6_PORT0_EN_WIDTH 1
- #define TX_IPFIL5_PORT1_EN_LBN 11
- #define TX_IPFIL5_PORT1_EN_WIDTH 1
- #define TX_IPFIL5_PORT0_EN_LBN 10
- #define TX_IPFIL5_PORT0_EN_WIDTH 1
- #define TX_IPFIL4_PORT1_EN_LBN 9
- #define TX_IPFIL4_PORT1_EN_WIDTH 1
- #define TX_IPFIL4_PORT0_EN_LBN 8
- #define TX_IPFIL4_PORT0_EN_WIDTH 1
- #define TX_IPFIL3_PORT1_EN_LBN 7
- #define TX_IPFIL3_PORT1_EN_WIDTH 1
- #define TX_IPFIL3_PORT0_EN_LBN 6
- #define TX_IPFIL3_PORT0_EN_WIDTH 1
- #define TX_IPFIL2_PORT1_EN_LBN 5
- #define TX_IPFIL2_PORT1_EN_WIDTH 1
- #define TX_IPFIL2_PORT0_EN_LBN 4
- #define TX_IPFIL2_PORT0_EN_WIDTH 1
- #define TX_IPFIL1_PORT1_EN_LBN 3
- #define TX_IPFIL1_PORT1_EN_WIDTH 1
- #define TX_IPFIL1_PORT0_EN_LBN 2
- #define TX_IPFIL1_PORT0_EN_WIDTH 1
- #define TX_IPFIL0_PORT1_EN_LBN 1
- #define TX_IPFIL0_PORT1_EN_WIDTH 1
- #define TX_IPFIL0_PORT0_EN_LBN 0
- #define TX_IPFIL0_PORT0_EN_WIDTH 1
-#define TX_IPFIL_TBL_OFST 0xB00 /* Transmit IP source address filter table */
- #define TX_IPFIL_MASK_LBN 32
- #define TX_IPFIL_MASK_WIDTH 32
- #define TX_IP_SRC_ADR_LBN 0
- #define TX_IP_SRC_ADR_WIDTH 32
-#define TX_PACE_REG_A1_OFST 0xF80000 /* Transmit pace control register */
-#define TX_PACE_REG_B0_OFST 0xA90 /* Transmit pace control register */
- #define TX_PACE_SB_AF_LBN 19
- #define TX_PACE_SB_AF_WIDTH 10
- #define TX_PACE_SB_NOTAF_LBN 9
- #define TX_PACE_SB_NOTAF_WIDTH 10
- #define TX_PACE_FB_BASE_LBN 5
- #define TX_PACE_FB_BASE_WIDTH 4
- #define TX_PACE_BIN_TH_LBN 0
- #define TX_PACE_BIN_TH_WIDTH 5
-#define TX_PACE_TBL_A1_OFST 0xF80040 /* Transmit pacing table */
-#define TX_PACE_TBL_FIRST_QUEUE_A1 4
-#define TX_PACE_TBL_B0_OFST 0xF80000 /* Transmit pacing table */
-#define TX_PACE_TBL_FIRST_QUEUE_B0 0
- #define TX_PACE_LBN 0
- #define TX_PACE_WIDTH 5
-
-/*************---- EE/Flash Registers C Header ----*************/
-#define EE_SPI_HCMD_REG_KER_OFST 0x100 /* SPI host command register */
-#define EE_SPI_HCMD_REG_OFST 0x100 /* SPI host command register */
- #define EE_SPI_HCMD_CMD_EN_LBN 31
- #define EE_SPI_HCMD_CMD_EN_WIDTH 1
- #define EE_WR_TIMER_ACTIVE_LBN 28
- #define EE_WR_TIMER_ACTIVE_WIDTH 1
- #define EE_SPI_HCMD_SF_SEL_LBN 24
- #define EE_SPI_HCMD_SF_SEL_WIDTH 1
- #define EE_SPI_HCMD_DABCNT_LBN 16
- #define EE_SPI_HCMD_DABCNT_WIDTH 5
- #define EE_SPI_HCMD_READ_LBN 15
- #define EE_SPI_HCMD_READ_WIDTH 1
- #define EE_SPI_HCMD_DUBCNT_LBN 12
- #define EE_SPI_HCMD_DUBCNT_WIDTH 2
- #define EE_SPI_HCMD_ADBCNT_LBN 8
- #define EE_SPI_HCMD_ADBCNT_WIDTH 2
- #define EE_SPI_HCMD_ENC_LBN 0
- #define EE_SPI_HCMD_ENC_WIDTH 8
-#define EE_SPI_HADR_REG_KER_OFST 0X110 /* SPI host address register */
-#define EE_SPI_HADR_REG_OFST 0X110 /* SPI host address register */
- #define EE_SPI_HADR_DUBYTE_LBN 24
- #define EE_SPI_HADR_DUBYTE_WIDTH 8
- #define EE_SPI_HADR_ADR_LBN 0
- #define EE_SPI_HADR_ADR_WIDTH 24
-#define EE_SPI_HDATA_REG_KER_OFST 0x120 /* SPI host data register */
-#define EE_SPI_HDATA_REG_OFST 0x120 /* SPI host data register */
- #define EE_SPI_HDATA3_LBN 96
- #define EE_SPI_HDATA3_WIDTH 32
- #define EE_SPI_HDATA2_LBN 64
- #define EE_SPI_HDATA2_WIDTH 32
- #define EE_SPI_HDATA1_LBN 32
- #define EE_SPI_HDATA1_WIDTH 32
- #define EE_SPI_HDATA0_LBN 0
- #define EE_SPI_HDATA0_WIDTH 32
-#define EE_BASE_PAGE_REG_KER_OFST 0x130 /* Expansion ROM base mirror register */
-#define EE_BASE_PAGE_REG_OFST 0x130 /* Expansion ROM base mirror register */
- #define EE_EXP_ROM_WINDOW_BASE_LBN 16
- #define EE_EXP_ROM_WINDOW_BASE_WIDTH 13
- #define EE_EXPROM_MASK_LBN 0
- #define EE_EXPROM_MASK_WIDTH 13
-#define EE_VPD_CFG0_REG_KER_OFST 0X140 /* SPI/VPD configuration register */
-#define EE_VPD_CFG0_REG_OFST 0X140 /* SPI/VPD configuration register */
- #define EE_SF_FASTRD_EN_LBN 127
- #define EE_SF_FASTRD_EN_WIDTH 1
- #define EE_SF_CLOCK_DIV_LBN 120
- #define EE_SF_CLOCK_DIV_WIDTH 7
- #define EE_VPD_WIP_POLL_LBN 119
- #define EE_VPD_WIP_POLL_WIDTH 1
- #define EE_VPDW_LENGTH_LBN 80
- #define EE_VPDW_LENGTH_WIDTH 15
- #define EE_VPDW_BASE_LBN 64
- #define EE_VPDW_BASE_WIDTH 15
- #define EE_VPD_WR_CMD_EN_LBN 56
- #define EE_VPD_WR_CMD_EN_WIDTH 8
- #define EE_VPD_BASE_LBN 32
- #define EE_VPD_BASE_WIDTH 24
- #define EE_VPD_LENGTH_LBN 16
- #define EE_VPD_LENGTH_WIDTH 13
- #define EE_VPD_AD_SIZE_LBN 8
- #define EE_VPD_AD_SIZE_WIDTH 5
- #define EE_VPD_ACCESS_ON_LBN 5
- #define EE_VPD_ACCESS_ON_WIDTH 1
-#define EE_VPD_SW_CNTL_REG_KER_OFST 0X150 /* VPD access SW control register */
-#define EE_VPD_SW_CNTL_REG_OFST 0X150 /* VPD access SW control register */
- #define EE_VPD_CYCLE_PENDING_LBN 31
- #define EE_VPD_CYCLE_PENDING_WIDTH 1
- #define EE_VPD_CYC_WRITE_LBN 28
- #define EE_VPD_CYC_WRITE_WIDTH 1
- #define EE_VPD_CYC_ADR_LBN 0
- #define EE_VPD_CYC_ADR_WIDTH 15
-#define EE_VPD_SW_DATA_REG_KER_OFST 0x160 /* VPD access SW data register */
-#define EE_VPD_SW_DATA_REG_OFST 0x160 /* VPD access SW data register */
- #define EE_VPD_CYC_DAT_LBN 0
- #define EE_VPD_CYC_DAT_WIDTH 32
* This file provides EtherFabric NIC - EFXXXX (aka Falcon) descriptor
* definitions.
*
- * Copyright 2005-2007: Solarflare Communications Inc,
+ * Copyright 2005-2010: Solarflare Communications Inc,
* 9501 Jeronimo Road, Suite 250,
* Irvine, CA 92618, USA
*
* This file provides EtherFabric NIC - EFXXXX (aka Falcon) event
* definitions.
*
- * Copyright 2005-2007: Solarflare Communications Inc,
+ * Copyright 2005-2010: Solarflare Communications Inc,
* 9501 Jeronimo Road, Suite 250,
* Irvine, CA 92618, USA
*
#define TX_PKT_NON_TCP_UDP_DECODE 0x9
#define TIMER_EV_DECODE 0xA
#define RX_DSC_ERROR_EV_DECODE 0xE
+ #define DRIVER_EV_RX_FLUSH_FAIL_LBN 12
+ #define DRIVER_EV_RX_FLUSH_FAIL_WIDTH 1
#define DRIVER_EV_TX_DESCQ_ID_LBN 0
#define DRIVER_EV_TX_DESCQ_ID_WIDTH 12
#define DRIVER_EV_RX_DESCQ_ID_LBN 0
* This file provides EtherFabric NIC - EFXXXX (aka Falcon) 1G MAC
* counters.
*
- * Copyright 2005-2007: Solarflare Communications Inc,
+ * Copyright 2005-2010: Solarflare Communications Inc,
* 9501 Jeronimo Road, Suite 250,
* Irvine, CA 92618, USA
*
* This file provides EtherFabric NIC - EFXXXX (aka Falcon) interrupt
* vector definitions.
*
- * Copyright 2005-2007: Solarflare Communications Inc,
+ * Copyright 2005-2010: Solarflare Communications Inc,
* 9501 Jeronimo Road, Suite 250,
* Irvine, CA 92618, USA
*
* This file provides EtherFabric NIC - EFXXXX (aka Falcon) MAC register
* definitions.
*
- * Copyright 2005-2007: Solarflare Communications Inc,
+ * Copyright 2005-2010: Solarflare Communications Inc,
* 9501 Jeronimo Road, Suite 250,
* Irvine, CA 92618, USA
*
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
****************************************************************************
*/
+#ifdef USE_OLD_HWDEFS
/*********---- 1G/10G Ethernet MAC Wrapper Registers C Header ----*********/
#define MD_TXD_REG_KER_OFST 0xC00 /* PHY management transmit data register */
#define XX_DISPERR_CH1_WIDTH 1
#define XX_DISPERR_CH0_LBN 0
#define XX_DISPERR_CH0_WIDTH 1
+#endif
* This file provides EtherFabric NIC - EFXXXX (aka Falcon) 10G MAC
* statistics register definitions.
*
- * Copyright 2005-2007: Solarflare Communications Inc,
+ * Copyright 2005-2010: Solarflare Communications Inc,
* 9501 Jeronimo Road, Suite 250,
* Irvine, CA 92618, USA
*
--- /dev/null
+/****************************************************************************
+ * Driver for Solarflare network controllers -
+ * resource management for Xen backend, OpenOnload, etc
+ * (including support for SFE4001 10GBT NIC)
+ *
+ * This file provides EtherFabric NIC hardware interface common
+ * definitions.
+ *
+ * Copyright 2005-2010: Solarflare Communications Inc,
+ * 9501 Jeronimo Road, Suite 250,
+ * Irvine, CA 92618, USA
+ *
+ * Developed and maintained by Solarflare Communications:
+ * <linux-xen-drivers@solarflare.com>
+ * <onload-dev@solarflare.com>
+ *
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation, incorporated herein by reference.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ ****************************************************************************
+ */
+
+#ifndef HOST_PROGMODEL_DEFS_H
+#define HOST_PROGMODEL_DEFS_H
+
+/*------------------------------------------------------------*/
+/*
+ * FR_AZ_IOM_IND_ADR_REG(32bit):
+ * IO-mapped indirect access address register
+ */
+#define FR_AZ_IOM_IND_ADR_REG_OFST 0x00000000
+/* falcona0,falconb0,sienaa0=net_func_bar0 */
+
+#define FRF_AZ_IOM_AUTO_ADR_INC_EN_LBN 24
+#define FRF_AZ_IOM_AUTO_ADR_INC_EN_WIDTH 1
+#define FRF_AZ_IOM_IND_ADR_LBN 0
+#define FRF_AZ_IOM_IND_ADR_WIDTH 24
+
+
+/*------------------------------------------------------------*/
+/*
+ * FR_AZ_IOM_IND_DAT_REG(32bit):
+ * IO-mapped indirect access data register
+ */
+#define FR_AZ_IOM_IND_DAT_REG_OFST 0x00000004
+/* falcona0,falconb0,sienaa0=net_func_bar0 */
+
+#define FRF_AZ_IOM_IND_DAT_LBN 0
+#define FRF_AZ_IOM_IND_DAT_WIDTH 32
+
+
+/*------------------------------------------------------------*/
+/*
+ * FR_AZ_ADR_REGION_REG(128bit):
+ * Address region register
+ */
+#define FR_AZ_ADR_REGION_REG_OFST 0x00000000
+/* falcona0,falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */
+
+#define FRF_AZ_ADR_REGION3_LBN 96
+#define FRF_AZ_ADR_REGION3_WIDTH 18
+#define FRF_AZ_ADR_REGION2_LBN 64
+#define FRF_AZ_ADR_REGION2_WIDTH 18
+#define FRF_AZ_ADR_REGION1_LBN 32
+#define FRF_AZ_ADR_REGION1_WIDTH 18
+#define FRF_AZ_ADR_REGION0_LBN 0
+#define FRF_AZ_ADR_REGION0_WIDTH 18
+
+
+/*------------------------------------------------------------*/
+/*
+ * FR_AZ_INT_EN_REG_KER(128bit):
+ * Kernel driver Interrupt enable register
+ */
+#define FR_AZ_INT_EN_REG_KER_OFST 0x00000010
+/* falcona0,falconb0,sienaa0=net_func_bar2 */
+
+#define FRF_AZ_KER_INT_LEVE_SEL_LBN 8
+#define FRF_AZ_KER_INT_LEVE_SEL_WIDTH 6
+#define FRF_AZ_KER_INT_CHAR_LBN 4
+#define FRF_AZ_KER_INT_CHAR_WIDTH 1
+#define FRF_AZ_KER_INT_KER_LBN 3
+#define FRF_AZ_KER_INT_KER_WIDTH 1
+#define FRF_AZ_DRV_INT_EN_KER_LBN 0
+#define FRF_AZ_DRV_INT_EN_KER_WIDTH 1
+
+
+/*------------------------------------------------------------*/
+/*
+ * FR_AZ_INT_EN_REG_CHAR(128bit):
+ * Char Driver interrupt enable register
+ */
+#define FR_AZ_INT_EN_REG_CHAR_OFST 0x00000020
+/* falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */
+
+#define FRF_AZ_CHAR_INT_LEVE_SEL_LBN 8
+#define FRF_AZ_CHAR_INT_LEVE_SEL_WIDTH 6
+#define FRF_AZ_CHAR_INT_CHAR_LBN 4
+#define FRF_AZ_CHAR_INT_CHAR_WIDTH 1
+#define FRF_AZ_CHAR_INT_KER_LBN 3
+#define FRF_AZ_CHAR_INT_KER_WIDTH 1
+#define FRF_AZ_DRV_INT_EN_CHAR_LBN 0
+#define FRF_AZ_DRV_INT_EN_CHAR_WIDTH 1
+
+
+/*------------------------------------------------------------*/
+/*
+ * FR_AZ_INT_ADR_REG_KER(128bit):
+ * Interrupt host address for Kernel driver
+ */
+#define FR_AZ_INT_ADR_REG_KER_OFST 0x00000030
+/* falcona0,falconb0,sienaa0=net_func_bar2 */
+
+#define FRF_AZ_NORM_INT_VEC_DIS_KER_LBN 64
+#define FRF_AZ_NORM_INT_VEC_DIS_KER_WIDTH 1
+#define FRF_AZ_INT_ADR_KER_LBN 0
+#define FRF_AZ_INT_ADR_KER_WIDTH 64
+
+
+/*------------------------------------------------------------*/
+/*
+ * FR_AZ_INT_ADR_REG_CHAR(128bit):
+ * Interrupt host address for Char driver
+ */
+#define FR_AZ_INT_ADR_REG_CHAR_OFST 0x00000040
+/* falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */
+
+#define FRF_AZ_NORM_INT_VEC_DIS_CHAR_LBN 64
+#define FRF_AZ_NORM_INT_VEC_DIS_CHAR_WIDTH 1
+#define FRF_AZ_INT_ADR_CHAR_LBN 0
+#define FRF_AZ_INT_ADR_CHAR_WIDTH 64
+
+
+/*------------------------------------------------------------*/
+/*
+ * FR_AA_INT_ACK_KER(32bit):
+ * Kernel interrupt acknowledge register
+ */
+#define FR_AA_INT_ACK_KER_OFST 0x00000050
+/* falcona0=net_func_bar2 */
+
+#define FRF_AA_INT_ACK_KER_FIELD_LBN 0
+#define FRF_AA_INT_ACK_KER_FIELD_WIDTH 32
+
+
+/*------------------------------------------------------------*/
+/*
+ * FR_BZ_INT_ISR0_REG(128bit):
+ * Function 0 Interrupt Acknowlege Status register
+ */
+#define FR_BZ_INT_ISR0_REG_OFST 0x00000090
+/* falconb0,sienaa0=net_func_bar2 */
+
+#define FRF_BZ_INT_ISR_REG_LBN 0
+#define FRF_BZ_INT_ISR_REG_WIDTH 64
+
+
+/*------------------------------------------------------------*/
+/*
+ * FR_AZ_HW_INIT_REG(128bit):
+ * Hardware initialization register
+ */
+#define FR_AZ_HW_INIT_REG_OFST 0x000000c0
+/* falcona0,falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */
+
+#define FRF_BB_BDMRD_CPLF_FULL_LBN 124
+#define FRF_BB_BDMRD_CPLF_FULL_WIDTH 1
+#define FRF_BB_PCIE_CPL_TIMEOUT_CTRL_LBN 121
+#define FRF_BB_PCIE_CPL_TIMEOUT_CTRL_WIDTH 3
+#define FRF_CZ_TX_MRG_TAGS_LBN 120
+#define FRF_CZ_TX_MRG_TAGS_WIDTH 1
+#define FRF_AB_TRGT_MASK_ALL_LBN 100
+#define FRF_AB_TRGT_MASK_ALL_WIDTH 1
+#define FRF_AZ_DOORBELL_DROP_LBN 92
+#define FRF_AZ_DOORBELL_DROP_WIDTH 8
+#define FRF_AB_TX_RREQ_MASK_EN_LBN 76
+#define FRF_AB_TX_RREQ_MASK_EN_WIDTH 1
+#define FRF_AB_PE_EIDLE_DIS_LBN 75
+#define FRF_AB_PE_EIDLE_DIS_WIDTH 1
+#define FRF_AA_FC_BLOCKING_EN_LBN 45
+#define FRF_AA_FC_BLOCKING_EN_WIDTH 1
+#define FRF_BZ_B2B_REQ_EN_LBN 45
+#define FRF_BZ_B2B_REQ_EN_WIDTH 1
+#define FRF_AA_B2B_REQ_EN_LBN 44
+#define FRF_AA_B2B_REQ_EN_WIDTH 1
+#define FRF_BB_FC_BLOCKING_EN_LBN 44
+#define FRF_BB_FC_BLOCKING_EN_WIDTH 1
+#define FRF_AZ_POST_WR_MASK_LBN 40
+#define FRF_AZ_POST_WR_MASK_WIDTH 4
+#define FRF_AZ_TLP_TC_LBN 34
+#define FRF_AZ_TLP_TC_WIDTH 3
+#define FRF_AZ_TLP_ATTR_LBN 32
+#define FRF_AZ_TLP_ATTR_WIDTH 2
+#define FRF_AB_INTB_VEC_LBN 24
+#define FRF_AB_INTB_VEC_WIDTH 5
+#define FRF_AB_INTA_VEC_LBN 16
+#define FRF_AB_INTA_VEC_WIDTH 5
+#define FRF_AZ_WD_TIMER_LBN 8
+#define FRF_AZ_WD_TIMER_WIDTH 8
+#define FRF_AZ_US_DISABLE_LBN 5
+#define FRF_AZ_US_DISABLE_WIDTH 1
+#define FRF_AZ_TLP_EP_LBN 4
+#define FRF_AZ_TLP_EP_WIDTH 1
+#define FRF_AZ_ATTR_SEL_LBN 3
+#define FRF_AZ_ATTR_SEL_WIDTH 1
+#define FRF_AZ_TD_SEL_LBN 1
+#define FRF_AZ_TD_SEL_WIDTH 1
+#define FRF_AZ_TLP_TD_LBN 0
+#define FRF_AZ_TLP_TD_WIDTH 1
+
+
+/*------------------------------------------------------------*/
+/*
+ * FR_AB_EE_SPI_HCMD_REG(128bit):
+ * SPI host command register
+ */
+#define FR_AB_EE_SPI_HCMD_REG_OFST 0x00000100
+/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */
+
+#define FRF_AB_EE_SPI_HCMD_CMD_EN_LBN 31
+#define FRF_AB_EE_SPI_HCMD_CMD_EN_WIDTH 1
+#define FRF_AB_EE_WR_TIMER_ACTIVE_LBN 28
+#define FRF_AB_EE_WR_TIMER_ACTIVE_WIDTH 1
+#define FRF_AB_EE_SPI_HCMD_SF_SEL_LBN 24
+#define FRF_AB_EE_SPI_HCMD_SF_SEL_WIDTH 1
+#define FRF_AB_EE_SPI_HCMD_DABCNT_LBN 16
+#define FRF_AB_EE_SPI_HCMD_DABCNT_WIDTH 5
+#define FRF_AB_EE_SPI_HCMD_READ_LBN 15
+#define FRF_AB_EE_SPI_HCMD_READ_WIDTH 1
+#define FRF_AB_EE_SPI_HCMD_DUBCNT_LBN 12
+#define FRF_AB_EE_SPI_HCMD_DUBCNT_WIDTH 2
+#define FRF_AB_EE_SPI_HCMD_ADBCNT_LBN 8
+#define FRF_AB_EE_SPI_HCMD_ADBCNT_WIDTH 2
+#define FRF_AB_EE_SPI_HCMD_ENC_LBN 0
+#define FRF_AB_EE_SPI_HCMD_ENC_WIDTH 8
+
+
+/*------------------------------------------------------------*/
+/*
+ * FR_CZ_USR_EV_CFG(128bit):
+ * User Level Event Configuration register
+ */
+#define FR_CZ_USR_EV_CFG_OFST 0x00000100
+/* sienaa0=net_func_bar2 */
+
+#define FRF_CZ_USREV_DIS_LBN 16
+#define FRF_CZ_USREV_DIS_WIDTH 1
+#define FRF_CZ_DFLT_EVQ_LBN 0
+#define FRF_CZ_DFLT_EVQ_WIDTH 10
+
+
+/*------------------------------------------------------------*/
+/*
+ * FR_AB_EE_SPI_HADR_REG(128bit):
+ * SPI host address register
+ */
+#define FR_AB_EE_SPI_HADR_REG_OFST 0x00000110
+/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */
+
+#define FRF_AB_EE_SPI_HADR_DUBYTE_LBN 24
+#define FRF_AB_EE_SPI_HADR_DUBYTE_WIDTH 8
+#define FRF_AB_EE_SPI_HADR_ADR_LBN 0
+#define FRF_AB_EE_SPI_HADR_ADR_WIDTH 24
+
+
+/*------------------------------------------------------------*/
+/*
+ * FR_AB_EE_SPI_HDATA_REG(128bit):
+ * SPI host data register
+ */
+#define FR_AB_EE_SPI_HDATA_REG_OFST 0x00000120
+/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */
+
+#define FRF_AB_EE_SPI_HDATA3_LBN 96
+#define FRF_AB_EE_SPI_HDATA3_WIDTH 32
+#define FRF_AB_EE_SPI_HDATA2_LBN 64
+#define FRF_AB_EE_SPI_HDATA2_WIDTH 32
+#define FRF_AB_EE_SPI_HDATA1_LBN 32
+#define FRF_AB_EE_SPI_HDATA1_WIDTH 32
+#define FRF_AB_EE_SPI_HDATA0_LBN 0
+#define FRF_AB_EE_SPI_HDATA0_WIDTH 32
+
+
+/*------------------------------------------------------------*/
+/*
+ * FR_AB_EE_BASE_PAGE_REG(128bit):
+ * Expansion ROM base mirror register
+ */
+#define FR_AB_EE_BASE_PAGE_REG_OFST 0x00000130
+/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */
+
+#define FRF_AB_EE_EXPROM_MASK_LBN 16
+#define FRF_AB_EE_EXPROM_MASK_WIDTH 13
+#define FRF_AB_EE_EXP_ROM_WINDOW_BASE_LBN 0
+#define FRF_AB_EE_EXP_ROM_WINDOW_BASE_WIDTH 13
+
+
+/*------------------------------------------------------------*/
+/*
+ * FR_AB_EE_VPD_CFG0_REG(128bit):
+ * SPI/VPD configuration register 0
+ */
+#define FR_AB_EE_VPD_CFG0_REG_OFST 0x00000140
+/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */
+
+#define FRF_AB_EE_SF_FASTRD_EN_LBN 127
+#define FRF_AB_EE_SF_FASTRD_EN_WIDTH 1
+#define FRF_AB_EE_SF_CLOCK_DIV_LBN 120
+#define FRF_AB_EE_SF_CLOCK_DIV_WIDTH 7
+#define FRF_AB_EE_VPD_WIP_POLL_LBN 119
+#define FRF_AB_EE_VPD_WIP_POLL_WIDTH 1
+#define FRF_AB_EE_EE_CLOCK_DIV_LBN 112
+#define FRF_AB_EE_EE_CLOCK_DIV_WIDTH 7
+#define FRF_AB_EE_EE_WR_TMR_VALUE_LBN 96
+#define FRF_AB_EE_EE_WR_TMR_VALUE_WIDTH 16
+#define FRF_AB_EE_VPDW_LENGTH_LBN 80
+#define FRF_AB_EE_VPDW_LENGTH_WIDTH 15
+#define FRF_AB_EE_VPDW_BASE_LBN 64
+#define FRF_AB_EE_VPDW_BASE_WIDTH 15
+#define FRF_AB_EE_VPD_WR_CMD_EN_LBN 56
+#define FRF_AB_EE_VPD_WR_CMD_EN_WIDTH 8
+#define FRF_AB_EE_VPD_BASE_LBN 32
+#define FRF_AB_EE_VPD_BASE_WIDTH 24
+#define FRF_AB_EE_VPD_LENGTH_LBN 16
+#define FRF_AB_EE_VPD_LENGTH_WIDTH 15
+#define FRF_AB_EE_VPD_AD_SIZE_LBN 8
+#define FRF_AB_EE_VPD_AD_SIZE_WIDTH 5
+#define FRF_AB_EE_VPD_ACCESS_ON_LBN 5
+#define FRF_AB_EE_VPD_ACCESS_ON_WIDTH 1
+#define FRF_AB_EE_VPD_ACCESS_BLOCK_LBN 4
+#define FRF_AB_EE_VPD_ACCESS_BLOCK_WIDTH 1
+#define FRF_AB_EE_VPD_DEV_SF_SEL_LBN 2
+#define FRF_AB_EE_VPD_DEV_SF_SEL_WIDTH 1
+#define FRF_AB_EE_VPD_EN_AD9_MODE_LBN 1
+#define FRF_AB_EE_VPD_EN_AD9_MODE_WIDTH 1
+#define FRF_AB_EE_VPD_EN_LBN 0
+#define FRF_AB_EE_VPD_EN_WIDTH 1
+
+
+/*------------------------------------------------------------*/
+/*
+ * FR_AB_EE_VPD_SW_CNTL_REG(128bit):
+ * VPD access SW control register
+ */
+#define FR_AB_EE_VPD_SW_CNTL_REG_OFST 0x00000150
+/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */
+
+#define FRF_AB_EE_VPD_CYCLE_PENDING_LBN 31
+#define FRF_AB_EE_VPD_CYCLE_PENDING_WIDTH 1
+#define FRF_AB_EE_VPD_CYC_WRITE_LBN 28
+#define FRF_AB_EE_VPD_CYC_WRITE_WIDTH 1
+#define FRF_AB_EE_VPD_CYC_ADR_LBN 0
+#define FRF_AB_EE_VPD_CYC_ADR_WIDTH 15
+
+
+/*------------------------------------------------------------*/
+/*
+ * FR_AB_EE_VPD_SW_DATA_REG(128bit):
+ * VPD access SW data register
+ */
+#define FR_AB_EE_VPD_SW_DATA_REG_OFST 0x00000160
+/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */
+
+#define FRF_AB_EE_VPD_CYC_DAT_LBN 0
+#define FRF_AB_EE_VPD_CYC_DAT_WIDTH 32
+
+
+/*------------------------------------------------------------*/
+/*
+ * FR_BB_PCIE_CORE_INDIRECT_REG(64bit):
+ * Indirect Access to PCIE Core registers
+ */
+#define FR_BB_PCIE_CORE_INDIRECT_REG_OFST 0x000001f0
+/* falconb0=net_func_bar2 */
+
+#define FRF_BB_PCIE_CORE_TARGET_DATA_LBN 32
+#define FRF_BB_PCIE_CORE_TARGET_DATA_WIDTH 32
+#define FRF_BB_PCIE_CORE_INDIRECT_ACCESS_DIR_LBN 15
+#define FRF_BB_PCIE_CORE_INDIRECT_ACCESS_DIR_WIDTH 1
+#define FRF_BB_PCIE_CORE_TARGET_REG_ADRS_LBN 0
+#define FRF_BB_PCIE_CORE_TARGET_REG_ADRS_WIDTH 12
+
+
+/*------------------------------------------------------------*/
+/*
+ * FR_AB_NIC_STAT_REG(128bit):
+ * NIC status register
+ */
+#define FR_AB_NIC_STAT_REG_OFST 0x00000200
+/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */
+
+#define FRF_BB_AER_DIS_LBN 34
+#define FRF_BB_AER_DIS_WIDTH 1
+#define FRF_BB_EE_STRAP_EN_LBN 31
+#define FRF_BB_EE_STRAP_EN_WIDTH 1
+#define FRF_BB_EE_STRAP_LBN 24
+#define FRF_BB_EE_STRAP_WIDTH 4
+#define FRF_BB_REVISION_ID_LBN 17
+#define FRF_BB_REVISION_ID_WIDTH 7
+#define FRF_AB_ONCHIP_SRAM_LBN 16
+#define FRF_AB_ONCHIP_SRAM_WIDTH 1
+#define FRF_AB_SF_PRST_LBN 9
+#define FRF_AB_SF_PRST_WIDTH 1
+#define FRF_AB_EE_PRST_LBN 8
+#define FRF_AB_EE_PRST_WIDTH 1
+#define FRF_AB_ATE_MODE_LBN 3
+#define FRF_AB_ATE_MODE_WIDTH 1
+#define FRF_AB_STRAP_PINS_LBN 0
+#define FRF_AB_STRAP_PINS_WIDTH 3
+
+
+/*------------------------------------------------------------*/
+/*
+ * FR_AB_GPIO_CTL_REG(128bit):
+ * GPIO control register
+ */
+#define FR_AB_GPIO_CTL_REG_OFST 0x00000210
+/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */
+
+#define FRF_AB_GPIO_OUT3_LBN 112
+#define FRF_AB_GPIO_OUT3_WIDTH 16
+#define FRF_AB_GPIO_IN3_LBN 104
+#define FRF_AB_GPIO_IN3_WIDTH 8
+#define FRF_AB_GPIO_PWRUP_VALUE3_LBN 96
+#define FRF_AB_GPIO_PWRUP_VALUE3_WIDTH 8
+#define FRF_AB_GPIO_OUT2_LBN 80
+#define FRF_AB_GPIO_OUT2_WIDTH 16
+#define FRF_AB_GPIO_IN2_LBN 72
+#define FRF_AB_GPIO_IN2_WIDTH 8
+#define FRF_AB_GPIO_PWRUP_VALUE2_LBN 64
+#define FRF_AB_GPIO_PWRUP_VALUE2_WIDTH 8
+#define FRF_AB_GPIO15_OEN_LBN 63
+#define FRF_AB_GPIO15_OEN_WIDTH 1
+#define FRF_AB_GPIO14_OEN_LBN 62
+#define FRF_AB_GPIO14_OEN_WIDTH 1
+#define FRF_AB_GPIO13_OEN_LBN 61
+#define FRF_AB_GPIO13_OEN_WIDTH 1
+#define FRF_AB_GPIO12_OEN_LBN 60
+#define FRF_AB_GPIO12_OEN_WIDTH 1
+#define FRF_AB_GPIO11_OEN_LBN 59
+#define FRF_AB_GPIO11_OEN_WIDTH 1
+#define FRF_AB_GPIO10_OEN_LBN 58
+#define FRF_AB_GPIO10_OEN_WIDTH 1
+#define FRF_AB_GPIO9_OEN_LBN 57
+#define FRF_AB_GPIO9_OEN_WIDTH 1
+#define FRF_AB_GPIO8_OEN_LBN 56
+#define FRF_AB_GPIO8_OEN_WIDTH 1
+#define FRF_AB_GPIO15_OUT_LBN 55
+#define FRF_AB_GPIO15_OUT_WIDTH 1
+#define FRF_AB_GPIO14_OUT_LBN 54
+#define FRF_AB_GPIO14_OUT_WIDTH 1
+#define FRF_AB_GPIO13_OUT_LBN 53
+#define FRF_AB_GPIO13_OUT_WIDTH 1
+#define FRF_AB_GPIO12_OUT_LBN 52
+#define FRF_AB_GPIO12_OUT_WIDTH 1
+#define FRF_AB_GPIO11_OUT_LBN 51
+#define FRF_AB_GPIO11_OUT_WIDTH 1
+#define FRF_AB_GPIO10_OUT_LBN 50
+#define FRF_AB_GPIO10_OUT_WIDTH 1
+#define FRF_AB_GPIO9_OUT_LBN 49
+#define FRF_AB_GPIO9_OUT_WIDTH 1
+#define FRF_AB_GPIO8_OUT_LBN 48
+#define FRF_AB_GPIO8_OUT_WIDTH 1
+#define FRF_AB_GPIO15_IN_LBN 47
+#define FRF_AB_GPIO15_IN_WIDTH 1
+#define FRF_AB_GPIO14_IN_LBN 46
+#define FRF_AB_GPIO14_IN_WIDTH 1
+#define FRF_AB_GPIO13_IN_LBN 45
+#define FRF_AB_GPIO13_IN_WIDTH 1
+#define FRF_AB_GPIO12_IN_LBN 44
+#define FRF_AB_GPIO12_IN_WIDTH 1
+#define FRF_AB_GPIO11_IN_LBN 43
+#define FRF_AB_GPIO11_IN_WIDTH 1
+#define FRF_AB_GPIO10_IN_LBN 42
+#define FRF_AB_GPIO10_IN_WIDTH 1
+#define FRF_AB_GPIO9_IN_LBN 41
+#define FRF_AB_GPIO9_IN_WIDTH 1
+#define FRF_AB_GPIO8_IN_LBN 40
+#define FRF_AB_GPIO8_IN_WIDTH 1
+#define FRF_AB_GPIO15_PWRUP_VALUE_LBN 39
+#define FRF_AB_GPIO15_PWRUP_VALUE_WIDTH 1
+#define FRF_AB_GPIO14_PWRUP_VALUE_LBN 38
+#define FRF_AB_GPIO14_PWRUP_VALUE_WIDTH 1
+#define FRF_AB_GPIO13_PWRUP_VALUE_LBN 37
+#define FRF_AB_GPIO13_PWRUP_VALUE_WIDTH 1
+#define FRF_AB_GPIO12_PWRUP_VALUE_LBN 36
+#define FRF_AB_GPIO12_PWRUP_VALUE_WIDTH 1
+#define FRF_AB_GPIO11_PWRUP_VALUE_LBN 35
+#define FRF_AB_GPIO11_PWRUP_VALUE_WIDTH 1
+#define FRF_AB_GPIO10_PWRUP_VALUE_LBN 34
+#define FRF_AB_GPIO10_PWRUP_VALUE_WIDTH 1
+#define FRF_AB_GPIO9_PWRUP_VALUE_LBN 33
+#define FRF_AB_GPIO9_PWRUP_VALUE_WIDTH 1
+#define FRF_AB_GPIO8_PWRUP_VALUE_LBN 32
+#define FRF_AB_GPIO8_PWRUP_VALUE_WIDTH 1
+#define FRF_AB_CLK156_OUT_EN_LBN 31
+#define FRF_AB_CLK156_OUT_EN_WIDTH 1
+#define FRF_AB_USE_NIC_CLK_LBN 30
+#define FRF_AB_USE_NIC_CLK_WIDTH 1
+#define FRF_AB_GPIO5_OEN_LBN 29
+#define FRF_AB_GPIO5_OEN_WIDTH 1
+#define FRF_AB_GPIO4_OEN_LBN 28
+#define FRF_AB_GPIO4_OEN_WIDTH 1
+#define FRF_AB_GPIO3_OEN_LBN 27
+#define FRF_AB_GPIO3_OEN_WIDTH 1
+#define FRF_AB_GPIO2_OEN_LBN 26
+#define FRF_AB_GPIO2_OEN_WIDTH 1
+#define FRF_AB_GPIO1_OEN_LBN 25
+#define FRF_AB_GPIO1_OEN_WIDTH 1
+#define FRF_AB_GPIO0_OEN_LBN 24
+#define FRF_AB_GPIO0_OEN_WIDTH 1
+#define FRF_AB_GPIO7_OUT_LBN 23
+#define FRF_AB_GPIO7_OUT_WIDTH 1
+#define FRF_AB_GPIO6_OUT_LBN 22
+#define FRF_AB_GPIO6_OUT_WIDTH 1
+#define FRF_AB_GPIO5_OUT_LBN 21
+#define FRF_AB_GPIO5_OUT_WIDTH 1
+#define FRF_AB_GPIO4_OUT_LBN 20
+#define FRF_AB_GPIO4_OUT_WIDTH 1
+#define FRF_AB_GPIO3_OUT_LBN 19
+#define FRF_AB_GPIO3_OUT_WIDTH 1
+#define FRF_AB_GPIO2_OUT_LBN 18
+#define FRF_AB_GPIO2_OUT_WIDTH 1
+#define FRF_AB_GPIO1_OUT_LBN 17
+#define FRF_AB_GPIO1_OUT_WIDTH 1
+#define FRF_AB_GPIO0_OUT_LBN 16
+#define FRF_AB_GPIO0_OUT_WIDTH 1
+#define FRF_AB_GPIO7_IN_LBN 15
+#define FRF_AB_GPIO7_IN_WIDTH 1
+#define FRF_AB_GPIO6_IN_LBN 14
+#define FRF_AB_GPIO6_IN_WIDTH 1
+#define FRF_AB_GPIO5_IN_LBN 13
+#define FRF_AB_GPIO5_IN_WIDTH 1
+#define FRF_AB_GPIO4_IN_LBN 12
+#define FRF_AB_GPIO4_IN_WIDTH 1
+#define FRF_AB_GPIO3_IN_LBN 11
+#define FRF_AB_GPIO3_IN_WIDTH 1
+#define FRF_AB_GPIO2_IN_LBN 10
+#define FRF_AB_GPIO2_IN_WIDTH 1
+#define FRF_AB_GPIO1_IN_LBN 9
+#define FRF_AB_GPIO1_IN_WIDTH 1
+#define FRF_AB_GPIO0_IN_LBN 8
+#define FRF_AB_GPIO0_IN_WIDTH 1
+#define FRF_AB_GPIO7_PWRUP_VALUE_LBN 7
+#define FRF_AB_GPIO7_PWRUP_VALUE_WIDTH 1
+#define FRF_AB_GPIO6_PWRUP_VALUE_LBN 6
+#define FRF_AB_GPIO6_PWRUP_VALUE_WIDTH 1
+#define FRF_AB_GPIO5_PWRUP_VALUE_LBN 5
+#define FRF_AB_GPIO5_PWRUP_VALUE_WIDTH 1
+#define FRF_AB_GPIO4_PWRUP_VALUE_LBN 4
+#define FRF_AB_GPIO4_PWRUP_VALUE_WIDTH 1
+#define FRF_AB_GPIO3_PWRUP_VALUE_LBN 3
+#define FRF_AB_GPIO3_PWRUP_VALUE_WIDTH 1
+#define FRF_AB_GPIO2_PWRUP_VALUE_LBN 2
+#define FRF_AB_GPIO2_PWRUP_VALUE_WIDTH 1
+#define FRF_AB_GPIO1_PWRUP_VALUE_LBN 1
+#define FRF_AB_GPIO1_PWRUP_VALUE_WIDTH 1
+#define FRF_AB_GPIO0_PWRUP_VALUE_LBN 0
+#define FRF_AB_GPIO0_PWRUP_VALUE_WIDTH 1
+
+
+/*------------------------------------------------------------*/
+/*
+ * FR_AB_GLB_CTL_REG(128bit):
+ * Global control register
+ */
+#define FR_AB_GLB_CTL_REG_OFST 0x00000220
+/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */
+
+#define FRF_AB_EXT_PHY_RST_CTL_LBN 63
+#define FRF_AB_EXT_PHY_RST_CTL_WIDTH 1
+#define FRF_AB_XAUI_SD_RST_CTL_LBN 62
+#define FRF_AB_XAUI_SD_RST_CTL_WIDTH 1
+#define FRF_AB_PCIE_SD_RST_CTL_LBN 61
+#define FRF_AB_PCIE_SD_RST_CTL_WIDTH 1
+#define FRF_AA_PCIX_RST_CTL_LBN 60
+#define FRF_AA_PCIX_RST_CTL_WIDTH 1
+#define FRF_BB_BIU_RST_CTL_LBN 60
+#define FRF_BB_BIU_RST_CTL_WIDTH 1
+#define FRF_AB_PCIE_STKY_RST_CTL_LBN 59
+#define FRF_AB_PCIE_STKY_RST_CTL_WIDTH 1
+#define FRF_AB_PCIE_NSTKY_RST_CTL_LBN 58
+#define FRF_AB_PCIE_NSTKY_RST_CTL_WIDTH 1
+#define FRF_AB_PCIE_CORE_RST_CTL_LBN 57
+#define FRF_AB_PCIE_CORE_RST_CTL_WIDTH 1
+#define FRF_AB_XGRX_RST_CTL_LBN 56
+#define FRF_AB_XGRX_RST_CTL_WIDTH 1
+#define FRF_AB_XGTX_RST_CTL_LBN 55
+#define FRF_AB_XGTX_RST_CTL_WIDTH 1
+#define FRF_AB_EM_RST_CTL_LBN 54
+#define FRF_AB_EM_RST_CTL_WIDTH 1
+#define FRF_AB_EV_RST_CTL_LBN 53
+#define FRF_AB_EV_RST_CTL_WIDTH 1
+#define FRF_AB_SR_RST_CTL_LBN 52
+#define FRF_AB_SR_RST_CTL_WIDTH 1
+#define FRF_AB_RX_RST_CTL_LBN 51
+#define FRF_AB_RX_RST_CTL_WIDTH 1
+#define FRF_AB_TX_RST_CTL_LBN 50
+#define FRF_AB_TX_RST_CTL_WIDTH 1
+#define FRF_AB_EE_RST_CTL_LBN 49
+#define FRF_AB_EE_RST_CTL_WIDTH 1
+#define FRF_AB_CS_RST_CTL_LBN 48
+#define FRF_AB_CS_RST_CTL_WIDTH 1
+#define FRF_AB_HOT_RST_CTL_LBN 40
+#define FRF_AB_HOT_RST_CTL_WIDTH 2
+#define FRF_AB_RST_EXT_PHY_LBN 31
+#define FRF_AB_RST_EXT_PHY_WIDTH 1
+#define FRF_AB_RST_XAUI_SD_LBN 30
+#define FRF_AB_RST_XAUI_SD_WIDTH 1
+#define FRF_AB_RST_PCIE_SD_LBN 29
+#define FRF_AB_RST_PCIE_SD_WIDTH 1
+#define FRF_AA_RST_PCIX_LBN 28
+#define FRF_AA_RST_PCIX_WIDTH 1
+#define FRF_BB_RST_BIU_LBN 28
+#define FRF_BB_RST_BIU_WIDTH 1
+#define FRF_AB_RST_PCIE_STKY_LBN 27
+#define FRF_AB_RST_PCIE_STKY_WIDTH 1
+#define FRF_AB_RST_PCIE_NSTKY_LBN 26
+#define FRF_AB_RST_PCIE_NSTKY_WIDTH 1
+#define FRF_AB_RST_PCIE_CORE_LBN 25
+#define FRF_AB_RST_PCIE_CORE_WIDTH 1
+#define FRF_AB_RST_XGRX_LBN 24
+#define FRF_AB_RST_XGRX_WIDTH 1
+#define FRF_AB_RST_XGTX_LBN 23
+#define FRF_AB_RST_XGTX_WIDTH 1
+#define FRF_AB_RST_EM_LBN 22
+#define FRF_AB_RST_EM_WIDTH 1
+#define FRF_AB_RST_EV_LBN 21
+#define FRF_AB_RST_EV_WIDTH 1
+#define FRF_AB_RST_SR_LBN 20
+#define FRF_AB_RST_SR_WIDTH 1
+#define FRF_AB_RST_RX_LBN 19
+#define FRF_AB_RST_RX_WIDTH 1
+#define FRF_AB_RST_TX_LBN 18
+#define FRF_AB_RST_TX_WIDTH 1
+#define FRF_AB_RST_SF_LBN 17
+#define FRF_AB_RST_SF_WIDTH 1
+#define FRF_AB_RST_CS_LBN 16
+#define FRF_AB_RST_CS_WIDTH 1
+#define FRF_AB_INT_RST_DUR_LBN 4
+#define FRF_AB_INT_RST_DUR_WIDTH 3
+#define FRF_AB_EXT_PHY_RST_DUR_LBN 1
+#define FRF_AB_EXT_PHY_RST_DUR_WIDTH 3
+#define FFE_AB_EXT_PHY_RST_DUR_10240US 7
+#define FFE_AB_EXT_PHY_RST_DUR_5120US 6
+#define FFE_AB_EXT_PHY_RST_DUR_2560US 5
+#define FFE_AB_EXT_PHY_RST_DUR_1280US 4
+#define FFE_AB_EXT_PHY_RST_DUR_640US 3
+#define FFE_AB_EXT_PHY_RST_DUR_320US 2
+#define FFE_AB_EXT_PHY_RST_DUR_160US 1
+#define FFE_AB_EXT_PHY_RST_DUR_80US 0
+#define FRF_AB_SWRST_LBN 0
+#define FRF_AB_SWRST_WIDTH 1
+
+
+/*------------------------------------------------------------*/
+/*
+ * FR_AZ_FATAL_INTR_REG_KER(128bit):
+ * Fatal interrupt register for Kernel
+ */
+#define FR_AZ_FATAL_INTR_REG_KER_OFST 0x00000230
+/* falcona0,falconb0,sienaa0=net_func_bar2 */
+
+#define FRF_CZ_SRAM_PERR_INT_P_KER_EN_LBN 44
+#define FRF_CZ_SRAM_PERR_INT_P_KER_EN_WIDTH 1
+#define FRF_AB_PCI_BUSERR_INT_KER_EN_LBN 43
+#define FRF_AB_PCI_BUSERR_INT_KER_EN_WIDTH 1
+#define FRF_CZ_MBU_PERR_INT_KER_EN_LBN 43
+#define FRF_CZ_MBU_PERR_INT_KER_EN_WIDTH 1
+#define FRF_AZ_SRAM_OOB_INT_KER_EN_LBN 42
+#define FRF_AZ_SRAM_OOB_INT_KER_EN_WIDTH 1
+#define FRF_AZ_BUFID_OOB_INT_KER_EN_LBN 41
+#define FRF_AZ_BUFID_OOB_INT_KER_EN_WIDTH 1
+#define FRF_AZ_MEM_PERR_INT_KER_EN_LBN 40
+#define FRF_AZ_MEM_PERR_INT_KER_EN_WIDTH 1
+#define FRF_AZ_RBUF_OWN_INT_KER_EN_LBN 39
+#define FRF_AZ_RBUF_OWN_INT_KER_EN_WIDTH 1
+#define FRF_AZ_TBUF_OWN_INT_KER_EN_LBN 38
+#define FRF_AZ_TBUF_OWN_INT_KER_EN_WIDTH 1
+#define FRF_AZ_RDESCQ_OWN_INT_KER_EN_LBN 37
+#define FRF_AZ_RDESCQ_OWN_INT_KER_EN_WIDTH 1
+#define FRF_AZ_TDESCQ_OWN_INT_KER_EN_LBN 36
+#define FRF_AZ_TDESCQ_OWN_INT_KER_EN_WIDTH 1
+#define FRF_AZ_EVQ_OWN_INT_KER_EN_LBN 35
+#define FRF_AZ_EVQ_OWN_INT_KER_EN_WIDTH 1
+#define FRF_AZ_EVF_OFLO_INT_KER_EN_LBN 34
+#define FRF_AZ_EVF_OFLO_INT_KER_EN_WIDTH 1
+#define FRF_AZ_ILL_ADR_INT_KER_EN_LBN 33
+#define FRF_AZ_ILL_ADR_INT_KER_EN_WIDTH 1
+#define FRF_AZ_SRM_PERR_INT_KER_EN_LBN 32
+#define FRF_AZ_SRM_PERR_INT_KER_EN_WIDTH 1
+#define FRF_CZ_SRAM_PERR_INT_P_KER_LBN 12
+#define FRF_CZ_SRAM_PERR_INT_P_KER_WIDTH 1
+#define FRF_AB_PCI_BUSERR_INT_KER_LBN 11
+#define FRF_AB_PCI_BUSERR_INT_KER_WIDTH 1
+#define FRF_CZ_MBU_PERR_INT_KER_LBN 11
+#define FRF_CZ_MBU_PERR_INT_KER_WIDTH 1
+#define FRF_AZ_SRAM_OOB_INT_KER_LBN 10
+#define FRF_AZ_SRAM_OOB_INT_KER_WIDTH 1
+#define FRF_AZ_BUFID_DC_OOB_INT_KER_LBN 9
+#define FRF_AZ_BUFID_DC_OOB_INT_KER_WIDTH 1
+#define FRF_AZ_MEM_PERR_INT_KER_LBN 8
+#define FRF_AZ_MEM_PERR_INT_KER_WIDTH 1
+#define FRF_AZ_RBUF_OWN_INT_KER_LBN 7
+#define FRF_AZ_RBUF_OWN_INT_KER_WIDTH 1
+#define FRF_AZ_TBUF_OWN_INT_KER_LBN 6
+#define FRF_AZ_TBUF_OWN_INT_KER_WIDTH 1
+#define FRF_AZ_RDESCQ_OWN_INT_KER_LBN 5
+#define FRF_AZ_RDESCQ_OWN_INT_KER_WIDTH 1
+#define FRF_AZ_TDESCQ_OWN_INT_KER_LBN 4
+#define FRF_AZ_TDESCQ_OWN_INT_KER_WIDTH 1
+#define FRF_AZ_EVQ_OWN_INT_KER_LBN 3
+#define FRF_AZ_EVQ_OWN_INT_KER_WIDTH 1
+#define FRF_AZ_EVF_OFLO_INT_KER_LBN 2
+#define FRF_AZ_EVF_OFLO_INT_KER_WIDTH 1
+#define FRF_AZ_ILL_ADR_INT_KER_LBN 1
+#define FRF_AZ_ILL_ADR_INT_KER_WIDTH 1
+#define FRF_AZ_SRM_PERR_INT_KER_LBN 0
+#define FRF_AZ_SRM_PERR_INT_KER_WIDTH 1
+
+
+/*------------------------------------------------------------*/
+/*
+ * FR_AZ_FATAL_INTR_REG_CHAR(128bit):
+ * Fatal interrupt register for Char
+ */
+#define FR_AZ_FATAL_INTR_REG_CHAR_OFST 0x00000240
+/* falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */
+
+#define FRF_CZ_SRAM_PERR_INT_P_CHAR_EN_LBN 44
+#define FRF_CZ_SRAM_PERR_INT_P_CHAR_EN_WIDTH 1
+#define FRF_AB_PCI_BUSERR_INT_CHAR_EN_LBN 43
+#define FRF_AB_PCI_BUSERR_INT_CHAR_EN_WIDTH 1
+#define FRF_CZ_MBU_PERR_INT_CHAR_EN_LBN 43
+#define FRF_CZ_MBU_PERR_INT_CHAR_EN_WIDTH 1
+#define FRF_AZ_SRAM_OOB_INT_CHAR_EN_LBN 42
+#define FRF_AZ_SRAM_OOB_INT_CHAR_EN_WIDTH 1
+#define FRF_AZ_BUFID_OOB_INT_CHAR_EN_LBN 41
+#define FRF_AZ_BUFID_OOB_INT_CHAR_EN_WIDTH 1
+#define FRF_AZ_MEM_PERR_INT_CHAR_EN_LBN 40
+#define FRF_AZ_MEM_PERR_INT_CHAR_EN_WIDTH 1
+#define FRF_AZ_RBUF_OWN_INT_CHAR_EN_LBN 39
+#define FRF_AZ_RBUF_OWN_INT_CHAR_EN_WIDTH 1
+#define FRF_AZ_TBUF_OWN_INT_CHAR_EN_LBN 38
+#define FRF_AZ_TBUF_OWN_INT_CHAR_EN_WIDTH 1
+#define FRF_AZ_RDESCQ_OWN_INT_CHAR_EN_LBN 37
+#define FRF_AZ_RDESCQ_OWN_INT_CHAR_EN_WIDTH 1
+#define FRF_AZ_TDESCQ_OWN_INT_CHAR_EN_LBN 36
+#define FRF_AZ_TDESCQ_OWN_INT_CHAR_EN_WIDTH 1
+#define FRF_AZ_EVQ_OWN_INT_CHAR_EN_LBN 35
+#define FRF_AZ_EVQ_OWN_INT_CHAR_EN_WIDTH 1
+#define FRF_AZ_EVF_OFLO_INT_CHAR_EN_LBN 34
+#define FRF_AZ_EVF_OFLO_INT_CHAR_EN_WIDTH 1
+#define FRF_AZ_ILL_ADR_INT_CHAR_EN_LBN 33
+#define FRF_AZ_ILL_ADR_INT_CHAR_EN_WIDTH 1
+#define FRF_AZ_SRM_PERR_INT_CHAR_EN_LBN 32
+#define FRF_AZ_SRM_PERR_INT_CHAR_EN_WIDTH 1
+#define FRF_CZ_SRAM_PERR_INT_P_CHAR_LBN 12
+#define FRF_CZ_SRAM_PERR_INT_P_CHAR_WIDTH 1
+#define FRF_AB_PCI_BUSERR_INT_CHAR_LBN 11
+#define FRF_AB_PCI_BUSERR_INT_CHAR_WIDTH 1
+#define FRF_CZ_MBU_PERR_INT_CHAR_LBN 11
+#define FRF_CZ_MBU_PERR_INT_CHAR_WIDTH 1
+#define FRF_AZ_SRAM_OOB_INT_CHAR_LBN 10
+#define FRF_AZ_SRAM_OOB_INT_CHAR_WIDTH 1
+#define FRF_AZ_BUFID_DC_OOB_INT_CHAR_LBN 9
+#define FRF_AZ_BUFID_DC_OOB_INT_CHAR_WIDTH 1
+#define FRF_AZ_MEM_PERR_INT_CHAR_LBN 8
+#define FRF_AZ_MEM_PERR_INT_CHAR_WIDTH 1
+#define FRF_AZ_RBUF_OWN_INT_CHAR_LBN 7
+#define FRF_AZ_RBUF_OWN_INT_CHAR_WIDTH 1
+#define FRF_AZ_TBUF_OWN_INT_CHAR_LBN 6
+#define FRF_AZ_TBUF_OWN_INT_CHAR_WIDTH 1
+#define FRF_AZ_RDESCQ_OWN_INT_CHAR_LBN 5
+#define FRF_AZ_RDESCQ_OWN_INT_CHAR_WIDTH 1
+#define FRF_AZ_TDESCQ_OWN_INT_CHAR_LBN 4
+#define FRF_AZ_TDESCQ_OWN_INT_CHAR_WIDTH 1
+#define FRF_AZ_EVQ_OWN_INT_CHAR_LBN 3
+#define FRF_AZ_EVQ_OWN_INT_CHAR_WIDTH 1
+#define FRF_AZ_EVF_OFLO_INT_CHAR_LBN 2
+#define FRF_AZ_EVF_OFLO_INT_CHAR_WIDTH 1
+#define FRF_AZ_ILL_ADR_INT_CHAR_LBN 1
+#define FRF_AZ_ILL_ADR_INT_CHAR_WIDTH 1
+#define FRF_AZ_SRM_PERR_INT_CHAR_LBN 0
+#define FRF_AZ_SRM_PERR_INT_CHAR_WIDTH 1
+
+
+/*------------------------------------------------------------*/
+/*
+ * FR_AZ_DP_CTRL_REG(128bit):
+ * Datapath control register
+ */
+#define FR_AZ_DP_CTRL_REG_OFST 0x00000250
+/* falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */
+
+#define FRF_AZ_FLS_EVQ_ID_LBN 0
+#define FRF_AZ_FLS_EVQ_ID_WIDTH 12
+
+
+/*------------------------------------------------------------*/
+/*
+ * FR_AZ_MEM_STAT_REG(128bit):
+ * Memory status register
+ */
+#define FR_AZ_MEM_STAT_REG_OFST 0x00000260
+/* falcona0,falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */
+
+#define FRF_AB_MEM_PERR_VEC_LBN 53
+#define FRF_AB_MEM_PERR_VEC_WIDTH 38
+#define FRF_AB_MBIST_CORR_LBN 38
+#define FRF_AB_MBIST_CORR_WIDTH 15
+#define FRF_AB_MBIST_ERR_LBN 0
+#define FRF_AB_MBIST_ERR_WIDTH 40
+#define FRF_CZ_MEM_PERR_VEC_LBN 0
+#define FRF_CZ_MEM_PERR_VEC_WIDTH 35
+
+
+/*------------------------------------------------------------*/
+/*
+ * FR_AZ_CS_DEBUG_REG(128bit):
+ * Debug register
+ */
+#define FR_AZ_CS_DEBUG_REG_OFST 0x00000270
+/* falcona0,falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */
+
+#define FRF_AB_GLB_DEBUG2_SEL_LBN 50
+#define FRF_AB_GLB_DEBUG2_SEL_WIDTH 3
+#define FRF_AB_DEBUG_BLK_SEL2_LBN 47
+#define FRF_AB_DEBUG_BLK_SEL2_WIDTH 3
+#define FRF_AB_DEBUG_BLK_SEL1_LBN 44
+#define FRF_AB_DEBUG_BLK_SEL1_WIDTH 3
+#define FRF_AB_DEBUG_BLK_SEL0_LBN 41
+#define FRF_AB_DEBUG_BLK_SEL0_WIDTH 3
+#define FRF_CZ_CS_PORT_NUM_LBN 40
+#define FRF_CZ_CS_PORT_NUM_WIDTH 2
+#define FRF_AB_MISC_DEBUG_ADDR_LBN 36
+#define FRF_AB_MISC_DEBUG_ADDR_WIDTH 5
+#define FRF_AB_SERDES_DEBUG_ADDR_LBN 31
+#define FRF_AB_SERDES_DEBUG_ADDR_WIDTH 5
+#define FRF_CZ_CS_PORT_FPE_LBN 1
+#define FRF_CZ_CS_PORT_FPE_WIDTH 35
+#define FRF_AB_EM_DEBUG_ADDR_LBN 26
+#define FRF_AB_EM_DEBUG_ADDR_WIDTH 5
+#define FRF_AB_SR_DEBUG_ADDR_LBN 21
+#define FRF_AB_SR_DEBUG_ADDR_WIDTH 5
+#define FRF_AB_EV_DEBUG_ADDR_LBN 16
+#define FRF_AB_EV_DEBUG_ADDR_WIDTH 5
+#define FRF_AB_RX_DEBUG_ADDR_LBN 11
+#define FRF_AB_RX_DEBUG_ADDR_WIDTH 5
+#define FRF_AB_TX_DEBUG_ADDR_LBN 6
+#define FRF_AB_TX_DEBUG_ADDR_WIDTH 5
+#define FRF_AB_CS_BIU_DEBUG_ADDR_LBN 1
+#define FRF_AB_CS_BIU_DEBUG_ADDR_WIDTH 5
+#define FRF_AZ_CS_DEBUG_EN_LBN 0
+#define FRF_AZ_CS_DEBUG_EN_WIDTH 1
+
+
+/*------------------------------------------------------------*/
+/*
+ * FR_AZ_DRIVER_REG(128bit):
+ * Driver scratch register [0-7]
+ */
+#define FR_AZ_DRIVER_REG_OFST 0x00000280
+/* falcona0,falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */
+#define FR_AZ_DRIVER_REG_STEP 16
+#define FR_AZ_DRIVER_REG_ROWS 8
+
+#define FRF_AZ_DRIVER_DW0_LBN 0
+#define FRF_AZ_DRIVER_DW0_WIDTH 32
+
+
+/*------------------------------------------------------------*/
+/*
+ * FR_AZ_ALTERA_BUILD_REG(128bit):
+ * Altera build register
+ */
+#define FR_AZ_ALTERA_BUILD_REG_OFST 0x00000300
+/* falcona0,falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */
+
+#define FRF_AZ_ALTERA_BUILD_VER_LBN 0
+#define FRF_AZ_ALTERA_BUILD_VER_WIDTH 32
+
+
+/*------------------------------------------------------------*/
+/*
+ * FR_AZ_CSR_SPARE_REG(128bit):
+ * Spare register
+ */
+#define FR_AZ_CSR_SPARE_REG_OFST 0x00000310
+/* falcona0,falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */
+
+#define FRF_AB_MEM_PERR_EN_LBN 64
+#define FRF_AB_MEM_PERR_EN_WIDTH 38
+#define FRF_CZ_MEM_PERR_EN_LBN 64
+#define FRF_CZ_MEM_PERR_EN_WIDTH 35
+#define FRF_AB_MEM_PERR_EN_TX_DATA_LBN 72
+#define FRF_AB_MEM_PERR_EN_TX_DATA_WIDTH 2
+#define FRF_AZ_CSR_SPARE_BITS_LBN 0
+#define FRF_AZ_CSR_SPARE_BITS_WIDTH 32
+
+
+/*------------------------------------------------------------*/
+/*
+ * FR_AB_PCIE_SD_CTL0123_REG(128bit):
+ * PCIE SerDes control register 0 to 3
+ */
+#define FR_AB_PCIE_SD_CTL0123_REG_OFST 0x00000320
+/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */
+
+#define FRF_AB_PCIE_TESTSIG_H_LBN 96
+#define FRF_AB_PCIE_TESTSIG_H_WIDTH 19
+#define FRF_AB_PCIE_TESTSIG_L_LBN 64
+#define FRF_AB_PCIE_TESTSIG_L_WIDTH 19
+#define FRF_AB_PCIE_OFFSET_LBN 56
+#define FRF_AB_PCIE_OFFSET_WIDTH 8
+#define FRF_AB_PCIE_OFFSETEN_H_LBN 55
+#define FRF_AB_PCIE_OFFSETEN_H_WIDTH 1
+#define FRF_AB_PCIE_OFFSETEN_L_LBN 54
+#define FRF_AB_PCIE_OFFSETEN_L_WIDTH 1
+#define FRF_AB_PCIE_HIVMODE_H_LBN 53
+#define FRF_AB_PCIE_HIVMODE_H_WIDTH 1
+#define FRF_AB_PCIE_HIVMODE_L_LBN 52
+#define FRF_AB_PCIE_HIVMODE_L_WIDTH 1
+#define FRF_AB_PCIE_PARRESET_H_LBN 51
+#define FRF_AB_PCIE_PARRESET_H_WIDTH 1
+#define FRF_AB_PCIE_PARRESET_L_LBN 50
+#define FRF_AB_PCIE_PARRESET_L_WIDTH 1
+#define FRF_AB_PCIE_LPBKWDRV_H_LBN 49
+#define FRF_AB_PCIE_LPBKWDRV_H_WIDTH 1
+#define FRF_AB_PCIE_LPBKWDRV_L_LBN 48
+#define FRF_AB_PCIE_LPBKWDRV_L_WIDTH 1
+#define FRF_AB_PCIE_LPBK_LBN 40
+#define FRF_AB_PCIE_LPBK_WIDTH 8
+#define FRF_AB_PCIE_PARLPBK_LBN 32
+#define FRF_AB_PCIE_PARLPBK_WIDTH 8
+#define FRF_AB_PCIE_RXTERMADJ_H_LBN 30
+#define FRF_AB_PCIE_RXTERMADJ_H_WIDTH 2
+#define FRF_AB_PCIE_RXTERMADJ_L_LBN 28
+#define FRF_AB_PCIE_RXTERMADJ_L_WIDTH 2
+#define FFE_AB_PCIE_RXTERMADJ_MIN15PCNT 3
+#define FFE_AB_PCIE_RXTERMADJ_PL10PCNT 2
+#define FFE_AB_PCIE_RXTERMADJ_MIN17PCNT 1
+#define FFE_AB_PCIE_RXTERMADJ_NOMNL 0
+#define FRF_AB_PCIE_TXTERMADJ_H_LBN 26
+#define FRF_AB_PCIE_TXTERMADJ_H_WIDTH 2
+#define FRF_AB_PCIE_TXTERMADJ_L_LBN 24
+#define FRF_AB_PCIE_TXTERMADJ_L_WIDTH 2
+#define FFE_AB_PCIE_TXTERMADJ_MIN15PCNT 3
+#define FFE_AB_PCIE_TXTERMADJ_PL10PCNT 2
+#define FFE_AB_PCIE_TXTERMADJ_MIN17PCNT 1
+#define FFE_AB_PCIE_TXTERMADJ_NOMNL 0
+#define FRF_AB_PCIE_RXEQCTL_H_LBN 18
+#define FRF_AB_PCIE_RXEQCTL_H_WIDTH 2
+#define FRF_AB_PCIE_RXEQCTL_L_LBN 16
+#define FRF_AB_PCIE_RXEQCTL_L_WIDTH 2
+#define FFE_AB_PCIE_RXEQCTL_OFF_ALT 3
+#define FFE_AB_PCIE_RXEQCTL_OFF 2
+#define FFE_AB_PCIE_RXEQCTL_MIN 1
+#define FFE_AB_PCIE_RXEQCTL_MAX 0
+#define FRF_AB_PCIE_HIDRV_LBN 8
+#define FRF_AB_PCIE_HIDRV_WIDTH 8
+#define FRF_AB_PCIE_LODRV_LBN 0
+#define FRF_AB_PCIE_LODRV_WIDTH 8
+
+
+/*------------------------------------------------------------*/
+/*
+ * FR_AB_PCIE_SD_CTL45_REG(128bit):
+ * PCIE SerDes control register 4 and 5
+ */
+#define FR_AB_PCIE_SD_CTL45_REG_OFST 0x00000330
+/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */
+
+#define FRF_AB_PCIE_DTX7_LBN 60
+#define FRF_AB_PCIE_DTX7_WIDTH 4
+#define FRF_AB_PCIE_DTX6_LBN 56
+#define FRF_AB_PCIE_DTX6_WIDTH 4
+#define FRF_AB_PCIE_DTX5_LBN 52
+#define FRF_AB_PCIE_DTX5_WIDTH 4
+#define FRF_AB_PCIE_DTX4_LBN 48
+#define FRF_AB_PCIE_DTX4_WIDTH 4
+#define FRF_AB_PCIE_DTX3_LBN 44
+#define FRF_AB_PCIE_DTX3_WIDTH 4
+#define FRF_AB_PCIE_DTX2_LBN 40
+#define FRF_AB_PCIE_DTX2_WIDTH 4
+#define FRF_AB_PCIE_DTX1_LBN 36
+#define FRF_AB_PCIE_DTX1_WIDTH 4
+#define FRF_AB_PCIE_DTX0_LBN 32
+#define FRF_AB_PCIE_DTX0_WIDTH 4
+#define FRF_AB_PCIE_DEQ7_LBN 28
+#define FRF_AB_PCIE_DEQ7_WIDTH 4
+#define FRF_AB_PCIE_DEQ6_LBN 24
+#define FRF_AB_PCIE_DEQ6_WIDTH 4
+#define FRF_AB_PCIE_DEQ5_LBN 20
+#define FRF_AB_PCIE_DEQ5_WIDTH 4
+#define FRF_AB_PCIE_DEQ4_LBN 16
+#define FRF_AB_PCIE_DEQ4_WIDTH 4
+#define FRF_AB_PCIE_DEQ3_LBN 12
+#define FRF_AB_PCIE_DEQ3_WIDTH 4
+#define FRF_AB_PCIE_DEQ2_LBN 8
+#define FRF_AB_PCIE_DEQ2_WIDTH 4
+#define FRF_AB_PCIE_DEQ1_LBN 4
+#define FRF_AB_PCIE_DEQ1_WIDTH 4
+#define FRF_AB_PCIE_DEQ0_LBN 0
+#define FRF_AB_PCIE_DEQ0_WIDTH 4
+
+
+/*------------------------------------------------------------*/
+/*
+ * FR_AB_PCIE_PCS_CTL_STAT_REG(128bit):
+ * PCIE PCS control and status register
+ */
+#define FR_AB_PCIE_PCS_CTL_STAT_REG_OFST 0x00000340
+/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */
+
+#define FRF_AB_PCIE_PRBSERRCOUNT0_H_LBN 52
+#define FRF_AB_PCIE_PRBSERRCOUNT0_H_WIDTH 4
+#define FRF_AB_PCIE_PRBSERRCOUNT0_L_LBN 48
+#define FRF_AB_PCIE_PRBSERRCOUNT0_L_WIDTH 4
+#define FRF_AB_PCIE_PRBSERR_LBN 40
+#define FRF_AB_PCIE_PRBSERR_WIDTH 8
+#define FRF_AB_PCIE_PRBSERRH0_LBN 32
+#define FRF_AB_PCIE_PRBSERRH0_WIDTH 8
+#define FRF_AB_PCIE_FASTINIT_H_LBN 15
+#define FRF_AB_PCIE_FASTINIT_H_WIDTH 1
+#define FRF_AB_PCIE_FASTINIT_L_LBN 14
+#define FRF_AB_PCIE_FASTINIT_L_WIDTH 1
+#define FRF_AB_PCIE_CTCDISABLE_H_LBN 13
+#define FRF_AB_PCIE_CTCDISABLE_H_WIDTH 1
+#define FRF_AB_PCIE_CTCDISABLE_L_LBN 12
+#define FRF_AB_PCIE_CTCDISABLE_L_WIDTH 1
+#define FRF_AB_PCIE_PRBSSYNC_H_LBN 11
+#define FRF_AB_PCIE_PRBSSYNC_H_WIDTH 1
+#define FRF_AB_PCIE_PRBSSYNC_L_LBN 10
+#define FRF_AB_PCIE_PRBSSYNC_L_WIDTH 1
+#define FRF_AB_PCIE_PRBSERRACK_H_LBN 9
+#define FRF_AB_PCIE_PRBSERRACK_H_WIDTH 1
+#define FRF_AB_PCIE_PRBSERRACK_L_LBN 8
+#define FRF_AB_PCIE_PRBSERRACK_L_WIDTH 1
+#define FRF_AB_PCIE_PRBSSEL_LBN 0
+#define FRF_AB_PCIE_PRBSSEL_WIDTH 8
+
+
+/*------------------------------------------------------------*/
+/*
+ * FR_BB_DEBUG_DATA_OUT_REG(128bit):
+ * Live Debug and Debug 2 out ports
+ */
+#define FR_BB_DEBUG_DATA_OUT_REG_OFST 0x00000350
+/* falconb0=net_func_bar2 */
+
+#define FRF_BB_DEBUG2_PORT_LBN 25
+#define FRF_BB_DEBUG2_PORT_WIDTH 15
+#define FRF_BB_DEBUG1_PORT_LBN 0
+#define FRF_BB_DEBUG1_PORT_WIDTH 25
+
+
+/*------------------------------------------------------------*/
+/*
+ * FR_BZ_EVQ_RPTR_REGP0(32bit):
+ * Event queue read pointer register
+ */
+#define FR_BZ_EVQ_RPTR_REGP0_OFST 0x00000400
+/* falconb0,sienaa0=net_func_bar2 */
+#define FR_BZ_EVQ_RPTR_REGP0_STEP 8192
+#define FR_BZ_EVQ_RPTR_REGP0_ROWS 1024
+/*
+ * FR_AA_EVQ_RPTR_REG_KER(32bit):
+ * Event queue read pointer register
+ */
+#define FR_AA_EVQ_RPTR_REG_KER_OFST 0x00011b00
+/* falcona0=net_func_bar2 */
+#define FR_AA_EVQ_RPTR_REG_KER_STEP 4
+#define FR_AA_EVQ_RPTR_REG_KER_ROWS 4
+/*
+ * FR_AZ_EVQ_RPTR_REG(32bit):
+ * Event queue read pointer register
+ */
+#define FR_AZ_EVQ_RPTR_REG_OFST 0x00fa0000
+/* falconb0=net_func_bar2,sienaa0=net_func_bar2,falcona0=char_func_bar0 */
+#define FR_AZ_EVQ_RPTR_REG_STEP 16
+#define FR_AB_EVQ_RPTR_REG_ROWS 4096
+#define FR_CZ_EVQ_RPTR_REG_ROWS 1024
+/*
+ * FR_BB_EVQ_RPTR_REGP123(32bit):
+ * Event queue read pointer register
+ */
+#define FR_BB_EVQ_RPTR_REGP123_OFST 0x01000400
+/* falconb0=net_func_bar2 */
+#define FR_BB_EVQ_RPTR_REGP123_STEP 8192
+#define FR_BB_EVQ_RPTR_REGP123_ROWS 3072
+
+#define FRF_AZ_EVQ_RPTR_VLD_LBN 15
+#define FRF_AZ_EVQ_RPTR_VLD_WIDTH 1
+#define FRF_AZ_EVQ_RPTR_LBN 0
+#define FRF_AZ_EVQ_RPTR_WIDTH 15
+
+
+/*------------------------------------------------------------*/
+/*
+ * FR_BZ_TIMER_COMMAND_REGP0(128bit):
+ * Timer Command Registers
+ */
+#define FR_BZ_TIMER_COMMAND_REGP0_OFST 0x00000420
+/* falconb0,sienaa0=net_func_bar2 */
+#define FR_AZ_TIMER_COMMAND_REGP0_STEP 8192
+#define FR_BZ_TIMER_COMMAND_REGP0_ROWS 1024
+/*
+ * FR_AA_TIMER_COMMAND_REG_KER(128bit):
+ * Timer Command Registers
+ */
+#define FR_AA_TIMER_COMMAND_REG_KER_OFST 0x00000420
+/* falcona0=net_func_bar2 */
+#define FR_AA_TIMER_COMMAND_REG_KER_STEP 8192
+#define FR_AA_TIMER_COMMAND_REG_KER_ROWS 4
+/*
+ * FR_AB_TIMER_COMMAND_REGP123(128bit):
+ * Timer Command Registers
+ */
+#define FR_AB_TIMER_COMMAND_REGP123_OFST 0x01000420
+/* falconb0=net_func_bar2,falcona0=char_func_bar0 */
+#define FR_AB_TIMER_COMMAND_REGP123_STEP 8192
+#define FR_AB_TIMER_COMMAND_REGP123_ROWS 3072
+/*
+ * FR_AA_TIMER_COMMAND_REGP0(128bit):
+ * Timer Command Registers
+ */
+#define FR_AA_TIMER_COMMAND_REGP0_OFST 0x00008420
+/* falcona0=char_func_bar0 */
+/* FR_AZ_TIMER_COMMAND_REGP0_STEP 8192 */
+#define FR_AA_TIMER_COMMAND_REGP0_ROWS 1020
+
+#define FRF_CZ_TC_TIMER_MODE_LBN 14
+#define FRF_CZ_TC_TIMER_MODE_WIDTH 2
+#define FRF_AB_TC_TIMER_MODE_LBN 12
+#define FRF_AB_TC_TIMER_MODE_WIDTH 2
+#define FRF_CZ_TC_TIMER_VAL_LBN 0
+#define FRF_CZ_TC_TIMER_VAL_WIDTH 14
+#define FRF_AB_TC_TIMER_VAL_LBN 0
+#define FRF_AB_TC_TIMER_VAL_WIDTH 12
+
+
+/*------------------------------------------------------------*/
+/*
+ * FR_AZ_DRV_EV_REG(128bit):
+ * Driver generated event register
+ */
+#define FR_AZ_DRV_EV_REG_OFST 0x00000440
+/* falcona0,falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */
+
+#define FRF_AZ_DRV_EV_QID_LBN 64
+#define FRF_AZ_DRV_EV_QID_WIDTH 12
+#define FRF_AZ_DRV_EV_DATA_LBN 0
+#define FRF_AZ_DRV_EV_DATA_WIDTH 64
+
+
+/*------------------------------------------------------------*/
+/*
+ * FR_AZ_EVQ_CTL_REG(128bit):
+ * Event queue control register
+ */
+#define FR_AZ_EVQ_CTL_REG_OFST 0x00000450
+/* falcona0,falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */
+
+#define FRF_CZ_RX_EVQ_WAKEUP_MASK_LBN 15
+#define FRF_CZ_RX_EVQ_WAKEUP_MASK_WIDTH 10
+#define FRF_BB_RX_EVQ_WAKEUP_MASK_LBN 15
+#define FRF_BB_RX_EVQ_WAKEUP_MASK_WIDTH 6
+#define FRF_AZ_EVQ_OWNERR_CTL_LBN 14
+#define FRF_AZ_EVQ_OWNERR_CTL_WIDTH 1
+#define FRF_AZ_EVQ_FIFO_AF_TH_LBN 7
+#define FRF_AZ_EVQ_FIFO_AF_TH_WIDTH 7
+#define FRF_AZ_EVQ_FIFO_NOTAF_TH_LBN 0
+#define FRF_AZ_EVQ_FIFO_NOTAF_TH_WIDTH 7
+
+
+/*------------------------------------------------------------*/
+/*
+ * FR_AZ_EVQ_CNT1_REG(128bit):
+ * Event counter 1 register
+ */
+#define FR_AZ_EVQ_CNT1_REG_OFST 0x00000460
+/* falcona0,falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */
+
+#define FRF_AZ_EVQ_CNT_PRE_FIFO_LBN 120
+#define FRF_AZ_EVQ_CNT_PRE_FIFO_WIDTH 7
+#define FRF_AZ_EVQ_CNT_TOBIU_LBN 100
+#define FRF_AZ_EVQ_CNT_TOBIU_WIDTH 20
+#define FRF_AZ_EVQ_TX_REQ_CNT_LBN 80
+#define FRF_AZ_EVQ_TX_REQ_CNT_WIDTH 20
+#define FRF_AZ_EVQ_RX_REQ_CNT_LBN 60
+#define FRF_AZ_EVQ_RX_REQ_CNT_WIDTH 20
+#define FRF_AZ_EVQ_EM_REQ_CNT_LBN 40
+#define FRF_AZ_EVQ_EM_REQ_CNT_WIDTH 20
+#define FRF_AZ_EVQ_CSR_REQ_CNT_LBN 20
+#define FRF_AZ_EVQ_CSR_REQ_CNT_WIDTH 20
+#define FRF_AZ_EVQ_ERR_REQ_CNT_LBN 0
+#define FRF_AZ_EVQ_ERR_REQ_CNT_WIDTH 20
+
+
+/*------------------------------------------------------------*/
+/*
+ * FR_AZ_EVQ_CNT2_REG(128bit):
+ * Event counter 2 register
+ */
+#define FR_AZ_EVQ_CNT2_REG_OFST 0x00000470
+/* falcona0,falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */
+
+#define FRF_AZ_EVQ_UPD_REQ_CNT_LBN 104
+#define FRF_AZ_EVQ_UPD_REQ_CNT_WIDTH 20
+#define FRF_AZ_EVQ_CLR_REQ_CNT_LBN 84
+#define FRF_AZ_EVQ_CLR_REQ_CNT_WIDTH 20
+#define FRF_AZ_EVQ_RDY_CNT_LBN 80
+#define FRF_AZ_EVQ_RDY_CNT_WIDTH 4
+#define FRF_AZ_EVQ_WU_REQ_CNT_LBN 60
+#define FRF_AZ_EVQ_WU_REQ_CNT_WIDTH 20
+#define FRF_AZ_EVQ_WET_REQ_CNT_LBN 40
+#define FRF_AZ_EVQ_WET_REQ_CNT_WIDTH 20
+#define FRF_AZ_EVQ_INIT_REQ_CNT_LBN 20
+#define FRF_AZ_EVQ_INIT_REQ_CNT_WIDTH 20
+#define FRF_AZ_EVQ_TM_REQ_CNT_LBN 0
+#define FRF_AZ_EVQ_TM_REQ_CNT_WIDTH 20
+
+
+/*------------------------------------------------------------*/
+/*
+ * FR_CZ_USR_EV_REG(32bit):
+ * Event mailbox register
+ */
+#define FR_CZ_USR_EV_REG_OFST 0x00000540
+/* sienaa0=net_func_bar2 */
+#define FR_CZ_USR_EV_REG_STEP 8192
+#define FR_CZ_USR_EV_REG_ROWS 1024
+
+#define FRF_CZ_USR_EV_DATA_LBN 0
+#define FRF_CZ_USR_EV_DATA_WIDTH 32
+
+
+/*------------------------------------------------------------*/
+/*
+ * FR_AZ_BUF_TBL_CFG_REG(128bit):
+ * Buffer table configuration register
+ */
+#define FR_AZ_BUF_TBL_CFG_REG_OFST 0x00000600
+/* falcona0,falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */
+
+#define FRF_AZ_BUF_TBL_MODE_LBN 3
+#define FRF_AZ_BUF_TBL_MODE_WIDTH 1
+
+
+/*------------------------------------------------------------*/
+/*
+ * FR_AZ_SRM_RX_DC_CFG_REG(128bit):
+ * SRAM receive descriptor cache configuration register
+ */
+#define FR_AZ_SRM_RX_DC_CFG_REG_OFST 0x00000610
+/* falcona0,falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */
+
+#define FRF_AZ_SRM_CLK_TMP_EN_LBN 21
+#define FRF_AZ_SRM_CLK_TMP_EN_WIDTH 1
+#define FRF_AZ_SRM_RX_DC_BASE_ADR_LBN 0
+#define FRF_AZ_SRM_RX_DC_BASE_ADR_WIDTH 21
+
+
+/*------------------------------------------------------------*/
+/*
+ * FR_AZ_SRM_TX_DC_CFG_REG(128bit):
+ * SRAM transmit descriptor cache configuration register
+ */
+#define FR_AZ_SRM_TX_DC_CFG_REG_OFST 0x00000620
+/* falcona0,falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */
+
+#define FRF_AZ_SRM_TX_DC_BASE_ADR_LBN 0
+#define FRF_AZ_SRM_TX_DC_BASE_ADR_WIDTH 21
+
+
+/*------------------------------------------------------------*/
+/*
+ * FR_AZ_SRM_CFG_REG(128bit):
+ * SRAM configuration register
+ */
+#define FR_AZ_SRM_CFG_REG_OFST 0x00000630
+/* falcona0,falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */
+
+#define FRF_AZ_SRM_OOB_ADR_INTEN_LBN 5
+#define FRF_AZ_SRM_OOB_ADR_INTEN_WIDTH 1
+#define FRF_AZ_SRM_OOB_BUF_INTEN_LBN 4
+#define FRF_AZ_SRM_OOB_BUF_INTEN_WIDTH 1
+#define FRF_AZ_SRM_INIT_EN_LBN 3
+#define FRF_AZ_SRM_INIT_EN_WIDTH 1
+#define FRF_AZ_SRM_NUM_BANK_LBN 2
+#define FRF_AZ_SRM_NUM_BANK_WIDTH 1
+#define FRF_AZ_SRM_BANK_SIZE_LBN 0
+#define FRF_AZ_SRM_BANK_SIZE_WIDTH 2
+
+
+/*------------------------------------------------------------*/
+/*
+ * FR_AZ_BUF_TBL_UPD_REG(128bit):
+ * Buffer table update register
+ */
+#define FR_AZ_BUF_TBL_UPD_REG_OFST 0x00000650
+/* falcona0,falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */
+
+#define FRF_AZ_BUF_UPD_CMD_LBN 63
+#define FRF_AZ_BUF_UPD_CMD_WIDTH 1
+#define FRF_AZ_BUF_CLR_CMD_LBN 62
+#define FRF_AZ_BUF_CLR_CMD_WIDTH 1
+#define FRF_AZ_BUF_CLR_END_ID_LBN 32
+#define FRF_AZ_BUF_CLR_END_ID_WIDTH 20
+#define FRF_AZ_BUF_CLR_START_ID_LBN 0
+#define FRF_AZ_BUF_CLR_START_ID_WIDTH 20
+
+
+/*------------------------------------------------------------*/
+/*
+ * FR_AZ_SRM_UPD_EVQ_REG(128bit):
+ * Buffer table update register
+ */
+#define FR_AZ_SRM_UPD_EVQ_REG_OFST 0x00000660
+/* falcona0,falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */
+
+#define FRF_AZ_SRM_UPD_EVQ_ID_LBN 0
+#define FRF_AZ_SRM_UPD_EVQ_ID_WIDTH 12
+
+
+/*------------------------------------------------------------*/
+/*
+ * FR_AZ_SRAM_PARITY_REG(128bit):
+ * SRAM parity register.
+ */
+#define FR_AZ_SRAM_PARITY_REG_OFST 0x00000670
+/* falcona0,falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */
+
+#define FRF_CZ_BYPASS_ECC_LBN 3
+#define FRF_CZ_BYPASS_ECC_WIDTH 1
+#define FRF_CZ_SEC_INT_LBN 2
+#define FRF_CZ_SEC_INT_WIDTH 1
+#define FRF_CZ_FORCE_SRAM_DOUBLE_ERR_LBN 1
+#define FRF_CZ_FORCE_SRAM_DOUBLE_ERR_WIDTH 1
+#define FRF_AB_FORCE_SRAM_PERR_LBN 0
+#define FRF_AB_FORCE_SRAM_PERR_WIDTH 1
+#define FRF_CZ_FORCE_SRAM_SINGLE_ERR_LBN 0
+#define FRF_CZ_FORCE_SRAM_SINGLE_ERR_WIDTH 1
+
+
+/*------------------------------------------------------------*/
+/*
+ * FR_AZ_RX_CFG_REG(128bit):
+ * Receive configuration register
+ */
+#define FR_AZ_RX_CFG_REG_OFST 0x00000800
+/* falcona0,falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */
+
+#define FRF_CZ_RX_MIN_KBUF_SIZE_LBN 72
+#define FRF_CZ_RX_MIN_KBUF_SIZE_WIDTH 14
+#define FRF_CZ_RX_HDR_SPLIT_EN_LBN 71
+#define FRF_CZ_RX_HDR_SPLIT_EN_WIDTH 1
+#define FRF_CZ_RX_HDR_SPLIT_PLD_BUF_SIZE_LBN 62
+#define FRF_CZ_RX_HDR_SPLIT_PLD_BUF_SIZE_WIDTH 9
+#define FRF_CZ_RX_HDR_SPLIT_HDR_BUF_SIZE_LBN 53
+#define FRF_CZ_RX_HDR_SPLIT_HDR_BUF_SIZE_WIDTH 9
+#define FRF_CZ_RX_PRE_RFF_IPG_LBN 49
+#define FRF_CZ_RX_PRE_RFF_IPG_WIDTH 4
+#define FRF_BZ_RX_TCP_SUP_LBN 48
+#define FRF_BZ_RX_TCP_SUP_WIDTH 1
+#define FRF_BZ_RX_INGR_EN_LBN 47
+#define FRF_BZ_RX_INGR_EN_WIDTH 1
+#define FRF_BZ_RX_IP_HASH_LBN 46
+#define FRF_BZ_RX_IP_HASH_WIDTH 1
+#define FRF_BZ_RX_HASH_ALG_LBN 45
+#define FRF_BZ_RX_HASH_ALG_WIDTH 1
+#define FRF_BZ_RX_HASH_INSRT_HDR_LBN 44
+#define FRF_BZ_RX_HASH_INSRT_HDR_WIDTH 1
+#define FRF_BZ_RX_DESC_PUSH_EN_LBN 43
+#define FRF_BZ_RX_DESC_PUSH_EN_WIDTH 1
+#define FRF_BZ_RX_RDW_PATCH_EN_LBN 42
+#define FRF_BZ_RX_RDW_PATCH_EN_WIDTH 1
+#define FRF_BB_RX_PCI_BURST_SIZE_LBN 39
+#define FRF_BB_RX_PCI_BURST_SIZE_WIDTH 3
+#define FRF_BZ_RX_OWNERR_CTL_LBN 38
+#define FRF_BZ_RX_OWNERR_CTL_WIDTH 1
+#define FRF_BZ_RX_XON_TX_TH_LBN 33
+#define FRF_BZ_RX_XON_TX_TH_WIDTH 5
+#define FRF_AA_RX_DESC_PUSH_EN_LBN 35
+#define FRF_AA_RX_DESC_PUSH_EN_WIDTH 1
+#define FRF_AA_RX_RDW_PATCH_EN_LBN 34
+#define FRF_AA_RX_RDW_PATCH_EN_WIDTH 1
+#define FRF_AA_RX_PCI_BURST_SIZE_LBN 31
+#define FRF_AA_RX_PCI_BURST_SIZE_WIDTH 3
+#define FRF_BZ_RX_XOFF_TX_TH_LBN 28
+#define FRF_BZ_RX_XOFF_TX_TH_WIDTH 5
+#define FRF_AA_RX_OWNERR_CTL_LBN 30
+#define FRF_AA_RX_OWNERR_CTL_WIDTH 1
+#define FRF_AA_RX_XON_TX_TH_LBN 25
+#define FRF_AA_RX_XON_TX_TH_WIDTH 5
+#define FRF_BZ_RX_USR_BUF_SIZE_LBN 19
+#define FRF_BZ_RX_USR_BUF_SIZE_WIDTH 9
+#define FRF_AA_RX_XOFF_TX_TH_LBN 20
+#define FRF_AA_RX_XOFF_TX_TH_WIDTH 5
+#define FRF_AA_RX_USR_BUF_SIZE_LBN 11
+#define FRF_AA_RX_USR_BUF_SIZE_WIDTH 9
+#define FRF_BZ_RX_XON_MAC_TH_LBN 10
+#define FRF_BZ_RX_XON_MAC_TH_WIDTH 9
+#define FRF_AA_RX_XON_MAC_TH_LBN 6
+#define FRF_AA_RX_XON_MAC_TH_WIDTH 5
+#define FRF_BZ_RX_XOFF_MAC_TH_LBN 1
+#define FRF_BZ_RX_XOFF_MAC_TH_WIDTH 9
+#define FRF_AA_RX_XOFF_MAC_TH_LBN 1
+#define FRF_AA_RX_XOFF_MAC_TH_WIDTH 5
+#define FRF_AZ_RX_XOFF_MAC_EN_LBN 0
+#define FRF_AZ_RX_XOFF_MAC_EN_WIDTH 1
+
+
+/*------------------------------------------------------------*/
+/*
+ * FR_AZ_RX_FILTER_CTL_REG(128bit):
+ * Receive filter control registers
+ */
+#define FR_AZ_RX_FILTER_CTL_REG_OFST 0x00000810
+/* falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */
+
+#define FRF_CZ_ETHERNET_WILDCARD_SEARCH_LIMIT_LBN 94
+#define FRF_CZ_ETHERNET_WILDCARD_SEARCH_LIMIT_WIDTH 8
+#define FRF_CZ_ETHERNET_FULL_SEARCH_LIMIT_LBN 86
+#define FRF_CZ_ETHERNET_FULL_SEARCH_LIMIT_WIDTH 8
+#define FRF_CZ_RX_FILTER_ALL_VLAN_ETHERTYPES_LBN 85
+#define FRF_CZ_RX_FILTER_ALL_VLAN_ETHERTYPES_WIDTH 1
+#define FRF_CZ_RX_VLAN_MATCH_ETHERTYPE_LBN 69
+#define FRF_CZ_RX_VLAN_MATCH_ETHERTYPE_WIDTH 16
+#define FRF_CZ_MULTICAST_NOMATCH_Q_ID_LBN 57
+#define FRF_CZ_MULTICAST_NOMATCH_Q_ID_WIDTH 12
+#define FRF_CZ_MULTICAST_NOMATCH_RSS_ENABLED_LBN 56
+#define FRF_CZ_MULTICAST_NOMATCH_RSS_ENABLED_WIDTH 1
+#define FRF_CZ_MULTICAST_NOMATCH_IP_OVERRIDE_LBN 55
+#define FRF_CZ_MULTICAST_NOMATCH_IP_OVERRIDE_WIDTH 1
+#define FRF_CZ_UNICAST_NOMATCH_Q_ID_LBN 43
+#define FRF_CZ_UNICAST_NOMATCH_Q_ID_WIDTH 12
+#define FRF_CZ_UNICAST_NOMATCH_RSS_ENABLED_LBN 42
+#define FRF_CZ_UNICAST_NOMATCH_RSS_ENABLED_WIDTH 1
+#define FRF_CZ_UNICAST_NOMATCH_IP_OVERRIDE_LBN 41
+#define FRF_CZ_UNICAST_NOMATCH_IP_OVERRIDE_WIDTH 1
+#define FRF_BZ_SCATTER_ENBL_NO_MATCH_Q_LBN 40
+#define FRF_BZ_SCATTER_ENBL_NO_MATCH_Q_WIDTH 1
+#define FRF_AZ_UDP_FULL_SRCH_LIMIT_LBN 32
+#define FRF_AZ_UDP_FULL_SRCH_LIMIT_WIDTH 8
+#define FRF_AZ_NUM_KER_LBN 24
+#define FRF_AZ_NUM_KER_WIDTH 2
+#define FRF_AZ_UDP_WILD_SRCH_LIMIT_LBN 16
+#define FRF_AZ_UDP_WILD_SRCH_LIMIT_WIDTH 8
+#define FRF_AZ_TCP_WILD_SRCH_LIMIT_LBN 8
+#define FRF_AZ_TCP_WILD_SRCH_LIMIT_WIDTH 8
+#define FRF_AZ_TCP_FULL_SRCH_LIMIT_LBN 0
+#define FRF_AZ_TCP_FULL_SRCH_LIMIT_WIDTH 8
+
+
+/*------------------------------------------------------------*/
+/*
+ * FR_AZ_RX_FLUSH_DESCQ_REG(128bit):
+ * Receive flush descriptor queue register
+ */
+#define FR_AZ_RX_FLUSH_DESCQ_REG_OFST 0x00000820
+/* falcona0,falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */
+
+#define FRF_AZ_RX_FLUSH_DESCQ_CMD_LBN 24
+#define FRF_AZ_RX_FLUSH_DESCQ_CMD_WIDTH 1
+#define FRF_AZ_RX_FLUSH_DESCQ_LBN 0
+#define FRF_AZ_RX_FLUSH_DESCQ_WIDTH 12
+
+
+/*------------------------------------------------------------*/
+/*
+ * FR_BZ_RX_DESC_UPD_REGP0(128bit):
+ * Receive descriptor update register.
+ */
+#define FR_BZ_RX_DESC_UPD_REGP0_OFST 0x00000830
+/* falconb0,sienaa0=net_func_bar2 */
+#define FR_AZ_RX_DESC_UPD_REGP0_STEP 8192
+#define FR_BZ_RX_DESC_UPD_REGP0_ROWS 1024
+/*
+ * FR_AA_RX_DESC_UPD_REG_KER(128bit):
+ * Receive descriptor update register.
+ */
+#define FR_AA_RX_DESC_UPD_REG_KER_OFST 0x00000830
+/* falcona0=net_func_bar2 */
+#define FR_AA_RX_DESC_UPD_REG_KER_STEP 8192
+#define FR_AA_RX_DESC_UPD_REG_KER_ROWS 4
+/*
+ * FR_AB_RX_DESC_UPD_REGP123(128bit):
+ * Receive descriptor update register.
+ */
+#define FR_AB_RX_DESC_UPD_REGP123_OFST 0x01000830
+/* falconb0=net_func_bar2,falcona0=char_func_bar0 */
+#define FR_AB_RX_DESC_UPD_REGP123_STEP 8192
+#define FR_AB_RX_DESC_UPD_REGP123_ROWS 3072
+/*
+ * FR_AA_RX_DESC_UPD_REGP0(128bit):
+ * Receive descriptor update register.
+ */
+#define FR_AA_RX_DESC_UPD_REGP0_OFST 0x00008830
+/* falcona0=char_func_bar0 */
+/* FR_AZ_RX_DESC_UPD_REGP0_STEP 8192 */
+#define FR_AA_RX_DESC_UPD_REGP0_ROWS 1020
+
+#define FRF_AZ_RX_DESC_WPTR_LBN 96
+#define FRF_AZ_RX_DESC_WPTR_WIDTH 12
+#define FRF_AZ_RX_DESC_PUSH_CMD_LBN 95
+#define FRF_AZ_RX_DESC_PUSH_CMD_WIDTH 1
+#define FRF_AZ_RX_DESC_LBN 0
+#define FRF_AZ_RX_DESC_WIDTH 64
+
+
+/*------------------------------------------------------------*/
+/*
+ * FR_AZ_RX_DC_CFG_REG(128bit):
+ * Receive descriptor cache configuration register
+ */
+#define FR_AZ_RX_DC_CFG_REG_OFST 0x00000840
+/* falcona0,falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */
+
+#define FRF_AB_RX_MAX_PF_LBN 2
+#define FRF_AB_RX_MAX_PF_WIDTH 2
+#define FRF_AZ_RX_DC_SIZE_LBN 0
+#define FRF_AZ_RX_DC_SIZE_WIDTH 2
+#define FFE_AZ_RX_DC_SIZE_64 3
+#define FFE_AZ_RX_DC_SIZE_32 2
+#define FFE_AZ_RX_DC_SIZE_16 1
+#define FFE_AZ_RX_DC_SIZE_8 0
+
+
+/*------------------------------------------------------------*/
+/*
+ * FR_AZ_RX_DC_PF_WM_REG(128bit):
+ * Receive descriptor cache pre-fetch watermark register
+ */
+#define FR_AZ_RX_DC_PF_WM_REG_OFST 0x00000850
+/* falcona0,falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */
+
+#define FRF_AZ_RX_DC_PF_HWM_LBN 6
+#define FRF_AZ_RX_DC_PF_HWM_WIDTH 6
+#define FRF_AZ_RX_DC_PF_LWM_LBN 0
+#define FRF_AZ_RX_DC_PF_LWM_WIDTH 6
+
+
+/*------------------------------------------------------------*/
+/*
+ * FR_BZ_RX_RSS_TKEY_REG(128bit):
+ * RSS Toeplitz hash key
+ */
+#define FR_BZ_RX_RSS_TKEY_REG_OFST 0x00000860
+/* falconb0,sienaa0=net_func_bar2 */
+
+#define FRF_BZ_RX_RSS_TKEY_HI_LBN 64
+#define FRF_BZ_RX_RSS_TKEY_HI_WIDTH 64
+#define FRF_BZ_RX_RSS_TKEY_LO_LBN 0
+#define FRF_BZ_RX_RSS_TKEY_LO_WIDTH 64
+
+
+/*------------------------------------------------------------*/
+/*
+ * FR_AZ_RX_NODESC_DROP_REG(128bit):
+ * Receive dropped packet counter register
+ */
+#define FR_AZ_RX_NODESC_DROP_REG_OFST 0x00000880
+/* falcona0,falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */
+
+#define FRF_CZ_RX_NODESC_DROP_CNT_LBN 0
+#define FRF_CZ_RX_NODESC_DROP_CNT_WIDTH 32
+#define FRF_AB_RX_NODESC_DROP_CNT_LBN 0
+#define FRF_AB_RX_NODESC_DROP_CNT_WIDTH 16
+
+
+/*------------------------------------------------------------*/
+/*
+ * FR_AA_RX_SELF_RST_REG(128bit):
+ * Receive self reset register
+ */
+#define FR_AA_RX_SELF_RST_REG_OFST 0x00000890
+/* falcona0=net_func_bar2,falcona0=char_func_bar0 */
+
+#define FRF_AA_RX_ISCSI_DIS_LBN 17
+#define FRF_AA_RX_ISCSI_DIS_WIDTH 1
+#define FRF_AA_RX_SW_RST_REG_LBN 16
+#define FRF_AA_RX_SW_RST_REG_WIDTH 1
+#define FRF_AA_RX_SELF_RST_EN_LBN 8
+#define FRF_AA_RX_SELF_RST_EN_WIDTH 1
+#define FRF_AA_RX_MAX_PF_LAT_LBN 4
+#define FRF_AA_RX_MAX_PF_LAT_WIDTH 4
+#define FRF_AA_RX_MAX_LU_LAT_LBN 0
+#define FRF_AA_RX_MAX_LU_LAT_WIDTH 4
+
+
+/*------------------------------------------------------------*/
+/*
+ * FR_AZ_RX_DEBUG_REG(128bit):
+ * undocumented register
+ */
+#define FR_AZ_RX_DEBUG_REG_OFST 0x000008a0
+/* falcona0,falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */
+
+#define FRF_AZ_RX_DEBUG_LBN 0
+#define FRF_AZ_RX_DEBUG_WIDTH 64
+
+
+/*------------------------------------------------------------*/
+/*
+ * FR_AZ_RX_PUSH_DROP_REG(128bit):
+ * Receive descriptor push dropped counter register
+ */
+#define FR_AZ_RX_PUSH_DROP_REG_OFST 0x000008b0
+/* falcona0,falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */
+
+#define FRF_AZ_RX_PUSH_DROP_CNT_LBN 0
+#define FRF_AZ_RX_PUSH_DROP_CNT_WIDTH 32
+
+
+/*------------------------------------------------------------*/
+/*
+ * FR_CZ_RX_RSS_IPV6_REG1(128bit):
+ * IPv6 RSS Toeplitz hash key low bytes
+ */
+#define FR_CZ_RX_RSS_IPV6_REG1_OFST 0x000008d0
+/* sienaa0=net_func_bar2 */
+
+#define FRF_CZ_RX_RSS_IPV6_TKEY_LO_LBN 0
+#define FRF_CZ_RX_RSS_IPV6_TKEY_LO_WIDTH 128
+
+
+/*------------------------------------------------------------*/
+/*
+ * FR_CZ_RX_RSS_IPV6_REG2(128bit):
+ * IPv6 RSS Toeplitz hash key middle bytes
+ */
+#define FR_CZ_RX_RSS_IPV6_REG2_OFST 0x000008e0
+/* sienaa0=net_func_bar2 */
+
+#define FRF_CZ_RX_RSS_IPV6_TKEY_MID_LBN 0
+#define FRF_CZ_RX_RSS_IPV6_TKEY_MID_WIDTH 128
+
+
+/*------------------------------------------------------------*/
+/*
+ * FR_CZ_RX_RSS_IPV6_REG3(128bit):
+ * IPv6 RSS Toeplitz hash key upper bytes and IPv6 RSS settings
+ */
+#define FR_CZ_RX_RSS_IPV6_REG3_OFST 0x000008f0
+/* sienaa0=net_func_bar2 */
+
+#define FRF_CZ_RX_RSS_IPV6_THASH_ENABLE_LBN 66
+#define FRF_CZ_RX_RSS_IPV6_THASH_ENABLE_WIDTH 1
+#define FRF_CZ_RX_RSS_IPV6_IP_THASH_ENABLE_LBN 65
+#define FRF_CZ_RX_RSS_IPV6_IP_THASH_ENABLE_WIDTH 1
+#define FRF_CZ_RX_RSS_IPV6_TCP_SUPPRESS_LBN 64
+#define FRF_CZ_RX_RSS_IPV6_TCP_SUPPRESS_WIDTH 1
+#define FRF_CZ_RX_RSS_IPV6_TKEY_HI_LBN 0
+#define FRF_CZ_RX_RSS_IPV6_TKEY_HI_WIDTH 64
+
+
+/*------------------------------------------------------------*/
+/*
+ * FR_AZ_TX_FLUSH_DESCQ_REG(128bit):
+ * Transmit flush descriptor queue register
+ */
+#define FR_AZ_TX_FLUSH_DESCQ_REG_OFST 0x00000a00
+/* falcona0,falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */
+
+#define FRF_AZ_TX_FLUSH_DESCQ_CMD_LBN 12
+#define FRF_AZ_TX_FLUSH_DESCQ_CMD_WIDTH 1
+#define FRF_AZ_TX_FLUSH_DESCQ_LBN 0
+#define FRF_AZ_TX_FLUSH_DESCQ_WIDTH 12
+
+
+/*------------------------------------------------------------*/
+/*
+ * FR_BZ_TX_DESC_UPD_REGP0(128bit):
+ * Transmit descriptor update register.
+ */
+#define FR_BZ_TX_DESC_UPD_REGP0_OFST 0x00000a10
+/* falconb0,sienaa0=net_func_bar2 */
+#define FR_AZ_TX_DESC_UPD_REGP0_STEP 8192
+#define FR_BZ_TX_DESC_UPD_REGP0_ROWS 1024
+/*
+ * FR_AA_TX_DESC_UPD_REG_KER(128bit):
+ * Transmit descriptor update register.
+ */
+#define FR_AA_TX_DESC_UPD_REG_KER_OFST 0x00000a10
+/* falcona0=net_func_bar2 */
+#define FR_AA_TX_DESC_UPD_REG_KER_STEP 8192
+#define FR_AA_TX_DESC_UPD_REG_KER_ROWS 8
+/*
+ * FR_AB_TX_DESC_UPD_REGP123(128bit):
+ * Transmit descriptor update register.
+ */
+#define FR_AB_TX_DESC_UPD_REGP123_OFST 0x01000a10
+/* falconb0=net_func_bar2,falcona0=char_func_bar0 */
+#define FR_AB_TX_DESC_UPD_REGP123_STEP 8192
+#define FR_AB_TX_DESC_UPD_REGP123_ROWS 3072
+/*
+ * FR_AA_TX_DESC_UPD_REGP0(128bit):
+ * Transmit descriptor update register.
+ */
+#define FR_AA_TX_DESC_UPD_REGP0_OFST 0x00008a10
+/* falcona0=char_func_bar0 */
+/* FR_AZ_TX_DESC_UPD_REGP0_STEP 8192 */
+#define FR_AA_TX_DESC_UPD_REGP0_ROWS 1020
+
+#define FRF_AZ_TX_DESC_WPTR_LBN 96
+#define FRF_AZ_TX_DESC_WPTR_WIDTH 12
+#define FRF_AZ_TX_DESC_PUSH_CMD_LBN 95
+#define FRF_AZ_TX_DESC_PUSH_CMD_WIDTH 1
+#define FRF_AZ_TX_DESC_LBN 0
+#define FRF_AZ_TX_DESC_WIDTH 95
+
+
+/*------------------------------------------------------------*/
+/*
+ * FR_AZ_TX_DC_CFG_REG(128bit):
+ * Transmit descriptor cache configuration register
+ */
+#define FR_AZ_TX_DC_CFG_REG_OFST 0x00000a20
+/* falcona0,falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */
+
+#define FRF_AZ_TX_DC_SIZE_LBN 0
+#define FRF_AZ_TX_DC_SIZE_WIDTH 2
+#define FFE_AZ_TX_DC_SIZE_32 2
+#define FFE_AZ_TX_DC_SIZE_16 1
+#define FFE_AZ_TX_DC_SIZE_8 0
+
+
+/*------------------------------------------------------------*/
+/*
+ * FR_AA_TX_CHKSM_CFG_REG(128bit):
+ * Transmit checksum configuration register
+ */
+#define FR_AA_TX_CHKSM_CFG_REG_OFST 0x00000a30
+/* falcona0=net_func_bar2,falcona0=char_func_bar0 */
+
+#define FRF_AA_TX_Q_CHKSM_DIS_96_127_LBN 96
+#define FRF_AA_TX_Q_CHKSM_DIS_96_127_WIDTH 32
+#define FRF_AA_TX_Q_CHKSM_DIS_64_95_LBN 64
+#define FRF_AA_TX_Q_CHKSM_DIS_64_95_WIDTH 32
+#define FRF_AA_TX_Q_CHKSM_DIS_32_63_LBN 32
+#define FRF_AA_TX_Q_CHKSM_DIS_32_63_WIDTH 32
+#define FRF_AA_TX_Q_CHKSM_DIS_0_31_LBN 0
+#define FRF_AA_TX_Q_CHKSM_DIS_0_31_WIDTH 32
+
+
+/*------------------------------------------------------------*/
+/*
+ * FR_AZ_TX_CFG_REG(128bit):
+ * Transmit configuration register
+ */
+#define FR_AZ_TX_CFG_REG_OFST 0x00000a50
+/* falcona0,falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */
+
+#define FRF_CZ_TX_CONT_LOOKUP_THRESH_RANGE_LBN 114
+#define FRF_CZ_TX_CONT_LOOKUP_THRESH_RANGE_WIDTH 8
+#define FRF_CZ_TX_FILTER_TEST_MODE_BIT_LBN 113
+#define FRF_CZ_TX_FILTER_TEST_MODE_BIT_WIDTH 1
+#define FRF_CZ_TX_ETH_FILTER_WILD_SEARCH_RANGE_LBN 105
+#define FRF_CZ_TX_ETH_FILTER_WILD_SEARCH_RANGE_WIDTH 8
+#define FRF_CZ_TX_ETH_FILTER_FULL_SEARCH_RANGE_LBN 97
+#define FRF_CZ_TX_ETH_FILTER_FULL_SEARCH_RANGE_WIDTH 8
+#define FRF_CZ_TX_UDPIP_FILTER_WILD_SEARCH_RANGE_LBN 89
+#define FRF_CZ_TX_UDPIP_FILTER_WILD_SEARCH_RANGE_WIDTH 8
+#define FRF_CZ_TX_UDPIP_FILTER_FULL_SEARCH_RANGE_LBN 81
+#define FRF_CZ_TX_UDPIP_FILTER_FULL_SEARCH_RANGE_WIDTH 8
+#define FRF_CZ_TX_TCPIP_FILTER_WILD_SEARCH_RANGE_LBN 73
+#define FRF_CZ_TX_TCPIP_FILTER_WILD_SEARCH_RANGE_WIDTH 8
+#define FRF_CZ_TX_TCPIP_FILTER_FULL_SEARCH_RANGE_LBN 65
+#define FRF_CZ_TX_TCPIP_FILTER_FULL_SEARCH_RANGE_WIDTH 8
+#define FRF_CZ_TX_FILTER_ALL_VLAN_ETHERTYPES_BIT_LBN 64
+#define FRF_CZ_TX_FILTER_ALL_VLAN_ETHERTYPES_BIT_WIDTH 1
+#define FRF_CZ_TX_VLAN_MATCH_ETHERTYPE_RANGE_LBN 48
+#define FRF_CZ_TX_VLAN_MATCH_ETHERTYPE_RANGE_WIDTH 16
+#define FRF_CZ_TX_FILTER_EN_BIT_LBN 47
+#define FRF_CZ_TX_FILTER_EN_BIT_WIDTH 1
+#define FRF_AZ_TX_IP_ID_P0_OFS_LBN 16
+#define FRF_AZ_TX_IP_ID_P0_OFS_WIDTH 15
+#define FRF_AZ_TX_NO_EOP_DISC_EN_LBN 5
+#define FRF_AZ_TX_NO_EOP_DISC_EN_WIDTH 1
+#define FRF_AZ_TX_P1_PRI_EN_LBN 4
+#define FRF_AZ_TX_P1_PRI_EN_WIDTH 1
+#define FRF_AZ_TX_OWNERR_CTL_LBN 2
+#define FRF_AZ_TX_OWNERR_CTL_WIDTH 1
+#define FRF_AA_TX_NON_IP_DROP_DIS_LBN 1
+#define FRF_AA_TX_NON_IP_DROP_DIS_WIDTH 1
+#define FRF_AZ_TX_IP_ID_REP_EN_LBN 0
+#define FRF_AZ_TX_IP_ID_REP_EN_WIDTH 1
+
+
+/*------------------------------------------------------------*/
+/*
+ * FR_AZ_TX_PUSH_DROP_REG(128bit):
+ * Transmit push dropped register
+ */
+#define FR_AZ_TX_PUSH_DROP_REG_OFST 0x00000a60
+/* falcona0,falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */
+
+#define FRF_AZ_TX_PUSH_DROP_CNT_LBN 0
+#define FRF_AZ_TX_PUSH_DROP_CNT_WIDTH 32
+
+
+/*------------------------------------------------------------*/
+/*
+ * FR_AZ_TX_RESERVED_REG(128bit):
+ * Transmit configuration register
+ */
+#define FR_AZ_TX_RESERVED_REG_OFST 0x00000a80
+/* falcona0,falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */
+
+#define FRF_AZ_TX_EVT_CNT_LBN 121
+#define FRF_AZ_TX_EVT_CNT_WIDTH 7
+#define FRF_AZ_TX_PREF_AGE_CNT_LBN 119
+#define FRF_AZ_TX_PREF_AGE_CNT_WIDTH 2
+#define FRF_AZ_TX_RD_COMP_TMR_LBN 96
+#define FRF_AZ_TX_RD_COMP_TMR_WIDTH 23
+#define FRF_AZ_TX_PUSH_EN_LBN 89
+#define FRF_AZ_TX_PUSH_EN_WIDTH 1
+#define FRF_AZ_TX_PUSH_CHK_DIS_LBN 88
+#define FRF_AZ_TX_PUSH_CHK_DIS_WIDTH 1
+#define FRF_AZ_TX_D_FF_FULL_P0_LBN 85
+#define FRF_AZ_TX_D_FF_FULL_P0_WIDTH 1
+#define FRF_AZ_TX_DMAR_ST_P0_LBN 81
+#define FRF_AZ_TX_DMAR_ST_P0_WIDTH 1
+#define FRF_AZ_TX_DMAQ_ST_LBN 78
+#define FRF_AZ_TX_DMAQ_ST_WIDTH 1
+#define FRF_AZ_TX_RX_SPACER_LBN 64
+#define FRF_AZ_TX_RX_SPACER_WIDTH 8
+#define FRF_AZ_TX_DROP_ABORT_EN_LBN 60
+#define FRF_AZ_TX_DROP_ABORT_EN_WIDTH 1
+#define FRF_AZ_TX_SOFT_EVT_EN_LBN 59
+#define FRF_AZ_TX_SOFT_EVT_EN_WIDTH 1
+#define FRF_AZ_TX_PS_EVT_DIS_LBN 58
+#define FRF_AZ_TX_PS_EVT_DIS_WIDTH 1
+#define FRF_AZ_TX_RX_SPACER_EN_LBN 57
+#define FRF_AZ_TX_RX_SPACER_EN_WIDTH 1
+#define FRF_AZ_TX_XP_TIMER_LBN 52
+#define FRF_AZ_TX_XP_TIMER_WIDTH 5
+#define FRF_AZ_TX_PREF_SPACER_LBN 44
+#define FRF_AZ_TX_PREF_SPACER_WIDTH 8
+#define FRF_AZ_TX_PREF_WD_TMR_LBN 22
+#define FRF_AZ_TX_PREF_WD_TMR_WIDTH 22
+#define FRF_AZ_TX_ONLY1TAG_LBN 21
+#define FRF_AZ_TX_ONLY1TAG_WIDTH 1
+#define FRF_AZ_TX_PREF_THRESHOLD_LBN 19
+#define FRF_AZ_TX_PREF_THRESHOLD_WIDTH 2
+#define FRF_AZ_TX_ONE_PKT_PER_Q_LBN 18
+#define FRF_AZ_TX_ONE_PKT_PER_Q_WIDTH 1
+#define FRF_AZ_TX_DIS_NON_IP_EV_LBN 17
+#define FRF_AZ_TX_DIS_NON_IP_EV_WIDTH 1
+#define FRF_AA_TX_DMA_FF_THR_LBN 16
+#define FRF_AA_TX_DMA_FF_THR_WIDTH 1
+#define FRF_AZ_TX_DMA_SPACER_LBN 8
+#define FRF_AZ_TX_DMA_SPACER_WIDTH 8
+#define FRF_AA_TX_TCP_DIS_LBN 7
+#define FRF_AA_TX_TCP_DIS_WIDTH 1
+#define FRF_BZ_TX_FLUSH_MIN_LEN_EN_LBN 7
+#define FRF_BZ_TX_FLUSH_MIN_LEN_EN_WIDTH 1
+#define FRF_AA_TX_IP_DIS_LBN 6
+#define FRF_AA_TX_IP_DIS_WIDTH 1
+#define FRF_AZ_TX_MAX_CPL_LBN 2
+#define FRF_AZ_TX_MAX_CPL_WIDTH 2
+#define FFE_AZ_TX_MAX_CPL_16 3
+#define FFE_AZ_TX_MAX_CPL_8 2
+#define FFE_AZ_TX_MAX_CPL_4 1
+#define FFE_AZ_TX_MAX_CPL_NOLIMIT 0
+#define FRF_AZ_TX_MAX_PREF_LBN 0
+#define FRF_AZ_TX_MAX_PREF_WIDTH 2
+#define FFE_AZ_TX_MAX_PREF_32 3
+#define FFE_AZ_TX_MAX_PREF_16 2
+#define FFE_AZ_TX_MAX_PREF_8 1
+#define FFE_AZ_TX_MAX_PREF_OFF 0
+
+
+/*------------------------------------------------------------*/
+/*
+ * FR_BZ_TX_PACE_REG(128bit):
+ * Transmit pace control register
+ */
+#define FR_BZ_TX_PACE_REG_OFST 0x00000a90
+/* falconb0,sienaa0=net_func_bar2 */
+/*
+ * FR_AA_TX_PACE_REG(128bit):
+ * Transmit pace control register
+ */
+#define FR_AA_TX_PACE_REG_OFST 0x00f80000
+/* falcona0=char_func_bar0 */
+
+#define FRF_AZ_TX_PACE_SB_NOT_AF_LBN 19
+#define FRF_AZ_TX_PACE_SB_NOT_AF_WIDTH 10
+#define FRF_AZ_TX_PACE_SB_AF_LBN 9
+#define FRF_AZ_TX_PACE_SB_AF_WIDTH 10
+#define FRF_AZ_TX_PACE_FB_BASE_LBN 5
+#define FRF_AZ_TX_PACE_FB_BASE_WIDTH 4
+#define FRF_AZ_TX_PACE_BIN_TH_LBN 0
+#define FRF_AZ_TX_PACE_BIN_TH_WIDTH 5
+
+
+/*------------------------------------------------------------*/
+/*
+ * FR_AZ_TX_PACE_DROP_QID_REG(128bit):
+ * PACE Drop QID Counter
+ */
+#define FR_AZ_TX_PACE_DROP_QID_REG_OFST 0x00000aa0
+/* falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */
+
+#define FRF_AZ_TX_PACE_QID_DRP_CNT_LBN 0
+#define FRF_AZ_TX_PACE_QID_DRP_CNT_WIDTH 16
+
+
+/*------------------------------------------------------------*/
+/*
+ * FR_AB_TX_VLAN_REG(128bit):
+ * Transmit VLAN tag register
+ */
+#define FR_AB_TX_VLAN_REG_OFST 0x00000ae0
+/* falconb0=net_func_bar2,falcona0=char_func_bar0 */
+
+#define FRF_AB_TX_VLAN_EN_LBN 127
+#define FRF_AB_TX_VLAN_EN_WIDTH 1
+#define FRF_AB_TX_VLAN7_PORT1_EN_LBN 125
+#define FRF_AB_TX_VLAN7_PORT1_EN_WIDTH 1
+#define FRF_AB_TX_VLAN7_PORT0_EN_LBN 124
+#define FRF_AB_TX_VLAN7_PORT0_EN_WIDTH 1
+#define FRF_AB_TX_VLAN7_LBN 112
+#define FRF_AB_TX_VLAN7_WIDTH 12
+#define FRF_AB_TX_VLAN6_PORT1_EN_LBN 109
+#define FRF_AB_TX_VLAN6_PORT1_EN_WIDTH 1
+#define FRF_AB_TX_VLAN6_PORT0_EN_LBN 108
+#define FRF_AB_TX_VLAN6_PORT0_EN_WIDTH 1
+#define FRF_AB_TX_VLAN6_LBN 96
+#define FRF_AB_TX_VLAN6_WIDTH 12
+#define FRF_AB_TX_VLAN5_PORT1_EN_LBN 93
+#define FRF_AB_TX_VLAN5_PORT1_EN_WIDTH 1
+#define FRF_AB_TX_VLAN5_PORT0_EN_LBN 92
+#define FRF_AB_TX_VLAN5_PORT0_EN_WIDTH 1
+#define FRF_AB_TX_VLAN5_LBN 80
+#define FRF_AB_TX_VLAN5_WIDTH 12
+#define FRF_AB_TX_VLAN4_PORT1_EN_LBN 77
+#define FRF_AB_TX_VLAN4_PORT1_EN_WIDTH 1
+#define FRF_AB_TX_VLAN4_PORT0_EN_LBN 76
+#define FRF_AB_TX_VLAN4_PORT0_EN_WIDTH 1
+#define FRF_AB_TX_VLAN4_LBN 64
+#define FRF_AB_TX_VLAN4_WIDTH 12
+#define FRF_AB_TX_VLAN3_PORT1_EN_LBN 61
+#define FRF_AB_TX_VLAN3_PORT1_EN_WIDTH 1
+#define FRF_AB_TX_VLAN3_PORT0_EN_LBN 60
+#define FRF_AB_TX_VLAN3_PORT0_EN_WIDTH 1
+#define FRF_AB_TX_VLAN3_LBN 48
+#define FRF_AB_TX_VLAN3_WIDTH 12
+#define FRF_AB_TX_VLAN2_PORT1_EN_LBN 45
+#define FRF_AB_TX_VLAN2_PORT1_EN_WIDTH 1
+#define FRF_AB_TX_VLAN2_PORT0_EN_LBN 44
+#define FRF_AB_TX_VLAN2_PORT0_EN_WIDTH 1
+#define FRF_AB_TX_VLAN2_LBN 32
+#define FRF_AB_TX_VLAN2_WIDTH 12
+#define FRF_AB_TX_VLAN1_PORT1_EN_LBN 29
+#define FRF_AB_TX_VLAN1_PORT1_EN_WIDTH 1
+#define FRF_AB_TX_VLAN1_PORT0_EN_LBN 28
+#define FRF_AB_TX_VLAN1_PORT0_EN_WIDTH 1
+#define FRF_AB_TX_VLAN1_LBN 16
+#define FRF_AB_TX_VLAN1_WIDTH 12
+#define FRF_AB_TX_VLAN0_PORT1_EN_LBN 13
+#define FRF_AB_TX_VLAN0_PORT1_EN_WIDTH 1
+#define FRF_AB_TX_VLAN0_PORT0_EN_LBN 12
+#define FRF_AB_TX_VLAN0_PORT0_EN_WIDTH 1
+#define FRF_AB_TX_VLAN0_LBN 0
+#define FRF_AB_TX_VLAN0_WIDTH 12
+
+
+/*------------------------------------------------------------*/
+/*
+ * FR_AZ_TX_IPFIL_PORTEN_REG(128bit):
+ * Transmit filter control register
+ */
+#define FR_AZ_TX_IPFIL_PORTEN_REG_OFST 0x00000af0
+/* falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */
+
+#define FRF_AZ_TX_MADR0_FIL_EN_LBN 64
+#define FRF_AZ_TX_MADR0_FIL_EN_WIDTH 1
+#define FRF_AB_TX_IPFIL31_PORT_EN_LBN 62
+#define FRF_AB_TX_IPFIL31_PORT_EN_WIDTH 1
+#define FRF_AB_TX_IPFIL30_PORT_EN_LBN 60
+#define FRF_AB_TX_IPFIL30_PORT_EN_WIDTH 1
+#define FRF_AB_TX_IPFIL29_PORT_EN_LBN 58
+#define FRF_AB_TX_IPFIL29_PORT_EN_WIDTH 1
+#define FRF_AB_TX_IPFIL28_PORT_EN_LBN 56
+#define FRF_AB_TX_IPFIL28_PORT_EN_WIDTH 1
+#define FRF_AB_TX_IPFIL27_PORT_EN_LBN 54
+#define FRF_AB_TX_IPFIL27_PORT_EN_WIDTH 1
+#define FRF_AB_TX_IPFIL26_PORT_EN_LBN 52
+#define FRF_AB_TX_IPFIL26_PORT_EN_WIDTH 1
+#define FRF_AB_TX_IPFIL25_PORT_EN_LBN 50
+#define FRF_AB_TX_IPFIL25_PORT_EN_WIDTH 1
+#define FRF_AB_TX_IPFIL24_PORT_EN_LBN 48
+#define FRF_AB_TX_IPFIL24_PORT_EN_WIDTH 1
+#define FRF_AB_TX_IPFIL23_PORT_EN_LBN 46
+#define FRF_AB_TX_IPFIL23_PORT_EN_WIDTH 1
+#define FRF_AB_TX_IPFIL22_PORT_EN_LBN 44
+#define FRF_AB_TX_IPFIL22_PORT_EN_WIDTH 1
+#define FRF_AB_TX_IPFIL21_PORT_EN_LBN 42
+#define FRF_AB_TX_IPFIL21_PORT_EN_WIDTH 1
+#define FRF_AB_TX_IPFIL20_PORT_EN_LBN 40
+#define FRF_AB_TX_IPFIL20_PORT_EN_WIDTH 1
+#define FRF_AB_TX_IPFIL19_PORT_EN_LBN 38
+#define FRF_AB_TX_IPFIL19_PORT_EN_WIDTH 1
+#define FRF_AB_TX_IPFIL18_PORT_EN_LBN 36
+#define FRF_AB_TX_IPFIL18_PORT_EN_WIDTH 1
+#define FRF_AB_TX_IPFIL17_PORT_EN_LBN 34
+#define FRF_AB_TX_IPFIL17_PORT_EN_WIDTH 1
+#define FRF_AB_TX_IPFIL16_PORT_EN_LBN 32
+#define FRF_AB_TX_IPFIL16_PORT_EN_WIDTH 1
+#define FRF_AB_TX_IPFIL15_PORT_EN_LBN 30
+#define FRF_AB_TX_IPFIL15_PORT_EN_WIDTH 1
+#define FRF_AB_TX_IPFIL14_PORT_EN_LBN 28
+#define FRF_AB_TX_IPFIL14_PORT_EN_WIDTH 1
+#define FRF_AB_TX_IPFIL13_PORT_EN_LBN 26
+#define FRF_AB_TX_IPFIL13_PORT_EN_WIDTH 1
+#define FRF_AB_TX_IPFIL12_PORT_EN_LBN 24
+#define FRF_AB_TX_IPFIL12_PORT_EN_WIDTH 1
+#define FRF_AB_TX_IPFIL11_PORT_EN_LBN 22
+#define FRF_AB_TX_IPFIL11_PORT_EN_WIDTH 1
+#define FRF_AB_TX_IPFIL10_PORT_EN_LBN 20
+#define FRF_AB_TX_IPFIL10_PORT_EN_WIDTH 1
+#define FRF_AB_TX_IPFIL9_PORT_EN_LBN 18
+#define FRF_AB_TX_IPFIL9_PORT_EN_WIDTH 1
+#define FRF_AB_TX_IPFIL8_PORT_EN_LBN 16
+#define FRF_AB_TX_IPFIL8_PORT_EN_WIDTH 1
+#define FRF_AB_TX_IPFIL7_PORT_EN_LBN 14
+#define FRF_AB_TX_IPFIL7_PORT_EN_WIDTH 1
+#define FRF_AB_TX_IPFIL6_PORT_EN_LBN 12
+#define FRF_AB_TX_IPFIL6_PORT_EN_WIDTH 1
+#define FRF_AB_TX_IPFIL5_PORT_EN_LBN 10
+#define FRF_AB_TX_IPFIL5_PORT_EN_WIDTH 1
+#define FRF_AB_TX_IPFIL4_PORT_EN_LBN 8
+#define FRF_AB_TX_IPFIL4_PORT_EN_WIDTH 1
+#define FRF_AB_TX_IPFIL3_PORT_EN_LBN 6
+#define FRF_AB_TX_IPFIL3_PORT_EN_WIDTH 1
+#define FRF_AB_TX_IPFIL2_PORT_EN_LBN 4
+#define FRF_AB_TX_IPFIL2_PORT_EN_WIDTH 1
+#define FRF_AB_TX_IPFIL1_PORT_EN_LBN 2
+#define FRF_AB_TX_IPFIL1_PORT_EN_WIDTH 1
+#define FRF_AB_TX_IPFIL0_PORT_EN_LBN 0
+#define FRF_AB_TX_IPFIL0_PORT_EN_WIDTH 1
+
+
+/*------------------------------------------------------------*/
+/*
+ * FR_AB_TX_IPFIL_TBL(128bit):
+ * Transmit IP source address filter table
+ */
+#define FR_AB_TX_IPFIL_TBL_OFST 0x00000b00
+/* falconb0=net_func_bar2,falcona0=char_func_bar0 */
+#define FR_AB_TX_IPFIL_TBL_STEP 16
+#define FR_AB_TX_IPFIL_TBL_ROWS 16
+
+#define FRF_AB_TX_IPFIL_MASK_1_LBN 96
+#define FRF_AB_TX_IPFIL_MASK_1_WIDTH 32
+#define FRF_AB_TX_IP_SRC_ADR_1_LBN 64
+#define FRF_AB_TX_IP_SRC_ADR_1_WIDTH 32
+#define FRF_AB_TX_IPFIL_MASK_0_LBN 32
+#define FRF_AB_TX_IPFIL_MASK_0_WIDTH 32
+#define FRF_AB_TX_IP_SRC_ADR_0_LBN 0
+#define FRF_AB_TX_IP_SRC_ADR_0_WIDTH 32
+
+
+/*------------------------------------------------------------*/
+/*
+ * FR_BB_TX_SRC_MAC_TBL(128bit):
+ * Transmit IP source address filter table
+ */
+#define FR_BB_TX_SRC_MAC_TBL_OFST 0x00001000
+/* falconb0=net_func_bar2 */
+#define FR_BB_TX_SRC_MAC_TBL_STEP 16
+#define FR_BB_TX_SRC_MAC_TBL_ROWS 16
+
+#define FRF_BB_TX_SRC_MAC_ADR_1_LBN 64
+#define FRF_BB_TX_SRC_MAC_ADR_1_WIDTH 48
+#define FRF_BB_TX_SRC_MAC_ADR_0_LBN 0
+#define FRF_BB_TX_SRC_MAC_ADR_0_WIDTH 48
+
+
+/*------------------------------------------------------------*/
+/*
+ * FR_BB_TX_SRC_MAC_CTL_REG(128bit):
+ * Transmit MAC source address filter control
+ */
+#define FR_BB_TX_SRC_MAC_CTL_REG_OFST 0x00001100
+/* falconb0=net_func_bar2 */
+
+#define FRF_BB_TX_SRC_DROP_CTR_LBN 16
+#define FRF_BB_TX_SRC_DROP_CTR_WIDTH 16
+#define FRF_BB_TX_SRC_FLTR_EN_LBN 15
+#define FRF_BB_TX_SRC_FLTR_EN_WIDTH 1
+#define FRF_BB_TX_DROP_CTR_CLR_LBN 12
+#define FRF_BB_TX_DROP_CTR_CLR_WIDTH 1
+#define FRF_BB_TX_MAC_QID_SEL_LBN 0
+#define FRF_BB_TX_MAC_QID_SEL_WIDTH 3
+
+
+/*------------------------------------------------------------*/
+/*
+ * FR_AA_RX_DESC_PTR_TBL_KER(128bit):
+ * Receive descriptor pointer table
+ */
+#define FR_AA_RX_DESC_PTR_TBL_KER_OFST 0x00011800
+/* falcona0=net_func_bar2 */
+#define FR_AA_RX_DESC_PTR_TBL_KER_STEP 16
+#define FR_AA_RX_DESC_PTR_TBL_KER_ROWS 4
+/*
+ * FR_AZ_RX_DESC_PTR_TBL(128bit):
+ * Receive descriptor pointer table
+ */
+#define FR_AZ_RX_DESC_PTR_TBL_OFST 0x00f40000
+/* falconb0=net_func_bar2,sienaa0=net_func_bar2,falcona0=char_func_bar0 */
+#define FR_AZ_RX_DESC_PTR_TBL_STEP 16
+#define FR_AB_RX_DESC_PTR_TBL_ROWS 4096
+#define FR_CZ_RX_DESC_PTR_TBL_ROWS 1024
+
+#define FRF_CZ_RX_HDR_SPLIT_LBN 90
+#define FRF_CZ_RX_HDR_SPLIT_WIDTH 1
+#define FRF_AA_RX_RESET_LBN 89
+#define FRF_AA_RX_RESET_WIDTH 1
+#define FRF_AZ_RX_ISCSI_DDIG_EN_LBN 88
+#define FRF_AZ_RX_ISCSI_DDIG_EN_WIDTH 1
+#define FRF_AZ_RX_ISCSI_HDIG_EN_LBN 87
+#define FRF_AZ_RX_ISCSI_HDIG_EN_WIDTH 1
+#define FRF_AZ_RX_DESC_PREF_ACT_LBN 86
+#define FRF_AZ_RX_DESC_PREF_ACT_WIDTH 1
+#define FRF_AZ_RX_DC_HW_RPTR_LBN 80
+#define FRF_AZ_RX_DC_HW_RPTR_WIDTH 6
+#define FRF_AZ_RX_DESCQ_HW_RPTR_LBN 68
+#define FRF_AZ_RX_DESCQ_HW_RPTR_WIDTH 12
+#define FRF_AZ_RX_DESCQ_SW_WPTR_LBN 56
+#define FRF_AZ_RX_DESCQ_SW_WPTR_WIDTH 12
+#define FRF_AZ_RX_DESCQ_BUF_BASE_ID_LBN 36
+#define FRF_AZ_RX_DESCQ_BUF_BASE_ID_WIDTH 20
+#define FRF_AZ_RX_DESCQ_EVQ_ID_LBN 24
+#define FRF_AZ_RX_DESCQ_EVQ_ID_WIDTH 12
+#define FRF_AZ_RX_DESCQ_OWNER_ID_LBN 10
+#define FRF_AZ_RX_DESCQ_OWNER_ID_WIDTH 14
+#define FRF_AZ_RX_DESCQ_LABEL_LBN 5
+#define FRF_AZ_RX_DESCQ_LABEL_WIDTH 5
+#define FRF_AZ_RX_DESCQ_SIZE_LBN 3
+#define FRF_AZ_RX_DESCQ_SIZE_WIDTH 2
+#define FFE_AZ_RX_DESCQ_SIZE_4K 3
+#define FFE_AZ_RX_DESCQ_SIZE_2K 2
+#define FFE_AZ_RX_DESCQ_SIZE_1K 1
+#define FFE_AZ_RX_DESCQ_SIZE_512 0
+#define FRF_AZ_RX_DESCQ_TYPE_LBN 2
+#define FRF_AZ_RX_DESCQ_TYPE_WIDTH 1
+#define FRF_AZ_RX_DESCQ_JUMBO_LBN 1
+#define FRF_AZ_RX_DESCQ_JUMBO_WIDTH 1
+#define FRF_AZ_RX_DESCQ_EN_LBN 0
+#define FRF_AZ_RX_DESCQ_EN_WIDTH 1
+
+
+/*------------------------------------------------------------*/
+/*
+ * FR_AA_TX_DESC_PTR_TBL_KER(128bit):
+ * Transmit descriptor pointer
+ */
+#define FR_AA_TX_DESC_PTR_TBL_KER_OFST 0x00011900
+/* falcona0=net_func_bar2 */
+#define FR_AA_TX_DESC_PTR_TBL_KER_STEP 16
+#define FR_AA_TX_DESC_PTR_TBL_KER_ROWS 8
+/*
+ * FR_AZ_TX_DESC_PTR_TBL(128bit):
+ * Transmit descriptor pointer
+ */
+#define FR_AZ_TX_DESC_PTR_TBL_OFST 0x00f50000
+/* falconb0=net_func_bar2,sienaa0=net_func_bar2,falcona0=char_func_bar0 */
+#define FR_AZ_TX_DESC_PTR_TBL_STEP 16
+#define FR_AB_TX_DESC_PTR_TBL_ROWS 4096
+#define FR_CZ_TX_DESC_PTR_TBL_ROWS 1024
+
+#define FRF_CZ_TX_DPT_Q_MASK_WIDTH_LBN 94
+#define FRF_CZ_TX_DPT_Q_MASK_WIDTH_WIDTH 2
+#define FRF_CZ_TX_DPT_ETH_FILT_EN_LBN 93
+#define FRF_CZ_TX_DPT_ETH_FILT_EN_WIDTH 1
+#define FRF_CZ_TX_DPT_IP_FILT_EN_LBN 92
+#define FRF_CZ_TX_DPT_IP_FILT_EN_WIDTH 1
+#define FRF_BZ_TX_NON_IP_DROP_DIS_LBN 91
+#define FRF_BZ_TX_NON_IP_DROP_DIS_WIDTH 1
+#define FRF_BZ_TX_IP_CHKSM_DIS_LBN 90
+#define FRF_BZ_TX_IP_CHKSM_DIS_WIDTH 1
+#define FRF_BZ_TX_TCP_CHKSM_DIS_LBN 89
+#define FRF_BZ_TX_TCP_CHKSM_DIS_WIDTH 1
+#define FRF_AZ_TX_DESCQ_EN_LBN 88
+#define FRF_AZ_TX_DESCQ_EN_WIDTH 1
+#define FRF_AZ_TX_ISCSI_DDIG_EN_LBN 87
+#define FRF_AZ_TX_ISCSI_DDIG_EN_WIDTH 1
+#define FRF_AZ_TX_ISCSI_HDIG_EN_LBN 86
+#define FRF_AZ_TX_ISCSI_HDIG_EN_WIDTH 1
+#define FRF_AZ_TX_DC_HW_RPTR_LBN 80
+#define FRF_AZ_TX_DC_HW_RPTR_WIDTH 6
+#define FRF_AZ_TX_DESCQ_HW_RPTR_LBN 68
+#define FRF_AZ_TX_DESCQ_HW_RPTR_WIDTH 12
+#define FRF_AZ_TX_DESCQ_SW_WPTR_LBN 56
+#define FRF_AZ_TX_DESCQ_SW_WPTR_WIDTH 12
+#define FRF_AZ_TX_DESCQ_BUF_BASE_ID_LBN 36
+#define FRF_AZ_TX_DESCQ_BUF_BASE_ID_WIDTH 20
+#define FRF_AZ_TX_DESCQ_EVQ_ID_LBN 24
+#define FRF_AZ_TX_DESCQ_EVQ_ID_WIDTH 12
+#define FRF_AZ_TX_DESCQ_OWNER_ID_LBN 10
+#define FRF_AZ_TX_DESCQ_OWNER_ID_WIDTH 14
+#define FRF_AZ_TX_DESCQ_LABEL_LBN 5
+#define FRF_AZ_TX_DESCQ_LABEL_WIDTH 5
+#define FRF_AZ_TX_DESCQ_SIZE_LBN 3
+#define FRF_AZ_TX_DESCQ_SIZE_WIDTH 2
+#define FFE_AZ_TX_DESCQ_SIZE_4K 3
+#define FFE_AZ_TX_DESCQ_SIZE_2K 2
+#define FFE_AZ_TX_DESCQ_SIZE_1K 1
+#define FFE_AZ_TX_DESCQ_SIZE_512 0
+#define FRF_AZ_TX_DESCQ_TYPE_LBN 1
+#define FRF_AZ_TX_DESCQ_TYPE_WIDTH 2
+#define FRF_AZ_TX_DESCQ_FLUSH_LBN 0
+#define FRF_AZ_TX_DESCQ_FLUSH_WIDTH 1
+
+
+/*------------------------------------------------------------*/
+/*
+ * FR_AA_EVQ_PTR_TBL_KER(128bit):
+ * Event queue pointer table
+ */
+#define FR_AA_EVQ_PTR_TBL_KER_OFST 0x00011a00
+/* falcona0=net_func_bar2 */
+#define FR_AA_EVQ_PTR_TBL_KER_STEP 16
+#define FR_AA_EVQ_PTR_TBL_KER_ROWS 4
+/*
+ * FR_AZ_EVQ_PTR_TBL(128bit):
+ * Event queue pointer table
+ */
+#define FR_AZ_EVQ_PTR_TBL_OFST 0x00f60000
+/* sienaa0=net_func_bar2,falconb0=net_func_bar2,falcona0=char_func_bar0 */
+#define FR_AZ_EVQ_PTR_TBL_STEP 16
+#define FR_CZ_EVQ_PTR_TBL_ROWS 1024
+#define FR_AB_EVQ_PTR_TBL_ROWS 4096
+
+#define FRF_BZ_EVQ_RPTR_IGN_LBN 40
+#define FRF_BZ_EVQ_RPTR_IGN_WIDTH 1
+#define FRF_AB_EVQ_WKUP_OR_INT_EN_LBN 39
+#define FRF_AB_EVQ_WKUP_OR_INT_EN_WIDTH 1
+#define FRF_CZ_EVQ_DOS_PROTECT_EN_LBN 39
+#define FRF_CZ_EVQ_DOS_PROTECT_EN_WIDTH 1
+#define FRF_AZ_EVQ_NXT_WPTR_LBN 24
+#define FRF_AZ_EVQ_NXT_WPTR_WIDTH 15
+#define FRF_AZ_EVQ_EN_LBN 23
+#define FRF_AZ_EVQ_EN_WIDTH 1
+#define FRF_AZ_EVQ_SIZE_LBN 20
+#define FRF_AZ_EVQ_SIZE_WIDTH 3
+#define FFE_AZ_EVQ_SIZE_32K 6
+#define FFE_AZ_EVQ_SIZE_16K 5
+#define FFE_AZ_EVQ_SIZE_8K 4
+#define FFE_AZ_EVQ_SIZE_4K 3
+#define FFE_AZ_EVQ_SIZE_2K 2
+#define FFE_AZ_EVQ_SIZE_1K 1
+#define FFE_AZ_EVQ_SIZE_512 0
+#define FRF_AZ_EVQ_BUF_BASE_ID_LBN 0
+#define FRF_AZ_EVQ_BUF_BASE_ID_WIDTH 20
+
+
+/*------------------------------------------------------------*/
+/*
+ * FR_AA_BUF_HALF_TBL_KER(64bit):
+ * Buffer table in half buffer table mode direct access by driver
+ */
+#define FR_AA_BUF_HALF_TBL_KER_OFST 0x00018000
+/* falcona0=net_func_bar2 */
+#define FR_AA_BUF_HALF_TBL_KER_STEP 8
+#define FR_AA_BUF_HALF_TBL_KER_ROWS 4096
+/*
+ * FR_AZ_BUF_HALF_TBL(64bit):
+ * Buffer table in half buffer table mode direct access by driver
+ */
+#define FR_AZ_BUF_HALF_TBL_OFST 0x00800000
+/* sienaa0=net_func_bar2,falconb0=net_func_bar2,falcona0=char_func_bar0 */
+#define FR_AZ_BUF_HALF_TBL_STEP 8
+#define FR_CZ_BUF_HALF_TBL_ROWS 147456
+#define FR_AB_BUF_HALF_TBL_ROWS 524288
+
+#define FRF_AZ_BUF_ADR_HBUF_ODD_LBN 44
+#define FRF_AZ_BUF_ADR_HBUF_ODD_WIDTH 20
+#define FRF_AZ_BUF_OWNER_ID_HBUF_ODD_LBN 32
+#define FRF_AZ_BUF_OWNER_ID_HBUF_ODD_WIDTH 12
+#define FRF_AZ_BUF_ADR_HBUF_EVEN_LBN 12
+#define FRF_AZ_BUF_ADR_HBUF_EVEN_WIDTH 20
+#define FRF_AZ_BUF_OWNER_ID_HBUF_EVEN_LBN 0
+#define FRF_AZ_BUF_OWNER_ID_HBUF_EVEN_WIDTH 12
+
+
+/*------------------------------------------------------------*/
+/*
+ * FR_AA_BUF_FULL_TBL_KER(64bit):
+ * Buffer table in full buffer table mode direct access by driver
+ */
+#define FR_AA_BUF_FULL_TBL_KER_OFST 0x00018000
+/* falcona0=net_func_bar2 */
+#define FR_AA_BUF_FULL_TBL_KER_STEP 8
+#define FR_AA_BUF_FULL_TBL_KER_ROWS 4096
+/*
+ * FR_AZ_BUF_FULL_TBL(64bit):
+ * Buffer table in full buffer table mode direct access by driver
+ */
+#define FR_AZ_BUF_FULL_TBL_OFST 0x00800000
+/* sienaa0=net_func_bar2,falconb0=net_func_bar2,falcona0=char_func_bar0 */
+#define FR_AZ_BUF_FULL_TBL_STEP 8
+#define FR_CZ_BUF_FULL_TBL_ROWS 147456
+#define FR_AB_BUF_FULL_TBL_ROWS 917504
+
+#define FRF_AZ_BUF_FULL_UNUSED_LBN 51
+#define FRF_AZ_BUF_FULL_UNUSED_WIDTH 13
+#define FRF_AZ_IP_DAT_BUF_SIZE_LBN 50
+#define FRF_AZ_IP_DAT_BUF_SIZE_WIDTH 1
+#define FRF_AZ_BUF_ADR_REGION_LBN 48
+#define FRF_AZ_BUF_ADR_REGION_WIDTH 2
+#define FFE_AZ_BUF_ADR_REGN3 3
+#define FFE_AZ_BUF_ADR_REGN2 2
+#define FFE_AZ_BUF_ADR_REGN1 1
+#define FFE_AZ_BUF_ADR_REGN0 0
+#define FRF_AZ_BUF_ADR_FBUF_LBN 14
+#define FRF_AZ_BUF_ADR_FBUF_WIDTH 34
+#define FRF_AZ_BUF_OWNER_ID_FBUF_LBN 0
+#define FRF_AZ_BUF_OWNER_ID_FBUF_WIDTH 14
+
+
+/*------------------------------------------------------------*/
+/*
+ * FR_AZ_RX_FILTER_TBL0(128bit):
+ * TCP/IPv4 Receive filter table
+ */
+#define FR_AZ_RX_FILTER_TBL0_OFST 0x00f00000
+/* falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */
+#define FR_AZ_RX_FILTER_TBL0_STEP 32
+#define FR_AZ_RX_FILTER_TBL0_ROWS 8192
+/*
+ * FR_AB_RX_FILTER_TBL1(128bit):
+ * TCP/IPv4 Receive filter table
+ */
+#define FR_AB_RX_FILTER_TBL1_OFST 0x00f00010
+/* falconb0=net_func_bar2,falcona0=char_func_bar0 */
+#define FR_AB_RX_FILTER_TBL1_STEP 32
+#define FR_AB_RX_FILTER_TBL1_ROWS 8192
+
+#define FRF_BZ_RSS_EN_LBN 110
+#define FRF_BZ_RSS_EN_WIDTH 1
+#define FRF_BZ_SCATTER_EN_LBN 109
+#define FRF_BZ_SCATTER_EN_WIDTH 1
+#define FRF_AZ_TCP_UDP_LBN 108
+#define FRF_AZ_TCP_UDP_WIDTH 1
+#define FRF_AZ_RXQ_ID_LBN 96
+#define FRF_AZ_RXQ_ID_WIDTH 12
+#define FRF_AZ_DEST_IP_LBN 64
+#define FRF_AZ_DEST_IP_WIDTH 32
+#define FRF_AZ_DEST_PORT_TCP_LBN 48
+#define FRF_AZ_DEST_PORT_TCP_WIDTH 16
+#define FRF_AZ_SRC_IP_LBN 16
+#define FRF_AZ_SRC_IP_WIDTH 32
+#define FRF_AZ_SRC_TCP_DEST_UDP_LBN 0
+#define FRF_AZ_SRC_TCP_DEST_UDP_WIDTH 16
+
+
+/*------------------------------------------------------------*/
+/*
+ * FR_CZ_RX_MAC_FILTER_TBL0(128bit):
+ * Receive Ethernet filter table
+ */
+#define FR_CZ_RX_MAC_FILTER_TBL0_OFST 0x00f00010
+/* sienaa0=net_func_bar2 */
+#define FR_CZ_RX_MAC_FILTER_TBL0_STEP 32
+#define FR_CZ_RX_MAC_FILTER_TBL0_ROWS 512
+
+#define FRF_CZ_RMFT_RSS_EN_LBN 75
+#define FRF_CZ_RMFT_RSS_EN_WIDTH 1
+#define FRF_CZ_RMFT_SCATTER_EN_LBN 74
+#define FRF_CZ_RMFT_SCATTER_EN_WIDTH 1
+#define FRF_CZ_RMFT_IP_OVERRIDE_LBN 73
+#define FRF_CZ_RMFT_IP_OVERRIDE_WIDTH 1
+#define FRF_CZ_RMFT_RXQ_ID_LBN 61
+#define FRF_CZ_RMFT_RXQ_ID_WIDTH 12
+#define FRF_CZ_RMFT_WILDCARD_MATCH_LBN 60
+#define FRF_CZ_RMFT_WILDCARD_MATCH_WIDTH 1
+#define FRF_CZ_RMFT_DEST_MAC_LBN 16
+#define FRF_CZ_RMFT_DEST_MAC_WIDTH 44
+#define FRF_CZ_RMFT_VLAN_ID_LBN 0
+#define FRF_CZ_RMFT_VLAN_ID_WIDTH 12
+
+
+/*------------------------------------------------------------*/
+/*
+ * FR_AZ_TIMER_TBL(128bit):
+ * Timer table
+ */
+#define FR_AZ_TIMER_TBL_OFST 0x00f70000
+/* sienaa0=net_func_bar2,falconb0=net_func_bar2,falcona0=char_func_bar0 */
+#define FR_AZ_TIMER_TBL_STEP 16
+#define FR_CZ_TIMER_TBL_ROWS 1024
+#define FR_AB_TIMER_TBL_ROWS 4096
+
+#define FRF_CZ_TIMER_Q_EN_LBN 33
+#define FRF_CZ_TIMER_Q_EN_WIDTH 1
+#define FRF_CZ_INT_ARMD_LBN 32
+#define FRF_CZ_INT_ARMD_WIDTH 1
+#define FRF_CZ_INT_PEND_LBN 31
+#define FRF_CZ_INT_PEND_WIDTH 1
+#define FRF_CZ_HOST_NOTIFY_MODE_LBN 30
+#define FRF_CZ_HOST_NOTIFY_MODE_WIDTH 1
+#define FRF_CZ_RELOAD_TIMER_VAL_LBN 16
+#define FRF_CZ_RELOAD_TIMER_VAL_WIDTH 14
+#define FRF_CZ_TIMER_MODE_LBN 14
+#define FRF_CZ_TIMER_MODE_WIDTH 2
+#define FFE_CZ_TIMER_MODE_INT_HLDOFF 3
+#define FFE_CZ_TIMER_MODE_TRIG_START 2
+#define FFE_CZ_TIMER_MODE_IMMED_START 1
+#define FFE_CZ_TIMER_MODE_DIS 0
+#define FRF_AB_TIMER_MODE_LBN 12
+#define FRF_AB_TIMER_MODE_WIDTH 2
+#define FFE_AB_TIMER_MODE_INT_HLDOFF 2
+#define FFE_AB_TIMER_MODE_TRIG_START 2
+#define FFE_AB_TIMER_MODE_IMMED_START 1
+#define FFE_AB_TIMER_MODE_DIS 0
+#define FRF_CZ_TIMER_VAL_LBN 0
+#define FRF_CZ_TIMER_VAL_WIDTH 14
+#define FRF_AB_TIMER_VAL_LBN 0
+#define FRF_AB_TIMER_VAL_WIDTH 12
+
+
+/*------------------------------------------------------------*/
+/*
+ * FR_BZ_TX_PACE_TBL(128bit):
+ * Transmit pacing table
+ */
+#define FR_BZ_TX_PACE_TBL_OFST 0x00f80000
+/* sienaa0=net_func_bar2,falconb0=net_func_bar2 */
+#define FR_AZ_TX_PACE_TBL_STEP 16
+#define FR_CZ_TX_PACE_TBL_ROWS 1024
+#define FR_BB_TX_PACE_TBL_ROWS 4096
+/*
+ * FR_AA_TX_PACE_TBL(128bit):
+ * Transmit pacing table
+ */
+#define FR_AA_TX_PACE_TBL_OFST 0x00f80040
+/* falcona0=char_func_bar0 */
+/* FR_AZ_TX_PACE_TBL_STEP 16 */
+#define FR_AA_TX_PACE_TBL_ROWS 4092
+
+#define FRF_AZ_TX_PACE_LBN 0
+#define FRF_AZ_TX_PACE_WIDTH 5
+
+
+/*------------------------------------------------------------*/
+/*
+ * FR_BZ_RX_INDIRECTION_TBL(7bit):
+ * RX Indirection Table
+ */
+#define FR_BZ_RX_INDIRECTION_TBL_OFST 0x00fb0000
+/* falconb0,sienaa0=net_func_bar2 */
+#define FR_BZ_RX_INDIRECTION_TBL_STEP 16
+#define FR_BZ_RX_INDIRECTION_TBL_ROWS 128
+
+#define FRF_BZ_IT_QUEUE_LBN 0
+#define FRF_BZ_IT_QUEUE_WIDTH 6
+
+
+/*------------------------------------------------------------*/
+/*
+ * FR_CZ_TX_FILTER_TBL0(128bit):
+ * TCP/IPv4 Transmit filter table
+ */
+#define FR_CZ_TX_FILTER_TBL0_OFST 0x00fc0000
+/* sienaa0=net_func_bar2 */
+#define FR_CZ_TX_FILTER_TBL0_STEP 16
+#define FR_CZ_TX_FILTER_TBL0_ROWS 8192
+
+#define FRF_CZ_TIFT_TCP_UDP_LBN 108
+#define FRF_CZ_TIFT_TCP_UDP_WIDTH 1
+#define FRF_CZ_TIFT_TXQ_ID_LBN 96
+#define FRF_CZ_TIFT_TXQ_ID_WIDTH 12
+#define FRF_CZ_TIFT_DEST_IP_LBN 64
+#define FRF_CZ_TIFT_DEST_IP_WIDTH 32
+#define FRF_CZ_TIFT_DEST_PORT_TCP_LBN 48
+#define FRF_CZ_TIFT_DEST_PORT_TCP_WIDTH 16
+#define FRF_CZ_TIFT_SRC_IP_LBN 16
+#define FRF_CZ_TIFT_SRC_IP_WIDTH 32
+#define FRF_CZ_TIFT_SRC_TCP_DEST_UDP_LBN 0
+#define FRF_CZ_TIFT_SRC_TCP_DEST_UDP_WIDTH 16
+
+
+/*------------------------------------------------------------*/
+/*
+ * FR_CZ_TX_MAC_FILTER_TBL0(128bit):
+ * Transmit Ethernet filter table
+ */
+#define FR_CZ_TX_MAC_FILTER_TBL0_OFST 0x00fe0000
+/* sienaa0=net_func_bar2 */
+#define FR_CZ_TX_MAC_FILTER_TBL0_STEP 16
+#define FR_CZ_TX_MAC_FILTER_TBL0_ROWS 512
+
+#define FRF_CZ_TMFT_TXQ_ID_LBN 61
+#define FRF_CZ_TMFT_TXQ_ID_WIDTH 12
+#define FRF_CZ_TMFT_WILDCARD_MATCH_LBN 60
+#define FRF_CZ_TMFT_WILDCARD_MATCH_WIDTH 1
+#define FRF_CZ_TMFT_SRC_MAC_LBN 16
+#define FRF_CZ_TMFT_SRC_MAC_WIDTH 44
+#define FRF_CZ_TMFT_VLAN_ID_LBN 0
+#define FRF_CZ_TMFT_VLAN_ID_WIDTH 12
+
+
+/*------------------------------------------------------------*/
+/*
+ * FR_CZ_MC_TREG_SMEM(32bit):
+ * MC Shared Memory
+ */
+#define FR_CZ_MC_TREG_SMEM_OFST 0x00ff0000
+/* sienaa0=net_func_bar2 */
+#define FR_CZ_MC_TREG_SMEM_STEP 4
+#define FR_CZ_MC_TREG_SMEM_ROWS 512
+
+#define FRF_CZ_MC_TREG_SMEM_ROW_LBN 0
+#define FRF_CZ_MC_TREG_SMEM_ROW_WIDTH 32
+
+
+/*------------------------------------------------------------*/
+/*
+ * FR_BB_MSIX_VECTOR_TABLE(128bit):
+ * MSIX Vector Table
+ */
+#define FR_BB_MSIX_VECTOR_TABLE_OFST 0x00ff0000
+/* falconb0=net_func_bar2 */
+#define FR_BZ_MSIX_VECTOR_TABLE_STEP 16
+#define FR_BB_MSIX_VECTOR_TABLE_ROWS 64
+/*
+ * FR_CZ_MSIX_VECTOR_TABLE(128bit):
+ * MSIX Vector Table
+ */
+#define FR_CZ_MSIX_VECTOR_TABLE_OFST 0x00000000
+/* sienaa0=pci_f0_bar4 */
+/* FR_BZ_MSIX_VECTOR_TABLE_STEP 16 */
+#define FR_CZ_MSIX_VECTOR_TABLE_ROWS 1024
+
+#define FRF_BZ_MSIX_VECTOR_RESERVED_LBN 97
+#define FRF_BZ_MSIX_VECTOR_RESERVED_WIDTH 31
+#define FRF_BZ_MSIX_VECTOR_MASK_LBN 96
+#define FRF_BZ_MSIX_VECTOR_MASK_WIDTH 1
+#define FRF_BZ_MSIX_MESSAGE_DATA_LBN 64
+#define FRF_BZ_MSIX_MESSAGE_DATA_WIDTH 32
+#define FRF_BZ_MSIX_MESSAGE_ADDRESS_HI_LBN 32
+#define FRF_BZ_MSIX_MESSAGE_ADDRESS_HI_WIDTH 32
+#define FRF_BZ_MSIX_MESSAGE_ADDRESS_LO_LBN 0
+#define FRF_BZ_MSIX_MESSAGE_ADDRESS_LO_WIDTH 32
+
+
+/*------------------------------------------------------------*/
+/*
+ * FR_BB_MSIX_PBA_TABLE(32bit):
+ * MSIX Pending Bit Array
+ */
+#define FR_BB_MSIX_PBA_TABLE_OFST 0x00ff2000
+/* falconb0=net_func_bar2 */
+#define FR_BZ_MSIX_PBA_TABLE_STEP 4
+#define FR_BB_MSIX_PBA_TABLE_ROWS 2
+/*
+ * FR_CZ_MSIX_PBA_TABLE(32bit):
+ * MSIX Pending Bit Array
+ */
+#define FR_CZ_MSIX_PBA_TABLE_OFST 0x00008000
+/* sienaa0=pci_f0_bar4 */
+/* FR_BZ_MSIX_PBA_TABLE_STEP 4 */
+#define FR_CZ_MSIX_PBA_TABLE_ROWS 32
+
+#define FRF_BZ_MSIX_PBA_PEND_DWORD_LBN 0
+#define FRF_BZ_MSIX_PBA_PEND_DWORD_WIDTH 32
+
+
+/*------------------------------------------------------------*/
+/*
+ * FR_AZ_SRM_DBG_REG(64bit):
+ * SRAM debug access
+ */
+#define FR_AZ_SRM_DBG_REG_OFST 0x03000000
+/* sienaa0=net_func_bar2,falconb0=net_func_bar2,falcona0=char_func_bar0 */
+#define FR_AZ_SRM_DBG_REG_STEP 8
+#define FR_CZ_SRM_DBG_REG_ROWS 262144
+#define FR_AB_SRM_DBG_REG_ROWS 2097152
+
+#define FRF_AZ_SRM_DBG_LBN 0
+#define FRF_AZ_SRM_DBG_WIDTH 64
+
+
+/*------------------------------------------------------------*/
+/*
+ * FR_CZ_TB_MSIX_PBA_TABLE(1bit):
+ * MSIX Pending Bit Array
+ */
+#define FR_CZ_TB_MSIX_PBA_TABLE_OFST 0x00008000
+/* sienaa0=pci_f0_bar4 */
+#define FR_CZ_TB_MSIX_PBA_TABLE_STEP 4
+#define FR_CZ_TB_MSIX_PBA_TABLE_ROWS 1024
+
+#define FRF_CZ_TB_MSIX_PBA_PEND_DWORD_LBN 0
+#define FRF_CZ_TB_MSIX_PBA_PEND_DWORD_WIDTH 32
+
+
+/*------------------------------------------------------------*/
+/*
+ * FR_AA_INT_ACK_CHAR(32bit):
+ * CHAR interrupt acknowledge register
+ */
+#define FR_AA_INT_ACK_CHAR_OFST 0x00000060
+/* falcona0=char_func_bar0 */
+
+#define FRF_AA_INT_ACK_CHAR_FIELD_LBN 0
+#define FRF_AA_INT_ACK_CHAR_FIELD_WIDTH 32
+
+
+/*------------------------------------------------------------*/
+/* FS_DRIVER_EV */
+#define FSF_AZ_DRIVER_EV_SUBCODE_LBN 56
+#define FSF_AZ_DRIVER_EV_SUBCODE_WIDTH 4
+#define FSE_BZ_TX_DSC_ERROR_EV 15
+#define FSE_BZ_RX_DSC_ERROR_EV 14
+#define FSE_AA_RX_RECOVER_EV 11
+#define FSE_AZ_TIMER_EV 10
+#define FSE_AZ_TX_PKT_NON_TCP_UDP 9
+#define FSE_AZ_WAKE_UP_EV 6
+#define FSE_AZ_SRM_UPD_DONE_EV 5
+#define FSE_AB_EVQ_NOT_EN_EV 3
+#define FSE_AZ_EVQ_INIT_DONE_EV 2
+#define FSE_AZ_RX_DESCQ_FLS_DONE_EV 1
+#define FSE_AZ_TX_DESCQ_FLS_DONE_EV 0
+#define FSF_AZ_DRIVER_EV_SUBDATA_LBN 0
+#define FSF_AZ_DRIVER_EV_SUBDATA_WIDTH 14
+
+
+/*------------------------------------------------------------*/
+/* FS_EVENT_ENTRY */
+#define FSF_AZ_EV_CODE_LBN 60
+#define FSF_AZ_EV_CODE_WIDTH 4
+#define FSE_CZ_EV_CODE_MCDI_EV 12
+#define FSE_CZ_EV_CODE_USER_EV 8
+#define FSE_AZ_EV_CODE_DRV_GEN_EV 7
+#define FSE_AZ_EV_CODE_GLOBAL_EV 6
+#define FSE_AZ_EV_CODE_DRIVER_EV 5
+#define FSE_AZ_EV_CODE_TX_EV 2
+#define FSE_AZ_EV_CODE_RX_EV 0
+#define FSF_AZ_EV_DATA_LBN 0
+#define FSF_AZ_EV_DATA_WIDTH 60
+
+
+/*------------------------------------------------------------*/
+/* FS_GLOBAL_EV */
+#define FSF_BB_GLB_EV_RX_RECOVERY_LBN 12
+#define FSF_BB_GLB_EV_RX_RECOVERY_WIDTH 1
+#define FSF_AA_GLB_EV_RX_RECOVERY_LBN 11
+#define FSF_AA_GLB_EV_RX_RECOVERY_WIDTH 1
+#define FSF_BB_GLB_EV_XG_MGT_INTR_LBN 11
+#define FSF_BB_GLB_EV_XG_MGT_INTR_WIDTH 1
+#define FSF_AB_GLB_EV_XFP_PHY0_INTR_LBN 10
+#define FSF_AB_GLB_EV_XFP_PHY0_INTR_WIDTH 1
+#define FSF_AB_GLB_EV_XG_PHY0_INTR_LBN 9
+#define FSF_AB_GLB_EV_XG_PHY0_INTR_WIDTH 1
+#define FSF_AB_GLB_EV_G_PHY0_INTR_LBN 7
+#define FSF_AB_GLB_EV_G_PHY0_INTR_WIDTH 1
+
+
+/*------------------------------------------------------------*/
+/* FS_LEGACY_INT_VEC */
+#define FSF_AZ_NET_IVEC_FATAL_INT_LBN 64
+#define FSF_AZ_NET_IVEC_FATAL_INT_WIDTH 1
+#define FSF_AZ_NET_IVEC_INT_Q_LBN 40
+#define FSF_AZ_NET_IVEC_INT_Q_WIDTH 4
+#define FSF_AZ_NET_IVEC_INT_FLAG_LBN 32
+#define FSF_AZ_NET_IVEC_INT_FLAG_WIDTH 1
+#define FSF_AZ_NET_IVEC_EVQ_FIFO_HF_LBN 1
+#define FSF_AZ_NET_IVEC_EVQ_FIFO_HF_WIDTH 1
+#define FSF_AZ_NET_IVEC_EVQ_FIFO_AF_LBN 0
+#define FSF_AZ_NET_IVEC_EVQ_FIFO_AF_WIDTH 1
+
+
+/*------------------------------------------------------------*/
+/* FS_MC_XGMAC_FLTR_RULE_DEF */
+#define FSF_CZ_MC_XFRC_MODE_LBN 416
+#define FSF_CZ_MC_XFRC_MODE_WIDTH 1
+#define FSE_CZ_MC_XFRC_MODE_LAYERED 1
+#define FSE_CZ_MC_XFRC_MODE_SIMPLE 0
+#define FSF_CZ_MC_XFRC_HASH_LBN 384
+#define FSF_CZ_MC_XFRC_HASH_WIDTH 32
+#define FSF_CZ_MC_XFRC_LAYER4_BYTE_MASK_LBN 256
+#define FSF_CZ_MC_XFRC_LAYER4_BYTE_MASK_WIDTH 128
+#define FSF_CZ_MC_XFRC_LAYER3_BYTE_MASK_LBN 128
+#define FSF_CZ_MC_XFRC_LAYER3_BYTE_MASK_WIDTH 128
+#define FSF_CZ_MC_XFRC_LAYER2_OR_SIMPLE_BYTE_MASK_LBN 0
+#define FSF_CZ_MC_XFRC_LAYER2_OR_SIMPLE_BYTE_MASK_WIDTH 128
+
+
+/*------------------------------------------------------------*/
+/* FS_RX_EV */
+#define FSF_CZ_RX_EV_PKT_NOT_PARSED_LBN 58
+#define FSF_CZ_RX_EV_PKT_NOT_PARSED_WIDTH 1
+#define FSF_CZ_RX_EV_IPV6_PKT_LBN 57
+#define FSF_CZ_RX_EV_IPV6_PKT_WIDTH 1
+#define FSF_AZ_RX_EV_PKT_OK_LBN 56
+#define FSF_AZ_RX_EV_PKT_OK_WIDTH 1
+#define FSF_AZ_RX_EV_PAUSE_FRM_ERR_LBN 55
+#define FSF_AZ_RX_EV_PAUSE_FRM_ERR_WIDTH 1
+#define FSF_AZ_RX_EV_BUF_OWNER_ID_ERR_LBN 54
+#define FSF_AZ_RX_EV_BUF_OWNER_ID_ERR_WIDTH 1
+#define FSF_AZ_RX_EV_IP_FRAG_ERR_LBN 53
+#define FSF_AZ_RX_EV_IP_FRAG_ERR_WIDTH 1
+#define FSF_AZ_RX_EV_IP_HDR_CHKSUM_ERR_LBN 52
+#define FSF_AZ_RX_EV_IP_HDR_CHKSUM_ERR_WIDTH 1
+#define FSF_AZ_RX_EV_TCP_UDP_CHKSUM_ERR_LBN 51
+#define FSF_AZ_RX_EV_TCP_UDP_CHKSUM_ERR_WIDTH 1
+#define FSF_AZ_RX_EV_ETH_CRC_ERR_LBN 50
+#define FSF_AZ_RX_EV_ETH_CRC_ERR_WIDTH 1
+#define FSF_AZ_RX_EV_FRM_TRUNC_LBN 49
+#define FSF_AZ_RX_EV_FRM_TRUNC_WIDTH 1
+#define FSF_AA_RX_EV_DRIB_NIB_LBN 49
+#define FSF_AA_RX_EV_DRIB_NIB_WIDTH 1
+#define FSF_AZ_RX_EV_TOBE_DISC_LBN 47
+#define FSF_AZ_RX_EV_TOBE_DISC_WIDTH 1
+#define FSF_AZ_RX_EV_PKT_TYPE_LBN 44
+#define FSF_AZ_RX_EV_PKT_TYPE_WIDTH 3
+#define FSE_AZ_RX_EV_PKT_TYPE_VLAN_JUMBO 5
+#define FSE_AZ_RX_EV_PKT_TYPE_VLAN_LLC 4
+#define FSE_AZ_RX_EV_PKT_TYPE_VLAN 3
+#define FSE_AZ_RX_EV_PKT_TYPE_JUMBO 2
+#define FSE_AZ_RX_EV_PKT_TYPE_LLC 1
+#define FSE_AZ_RX_EV_PKT_TYPE_ETH 0
+#define FSF_AZ_RX_EV_HDR_TYPE_LBN 42
+#define FSF_AZ_RX_EV_HDR_TYPE_WIDTH 2
+#define FSE_AZ_RX_EV_HDR_TYPE_OTHER 3
+#define FSE_AB_RX_EV_HDR_TYPE_IPV4_OTHER 2
+#define FSE_CZ_RX_EV_HDR_TYPE_IPV4V6_OTHER 2
+#define FSE_AB_RX_EV_HDR_TYPE_IPV4_UDP 1
+#define FSE_CZ_RX_EV_HDR_TYPE_IPV4V6_UDP 1
+#define FSE_AB_RX_EV_HDR_TYPE_IPV4_TCP 0
+#define FSE_CZ_RX_EV_HDR_TYPE_IPV4V6_TCP 0
+#define FSF_AZ_RX_EV_DESC_Q_EMPTY_LBN 41
+#define FSF_AZ_RX_EV_DESC_Q_EMPTY_WIDTH 1
+#define FSF_AZ_RX_EV_MCAST_HASH_MATCH_LBN 40
+#define FSF_AZ_RX_EV_MCAST_HASH_MATCH_WIDTH 1
+#define FSF_AZ_RX_EV_MCAST_PKT_LBN 39
+#define FSF_AZ_RX_EV_MCAST_PKT_WIDTH 1
+#define FSF_AA_RX_EV_RECOVERY_FLAG_LBN 37
+#define FSF_AA_RX_EV_RECOVERY_FLAG_WIDTH 1
+#define FSF_AZ_RX_EV_Q_LABEL_LBN 32
+#define FSF_AZ_RX_EV_Q_LABEL_WIDTH 5
+#define FSF_AZ_RX_EV_JUMBO_CONT_LBN 31
+#define FSF_AZ_RX_EV_JUMBO_CONT_WIDTH 1
+#define FSF_AZ_RX_EV_PORT_LBN 30
+#define FSF_AZ_RX_EV_PORT_WIDTH 1
+#define FSF_AZ_RX_EV_BYTE_CNT_LBN 16
+#define FSF_AZ_RX_EV_BYTE_CNT_WIDTH 14
+#define FSF_AZ_RX_EV_SOP_LBN 15
+#define FSF_AZ_RX_EV_SOP_WIDTH 1
+#define FSF_AZ_RX_EV_ISCSI_PKT_OK_LBN 14
+#define FSF_AZ_RX_EV_ISCSI_PKT_OK_WIDTH 1
+#define FSF_AZ_RX_EV_ISCSI_DDIG_ERR_LBN 13
+#define FSF_AZ_RX_EV_ISCSI_DDIG_ERR_WIDTH 1
+#define FSF_AZ_RX_EV_ISCSI_HDIG_ERR_LBN 12
+#define FSF_AZ_RX_EV_ISCSI_HDIG_ERR_WIDTH 1
+#define FSF_AZ_RX_EV_DESC_PTR_LBN 0
+#define FSF_AZ_RX_EV_DESC_PTR_WIDTH 12
+
+
+/*------------------------------------------------------------*/
+/* FS_RX_KER_DESC */
+#define FSF_AZ_RX_KER_BUF_SIZE_LBN 48
+#define FSF_AZ_RX_KER_BUF_SIZE_WIDTH 14
+#define FSF_AZ_RX_KER_BUF_REGION_LBN 46
+#define FSF_AZ_RX_KER_BUF_REGION_WIDTH 2
+#define FSF_AZ_RX_KER_BUF_ADDR_LBN 0
+#define FSF_AZ_RX_KER_BUF_ADDR_WIDTH 46
+
+
+/*------------------------------------------------------------*/
+/* FS_RX_USER_DESC */
+#define FSF_AZ_RX_USER_2BYTE_OFFSET_LBN 20
+#define FSF_AZ_RX_USER_2BYTE_OFFSET_WIDTH 12
+#define FSF_AZ_RX_USER_BUF_ID_LBN 0
+#define FSF_AZ_RX_USER_BUF_ID_WIDTH 20
+
+
+/*------------------------------------------------------------*/
+/* FS_TX_EV */
+#define FSF_AZ_TX_EV_PKT_ERR_LBN 38
+#define FSF_AZ_TX_EV_PKT_ERR_WIDTH 1
+#define FSF_AZ_TX_EV_PKT_TOO_BIG_LBN 37
+#define FSF_AZ_TX_EV_PKT_TOO_BIG_WIDTH 1
+#define FSF_AZ_TX_EV_Q_LABEL_LBN 32
+#define FSF_AZ_TX_EV_Q_LABEL_WIDTH 5
+#define FSF_AZ_TX_EV_PORT_LBN 16
+#define FSF_AZ_TX_EV_PORT_WIDTH 1
+#define FSF_AZ_TX_EV_WQ_FF_FULL_LBN 15
+#define FSF_AZ_TX_EV_WQ_FF_FULL_WIDTH 1
+#define FSF_AZ_TX_EV_BUF_OWNER_ID_ERR_LBN 14
+#define FSF_AZ_TX_EV_BUF_OWNER_ID_ERR_WIDTH 1
+#define FSF_AZ_TX_EV_COMP_LBN 12
+#define FSF_AZ_TX_EV_COMP_WIDTH 1
+#define FSF_AZ_TX_EV_DESC_PTR_LBN 0
+#define FSF_AZ_TX_EV_DESC_PTR_WIDTH 12
+
+
+/*------------------------------------------------------------*/
+/* FS_TX_KER_DESC */
+#define FSF_AZ_TX_KER_CONT_LBN 62
+#define FSF_AZ_TX_KER_CONT_WIDTH 1
+#define FSF_AZ_TX_KER_BYTE_COUNT_LBN 48
+#define FSF_AZ_TX_KER_BYTE_COUNT_WIDTH 14
+#define FSF_AZ_TX_KER_BUF_REGION_LBN 46
+#define FSF_AZ_TX_KER_BUF_REGION_WIDTH 2
+#define FSF_AZ_TX_KER_BUF_ADDR_LBN 0
+#define FSF_AZ_TX_KER_BUF_ADDR_WIDTH 46
+
+
+/*------------------------------------------------------------*/
+/* FS_TX_USER_DESC */
+#define FSF_AZ_TX_USER_SW_EV_EN_LBN 48
+#define FSF_AZ_TX_USER_SW_EV_EN_WIDTH 1
+#define FSF_AZ_TX_USER_CONT_LBN 46
+#define FSF_AZ_TX_USER_CONT_WIDTH 1
+#define FSF_AZ_TX_USER_BYTE_CNT_LBN 33
+#define FSF_AZ_TX_USER_BYTE_CNT_WIDTH 13
+#define FSF_AZ_TX_USER_BUF_ID_LBN 13
+#define FSF_AZ_TX_USER_BUF_ID_WIDTH 20
+#define FSF_AZ_TX_USER_BYTE_OFS_LBN 0
+#define FSF_AZ_TX_USER_BYTE_OFS_WIDTH 13
+
+
+/*------------------------------------------------------------*/
+/* FS_USER_EV */
+#define FSF_CZ_USER_QID_LBN 32
+#define FSF_CZ_USER_QID_WIDTH 10
+#define FSF_CZ_USER_EV_REG_VALUE_LBN 0
+#define FSF_CZ_USER_EV_REG_VALUE_WIDTH 32
+
+
+#endif /* HOST_PROGMODEL_DEFS_H */
--- /dev/null
+/****************************************************************************
+ * Driver for Solarflare network controllers -
+ * resource management for Xen backend, OpenOnload, etc
+ * (including support for SFE4001 10GBT NIC)
+ *
+ * This file provides EtherFabric NIC hardware interface common
+ * definitions.
+ *
+ * Copyright 2005-2010: Solarflare Communications Inc,
+ * 9501 Jeronimo Road, Suite 250,
+ * Irvine, CA 92618, USA
+ *
+ * Developed and maintained by Solarflare Communications:
+ * <linux-xen-drivers@solarflare.com>
+ * <onload-dev@solarflare.com>
+ *
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation, incorporated herein by reference.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ ****************************************************************************
+ */
+
+#ifndef HOST_MAC_PROGMODEL_DEFS_H
+#define HOST_MAC_PROGMODEL_DEFS_H
+
+/*------------------------------------------------------------*/
+/*
+ * FR_AB_MD_TXD_REG(128bit):
+ * PHY management transmit data register
+ */
+#define FR_AB_MD_TXD_REG_OFST 0x00000c00
+/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */
+
+#define FRF_AB_MD_TXD_LBN 0
+#define FRF_AB_MD_TXD_WIDTH 16
+
+
+/*------------------------------------------------------------*/
+/*
+ * FR_AB_MD_RXD_REG(128bit):
+ * PHY management receive data register
+ */
+#define FR_AB_MD_RXD_REG_OFST 0x00000c10
+/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */
+
+#define FRF_AB_MD_RXD_LBN 0
+#define FRF_AB_MD_RXD_WIDTH 16
+
+
+/*------------------------------------------------------------*/
+/*
+ * FR_AB_MD_CS_REG(128bit):
+ * PHY management configuration & status register
+ */
+#define FR_AB_MD_CS_REG_OFST 0x00000c20
+/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */
+
+#define FRF_AB_MD_RD_EN_CMD_LBN 15
+#define FRF_AB_MD_RD_EN_CMD_WIDTH 1
+#define FRF_AB_MD_WR_EN_CMD_LBN 14
+#define FRF_AB_MD_WR_EN_CMD_WIDTH 1
+#define FRF_AB_MD_ADDR_CMD_LBN 13
+#define FRF_AB_MD_ADDR_CMD_WIDTH 1
+#define FRF_AB_MD_PT_LBN 7
+#define FRF_AB_MD_PT_WIDTH 3
+#define FRF_AB_MD_PL_LBN 6
+#define FRF_AB_MD_PL_WIDTH 1
+#define FRF_AB_MD_INT_CLR_LBN 5
+#define FRF_AB_MD_INT_CLR_WIDTH 1
+#define FRF_AB_MD_GC_LBN 4
+#define FRF_AB_MD_GC_WIDTH 1
+#define FRF_AB_MD_PRSP_LBN 3
+#define FRF_AB_MD_PRSP_WIDTH 1
+#define FRF_AB_MD_RIC_LBN 2
+#define FRF_AB_MD_RIC_WIDTH 1
+#define FRF_AB_MD_RDC_LBN 1
+#define FRF_AB_MD_RDC_WIDTH 1
+#define FRF_AB_MD_WRC_LBN 0
+#define FRF_AB_MD_WRC_WIDTH 1
+
+
+/*------------------------------------------------------------*/
+/*
+ * FR_AB_MD_PHY_ADR_REG(128bit):
+ * PHY management PHY address register
+ */
+#define FR_AB_MD_PHY_ADR_REG_OFST 0x00000c30
+/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */
+
+#define FRF_AB_MD_PHY_ADR_LBN 0
+#define FRF_AB_MD_PHY_ADR_WIDTH 16
+
+
+/*------------------------------------------------------------*/
+/*
+ * FR_AB_MD_ID_REG(128bit):
+ * PHY management ID register
+ */
+#define FR_AB_MD_ID_REG_OFST 0x00000c40
+/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */
+
+#define FRF_AB_MD_PRT_ADR_LBN 11
+#define FRF_AB_MD_PRT_ADR_WIDTH 5
+#define FRF_AB_MD_DEV_ADR_LBN 6
+#define FRF_AB_MD_DEV_ADR_WIDTH 5
+
+
+/*------------------------------------------------------------*/
+/*
+ * FR_AB_MD_STAT_REG(128bit):
+ * PHY management status & mask register
+ */
+#define FR_AB_MD_STAT_REG_OFST 0x00000c50
+/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */
+
+#define FRF_AB_MD_PINT_LBN 4
+#define FRF_AB_MD_PINT_WIDTH 1
+#define FRF_AB_MD_DONE_LBN 3
+#define FRF_AB_MD_DONE_WIDTH 1
+#define FRF_AB_MD_BSERR_LBN 2
+#define FRF_AB_MD_BSERR_WIDTH 1
+#define FRF_AB_MD_LNFL_LBN 1
+#define FRF_AB_MD_LNFL_WIDTH 1
+#define FRF_AB_MD_BSY_LBN 0
+#define FRF_AB_MD_BSY_WIDTH 1
+
+
+/*------------------------------------------------------------*/
+/*
+ * FR_AB_MAC_STAT_DMA_REG(128bit):
+ * Port MAC statistical counter DMA register
+ */
+#define FR_AB_MAC_STAT_DMA_REG_OFST 0x00000c60
+/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */
+
+#define FRF_AB_MAC_STAT_DMA_CMD_LBN 48
+#define FRF_AB_MAC_STAT_DMA_CMD_WIDTH 1
+#define FRF_AB_MAC_STAT_DMA_ADR_LBN 0
+#define FRF_AB_MAC_STAT_DMA_ADR_WIDTH 48
+
+
+/*------------------------------------------------------------*/
+/*
+ * FR_AB_MAC_CTRL_REG(128bit):
+ * Port MAC control register
+ */
+#define FR_AB_MAC_CTRL_REG_OFST 0x00000c80
+/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */
+
+#define FRF_AB_MAC_XOFF_VAL_LBN 16
+#define FRF_AB_MAC_XOFF_VAL_WIDTH 16
+#define FRF_BB_TXFIFO_DRAIN_EN_LBN 7
+#define FRF_BB_TXFIFO_DRAIN_EN_WIDTH 1
+#define FRF_AB_MAC_XG_DISTXCRC_LBN 5
+#define FRF_AB_MAC_XG_DISTXCRC_WIDTH 1
+#define FRF_AB_MAC_BCAD_ACPT_LBN 4
+#define FRF_AB_MAC_BCAD_ACPT_WIDTH 1
+#define FRF_AB_MAC_UC_PROM_LBN 3
+#define FRF_AB_MAC_UC_PROM_WIDTH 1
+#define FRF_AB_MAC_LINK_STATUS_LBN 2
+#define FRF_AB_MAC_LINK_STATUS_WIDTH 1
+#define FRF_AB_MAC_SPEED_LBN 0
+#define FRF_AB_MAC_SPEED_WIDTH 2
+#define FFE_AB_MAC_SPEED_10G 3
+#define FFE_AB_MAC_SPEED_1G 2
+#define FFE_AB_MAC_SPEED_100M 1
+#define FFE_AB_MAC_SPEED_10M 0
+
+
+/*------------------------------------------------------------*/
+/*
+ * FR_BB_GEN_MODE_REG(128bit):
+ * General Purpose mode register (external interrupt mask)
+ */
+#define FR_BB_GEN_MODE_REG_OFST 0x00000c90
+/* falconb0=net_func_bar2 */
+
+#define FRF_BB_XFP_PHY_INT_POL_SEL_LBN 3
+#define FRF_BB_XFP_PHY_INT_POL_SEL_WIDTH 1
+#define FRF_BB_XG_PHY_INT_POL_SEL_LBN 2
+#define FRF_BB_XG_PHY_INT_POL_SEL_WIDTH 1
+#define FRF_BB_XFP_PHY_INT_MASK_LBN 1
+#define FRF_BB_XFP_PHY_INT_MASK_WIDTH 1
+#define FRF_BB_XG_PHY_INT_MASK_LBN 0
+#define FRF_BB_XG_PHY_INT_MASK_WIDTH 1
+
+
+/*------------------------------------------------------------*/
+/*
+ * FR_AB_MAC_MC_HASH_REG0(128bit):
+ * Multicast address hash table
+ */
+#define FR_AB_MAC_MC_HASH_REG0_OFST 0x00000ca0
+/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */
+
+#define FRF_AB_MAC_MCAST_HASH0_LBN 0
+#define FRF_AB_MAC_MCAST_HASH0_WIDTH 128
+
+
+/*------------------------------------------------------------*/
+/*
+ * FR_AB_MAC_MC_HASH_REG1(128bit):
+ * Multicast address hash table
+ */
+#define FR_AB_MAC_MC_HASH_REG1_OFST 0x00000cb0
+/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */
+
+#define FRF_AB_MAC_MCAST_HASH1_LBN 0
+#define FRF_AB_MAC_MCAST_HASH1_WIDTH 128
+
+
+/*------------------------------------------------------------*/
+/*
+ * FR_AB_GM_CFG1_REG(32bit):
+ * GMAC configuration register 1
+ */
+#define FR_AB_GM_CFG1_REG_OFST 0x00000e00
+/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */
+
+#define FRF_AB_GM_SW_RST_LBN 31
+#define FRF_AB_GM_SW_RST_WIDTH 1
+#define FRF_AB_GM_SIM_RST_LBN 30
+#define FRF_AB_GM_SIM_RST_WIDTH 1
+#define FRF_AB_GM_RST_RX_MAC_CTL_LBN 19
+#define FRF_AB_GM_RST_RX_MAC_CTL_WIDTH 1
+#define FRF_AB_GM_RST_TX_MAC_CTL_LBN 18
+#define FRF_AB_GM_RST_TX_MAC_CTL_WIDTH 1
+#define FRF_AB_GM_RST_RX_FUNC_LBN 17
+#define FRF_AB_GM_RST_RX_FUNC_WIDTH 1
+#define FRF_AB_GM_RST_TX_FUNC_LBN 16
+#define FRF_AB_GM_RST_TX_FUNC_WIDTH 1
+#define FRF_AB_GM_LOOP_LBN 8
+#define FRF_AB_GM_LOOP_WIDTH 1
+#define FRF_AB_GM_RX_FC_EN_LBN 5
+#define FRF_AB_GM_RX_FC_EN_WIDTH 1
+#define FRF_AB_GM_TX_FC_EN_LBN 4
+#define FRF_AB_GM_TX_FC_EN_WIDTH 1
+#define FRF_AB_GM_SYNC_RXEN_LBN 3
+#define FRF_AB_GM_SYNC_RXEN_WIDTH 1
+#define FRF_AB_GM_RX_EN_LBN 2
+#define FRF_AB_GM_RX_EN_WIDTH 1
+#define FRF_AB_GM_SYNC_TXEN_LBN 1
+#define FRF_AB_GM_SYNC_TXEN_WIDTH 1
+#define FRF_AB_GM_TX_EN_LBN 0
+#define FRF_AB_GM_TX_EN_WIDTH 1
+
+
+/*------------------------------------------------------------*/
+/*
+ * FR_AB_GM_CFG2_REG(32bit):
+ * GMAC configuration register 2
+ */
+#define FR_AB_GM_CFG2_REG_OFST 0x00000e10
+/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */
+
+#define FRF_AB_GM_PAMBL_LEN_LBN 12
+#define FRF_AB_GM_PAMBL_LEN_WIDTH 4
+#define FRF_AB_GM_IF_MODE_LBN 8
+#define FRF_AB_GM_IF_MODE_WIDTH 2
+#define FFE_AB_IF_MODE_BYTE_MODE 2
+#define FFE_AB_IF_MODE_NIBBLE_MODE 1
+#define FRF_AB_GM_HUGE_FRM_EN_LBN 5
+#define FRF_AB_GM_HUGE_FRM_EN_WIDTH 1
+#define FRF_AB_GM_LEN_CHK_LBN 4
+#define FRF_AB_GM_LEN_CHK_WIDTH 1
+#define FRF_AB_GM_PAD_CRC_EN_LBN 2
+#define FRF_AB_GM_PAD_CRC_EN_WIDTH 1
+#define FRF_AB_GM_CRC_EN_LBN 1
+#define FRF_AB_GM_CRC_EN_WIDTH 1
+#define FRF_AB_GM_FD_LBN 0
+#define FRF_AB_GM_FD_WIDTH 1
+
+
+/*------------------------------------------------------------*/
+/*
+ * FR_AB_GM_IPG_REG(32bit):
+ * GMAC IPG register
+ */
+#define FR_AB_GM_IPG_REG_OFST 0x00000e20
+/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */
+
+#define FRF_AB_GM_NONB2B_IPG1_LBN 24
+#define FRF_AB_GM_NONB2B_IPG1_WIDTH 7
+#define FRF_AB_GM_NONB2B_IPG2_LBN 16
+#define FRF_AB_GM_NONB2B_IPG2_WIDTH 7
+#define FRF_AB_GM_MIN_IPG_ENF_LBN 8
+#define FRF_AB_GM_MIN_IPG_ENF_WIDTH 8
+#define FRF_AB_GM_B2B_IPG_LBN 0
+#define FRF_AB_GM_B2B_IPG_WIDTH 7
+
+
+/*------------------------------------------------------------*/
+/*
+ * FR_AB_GM_HD_REG(32bit):
+ * GMAC half duplex register
+ */
+#define FR_AB_GM_HD_REG_OFST 0x00000e30
+/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */
+
+#define FRF_AB_GM_ALT_BOFF_VAL_LBN 20
+#define FRF_AB_GM_ALT_BOFF_VAL_WIDTH 4
+#define FRF_AB_GM_ALT_BOFF_EN_LBN 19
+#define FRF_AB_GM_ALT_BOFF_EN_WIDTH 1
+#define FRF_AB_GM_BP_NO_BOFF_LBN 18
+#define FRF_AB_GM_BP_NO_BOFF_WIDTH 1
+#define FRF_AB_GM_DIS_BOFF_LBN 17
+#define FRF_AB_GM_DIS_BOFF_WIDTH 1
+#define FRF_AB_GM_EXDEF_TX_EN_LBN 16
+#define FRF_AB_GM_EXDEF_TX_EN_WIDTH 1
+#define FRF_AB_GM_RTRY_LIMIT_LBN 12
+#define FRF_AB_GM_RTRY_LIMIT_WIDTH 4
+#define FRF_AB_GM_COL_WIN_LBN 0
+#define FRF_AB_GM_COL_WIN_WIDTH 10
+
+
+/*------------------------------------------------------------*/
+/*
+ * FR_AB_GM_MAX_FLEN_REG(32bit):
+ * GMAC maximum frame length register
+ */
+#define FR_AB_GM_MAX_FLEN_REG_OFST 0x00000e40
+/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */
+
+#define FRF_AB_GM_MAX_FLEN_LBN 0
+#define FRF_AB_GM_MAX_FLEN_WIDTH 16
+
+
+/*------------------------------------------------------------*/
+/*
+ * FR_AB_GM_TEST_REG(32bit):
+ * GMAC test register
+ */
+#define FR_AB_GM_TEST_REG_OFST 0x00000e70
+/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */
+
+#define FRF_AB_GM_MAX_BOFF_LBN 3
+#define FRF_AB_GM_MAX_BOFF_WIDTH 1
+#define FRF_AB_GM_REG_TX_FLOW_EN_LBN 2
+#define FRF_AB_GM_REG_TX_FLOW_EN_WIDTH 1
+#define FRF_AB_GM_TEST_PAUSE_LBN 1
+#define FRF_AB_GM_TEST_PAUSE_WIDTH 1
+#define FRF_AB_GM_SHORT_SLOT_LBN 0
+#define FRF_AB_GM_SHORT_SLOT_WIDTH 1
+
+
+/*------------------------------------------------------------*/
+/*
+ * FR_AB_GM_ADR1_REG(32bit):
+ * GMAC station address register 1
+ */
+#define FR_AB_GM_ADR1_REG_OFST 0x00000f00
+/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */
+
+#define FRF_AB_GM_ADR_B0_LBN 24
+#define FRF_AB_GM_ADR_B0_WIDTH 8
+#define FRF_AB_GM_ADR_B1_LBN 16
+#define FRF_AB_GM_ADR_B1_WIDTH 8
+#define FRF_AB_GM_ADR_B2_LBN 8
+#define FRF_AB_GM_ADR_B2_WIDTH 8
+#define FRF_AB_GM_ADR_B3_LBN 0
+#define FRF_AB_GM_ADR_B3_WIDTH 8
+
+
+/*------------------------------------------------------------*/
+/*
+ * FR_AB_GM_ADR2_REG(32bit):
+ * GMAC station address register 2
+ */
+#define FR_AB_GM_ADR2_REG_OFST 0x00000f10
+/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */
+
+#define FRF_AB_GM_ADR_B4_LBN 24
+#define FRF_AB_GM_ADR_B4_WIDTH 8
+#define FRF_AB_GM_ADR_B5_LBN 16
+#define FRF_AB_GM_ADR_B5_WIDTH 8
+
+
+/*------------------------------------------------------------*/
+/*
+ * FR_AB_GMF_CFG0_REG(32bit):
+ * GMAC FIFO configuration register 0
+ */
+#define FR_AB_GMF_CFG0_REG_OFST 0x00000f20
+/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */
+
+#define FRF_AB_GMF_FTFENRPLY_LBN 20
+#define FRF_AB_GMF_FTFENRPLY_WIDTH 1
+#define FRF_AB_GMF_STFENRPLY_LBN 19
+#define FRF_AB_GMF_STFENRPLY_WIDTH 1
+#define FRF_AB_GMF_FRFENRPLY_LBN 18
+#define FRF_AB_GMF_FRFENRPLY_WIDTH 1
+#define FRF_AB_GMF_SRFENRPLY_LBN 17
+#define FRF_AB_GMF_SRFENRPLY_WIDTH 1
+#define FRF_AB_GMF_WTMENRPLY_LBN 16
+#define FRF_AB_GMF_WTMENRPLY_WIDTH 1
+#define FRF_AB_GMF_FTFENREQ_LBN 12
+#define FRF_AB_GMF_FTFENREQ_WIDTH 1
+#define FRF_AB_GMF_STFENREQ_LBN 11
+#define FRF_AB_GMF_STFENREQ_WIDTH 1
+#define FRF_AB_GMF_FRFENREQ_LBN 10
+#define FRF_AB_GMF_FRFENREQ_WIDTH 1
+#define FRF_AB_GMF_SRFENREQ_LBN 9
+#define FRF_AB_GMF_SRFENREQ_WIDTH 1
+#define FRF_AB_GMF_WTMENREQ_LBN 8
+#define FRF_AB_GMF_WTMENREQ_WIDTH 1
+#define FRF_AB_GMF_HSTRSTFT_LBN 4
+#define FRF_AB_GMF_HSTRSTFT_WIDTH 1
+#define FRF_AB_GMF_HSTRSTST_LBN 3
+#define FRF_AB_GMF_HSTRSTST_WIDTH 1
+#define FRF_AB_GMF_HSTRSTFR_LBN 2
+#define FRF_AB_GMF_HSTRSTFR_WIDTH 1
+#define FRF_AB_GMF_HSTRSTSR_LBN 1
+#define FRF_AB_GMF_HSTRSTSR_WIDTH 1
+#define FRF_AB_GMF_HSTRSTWT_LBN 0
+#define FRF_AB_GMF_HSTRSTWT_WIDTH 1
+
+
+/*------------------------------------------------------------*/
+/*
+ * FR_AB_GMF_CFG1_REG(32bit):
+ * GMAC FIFO configuration register 1
+ */
+#define FR_AB_GMF_CFG1_REG_OFST 0x00000f30
+/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */
+
+#define FRF_AB_GMF_CFGFRTH_LBN 16
+#define FRF_AB_GMF_CFGFRTH_WIDTH 5
+#define FRF_AB_GMF_CFGXOFFRTX_LBN 0
+#define FRF_AB_GMF_CFGXOFFRTX_WIDTH 16
+
+
+/*------------------------------------------------------------*/
+/*
+ * FR_AB_GMF_CFG2_REG(32bit):
+ * GMAC FIFO configuration register 2
+ */
+#define FR_AB_GMF_CFG2_REG_OFST 0x00000f40
+/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */
+
+#define FRF_AB_GMF_CFGHWM_LBN 16
+#define FRF_AB_GMF_CFGHWM_WIDTH 6
+#define FRF_AB_GMF_CFGLWM_LBN 0
+#define FRF_AB_GMF_CFGLWM_WIDTH 6
+
+
+/*------------------------------------------------------------*/
+/*
+ * FR_AB_GMF_CFG3_REG(32bit):
+ * GMAC FIFO configuration register 3
+ */
+#define FR_AB_GMF_CFG3_REG_OFST 0x00000f50
+/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */
+
+#define FRF_AB_GMF_CFGHWMFT_LBN 16
+#define FRF_AB_GMF_CFGHWMFT_WIDTH 6
+#define FRF_AB_GMF_CFGFTTH_LBN 0
+#define FRF_AB_GMF_CFGFTTH_WIDTH 6
+
+
+/*------------------------------------------------------------*/
+/*
+ * FR_AB_GMF_CFG4_REG(32bit):
+ * GMAC FIFO configuration register 4
+ */
+#define FR_AB_GMF_CFG4_REG_OFST 0x00000f60
+/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */
+
+#define FRF_AB_GMF_HSTFLTRFRM_LBN 0
+#define FRF_AB_GMF_HSTFLTRFRM_WIDTH 18
+
+
+/*------------------------------------------------------------*/
+/*
+ * FR_AB_GMF_CFG5_REG(32bit):
+ * GMAC FIFO configuration register 5
+ */
+#define FR_AB_GMF_CFG5_REG_OFST 0x00000f70
+/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */
+
+#define FRF_AB_GMF_CFGHDPLX_LBN 22
+#define FRF_AB_GMF_CFGHDPLX_WIDTH 1
+#define FRF_AB_GMF_SRFULL_LBN 21
+#define FRF_AB_GMF_SRFULL_WIDTH 1
+#define FRF_AB_GMF_HSTSRFULLCLR_LBN 20
+#define FRF_AB_GMF_HSTSRFULLCLR_WIDTH 1
+#define FRF_AB_GMF_CFGBYTMODE_LBN 19
+#define FRF_AB_GMF_CFGBYTMODE_WIDTH 1
+#define FRF_AB_GMF_HSTDRPLT64_LBN 18
+#define FRF_AB_GMF_HSTDRPLT64_WIDTH 1
+#define FRF_AB_GMF_HSTFLTRFRMDC_LBN 0
+#define FRF_AB_GMF_HSTFLTRFRMDC_WIDTH 18
+
+
+/*------------------------------------------------------------*/
+/*
+ * FR_AB_XM_ADR_LO_REG(128bit):
+ * XGMAC address register low
+ */
+#define FR_AB_XM_ADR_LO_REG_OFST 0x00001200
+/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */
+
+#define FRF_AB_XM_ADR_LO_LBN 0
+#define FRF_AB_XM_ADR_LO_WIDTH 32
+
+
+/*------------------------------------------------------------*/
+/*
+ * FR_AB_XM_ADR_HI_REG(128bit):
+ * XGMAC address register high
+ */
+#define FR_AB_XM_ADR_HI_REG_OFST 0x00001210
+/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */
+
+#define FRF_AB_XM_ADR_HI_LBN 0
+#define FRF_AB_XM_ADR_HI_WIDTH 16
+
+
+/*------------------------------------------------------------*/
+/*
+ * FR_AB_XM_GLB_CFG_REG(128bit):
+ * XGMAC global configuration
+ */
+#define FR_AB_XM_GLB_CFG_REG_OFST 0x00001220
+/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */
+
+#define FRF_AB_XM_RMTFLT_GEN_LBN 17
+#define FRF_AB_XM_RMTFLT_GEN_WIDTH 1
+#define FRF_AB_XM_DEBUG_MODE_LBN 16
+#define FRF_AB_XM_DEBUG_MODE_WIDTH 1
+#define FRF_AB_XM_RX_STAT_EN_LBN 11
+#define FRF_AB_XM_RX_STAT_EN_WIDTH 1
+#define FRF_AB_XM_TX_STAT_EN_LBN 10
+#define FRF_AB_XM_TX_STAT_EN_WIDTH 1
+#define FRF_AB_XM_RX_JUMBO_MODE_LBN 6
+#define FRF_AB_XM_RX_JUMBO_MODE_WIDTH 1
+#define FRF_AB_XM_WAN_MODE_LBN 5
+#define FRF_AB_XM_WAN_MODE_WIDTH 1
+#define FRF_AB_XM_INTCLR_MODE_LBN 3
+#define FRF_AB_XM_INTCLR_MODE_WIDTH 1
+#define FRF_AB_XM_CORE_RST_LBN 0
+#define FRF_AB_XM_CORE_RST_WIDTH 1
+
+
+/*------------------------------------------------------------*/
+/*
+ * FR_AB_XM_TX_CFG_REG(128bit):
+ * XGMAC transmit configuration
+ */
+#define FR_AB_XM_TX_CFG_REG_OFST 0x00001230
+/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */
+
+#define FRF_AB_XM_TX_PROG_LBN 24
+#define FRF_AB_XM_TX_PROG_WIDTH 1
+#define FRF_AB_XM_IPG_LBN 16
+#define FRF_AB_XM_IPG_WIDTH 4
+#define FRF_AB_XM_FCNTL_LBN 10
+#define FRF_AB_XM_FCNTL_WIDTH 1
+#define FRF_AB_XM_TXCRC_LBN 8
+#define FRF_AB_XM_TXCRC_WIDTH 1
+#define FRF_AB_XM_EDRC_LBN 6
+#define FRF_AB_XM_EDRC_WIDTH 1
+#define FRF_AB_XM_AUTO_PAD_LBN 5
+#define FRF_AB_XM_AUTO_PAD_WIDTH 1
+#define FRF_AB_XM_TX_PRMBL_LBN 2
+#define FRF_AB_XM_TX_PRMBL_WIDTH 1
+#define FRF_AB_XM_TXEN_LBN 1
+#define FRF_AB_XM_TXEN_WIDTH 1
+#define FRF_AB_XM_TX_RST_LBN 0
+#define FRF_AB_XM_TX_RST_WIDTH 1
+
+
+/*------------------------------------------------------------*/
+/*
+ * FR_AB_XM_RX_CFG_REG(128bit):
+ * XGMAC receive configuration
+ */
+#define FR_AB_XM_RX_CFG_REG_OFST 0x00001240
+/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */
+
+#define FRF_AB_XM_PASS_LENERR_LBN 26
+#define FRF_AB_XM_PASS_LENERR_WIDTH 1
+#define FRF_AB_XM_PASS_CRC_ERR_LBN 25
+#define FRF_AB_XM_PASS_CRC_ERR_WIDTH 1
+#define FRF_AB_XM_PASS_PRMBLE_ERR_LBN 24
+#define FRF_AB_XM_PASS_PRMBLE_ERR_WIDTH 1
+#define FRF_AB_XM_REJ_BCAST_LBN 20
+#define FRF_AB_XM_REJ_BCAST_WIDTH 1
+#define FRF_AB_XM_ACPT_ALL_MCAST_LBN 11
+#define FRF_AB_XM_ACPT_ALL_MCAST_WIDTH 1
+#define FRF_AB_XM_ACPT_ALL_UCAST_LBN 9
+#define FRF_AB_XM_ACPT_ALL_UCAST_WIDTH 1
+#define FRF_AB_XM_AUTO_DEPAD_LBN 8
+#define FRF_AB_XM_AUTO_DEPAD_WIDTH 1
+#define FRF_AB_XM_RXCRC_LBN 3
+#define FRF_AB_XM_RXCRC_WIDTH 1
+#define FRF_AB_XM_RX_PRMBL_LBN 2
+#define FRF_AB_XM_RX_PRMBL_WIDTH 1
+#define FRF_AB_XM_RXEN_LBN 1
+#define FRF_AB_XM_RXEN_WIDTH 1
+#define FRF_AB_XM_RX_RST_LBN 0
+#define FRF_AB_XM_RX_RST_WIDTH 1
+
+
+/*------------------------------------------------------------*/
+/*
+ * FR_AB_XM_MGT_INT_MASK(128bit):
+ * documentation to be written for sum_XM_MGT_INT_MASK
+ */
+#define FR_AB_XM_MGT_INT_MASK_OFST 0x00001250
+/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */
+
+#define FRF_AB_XM_MSK_STA_INTR_LBN 16
+#define FRF_AB_XM_MSK_STA_INTR_WIDTH 1
+#define FRF_AB_XM_MSK_STAT_CNTR_HF_LBN 9
+#define FRF_AB_XM_MSK_STAT_CNTR_HF_WIDTH 1
+#define FRF_AB_XM_MSK_STAT_CNTR_OF_LBN 8
+#define FRF_AB_XM_MSK_STAT_CNTR_OF_WIDTH 1
+#define FRF_AB_XM_MSK_PRMBLE_ERR_LBN 2
+#define FRF_AB_XM_MSK_PRMBLE_ERR_WIDTH 1
+#define FRF_AB_XM_MSK_RMTFLT_LBN 1
+#define FRF_AB_XM_MSK_RMTFLT_WIDTH 1
+#define FRF_AB_XM_MSK_LCLFLT_LBN 0
+#define FRF_AB_XM_MSK_LCLFLT_WIDTH 1
+
+
+/*------------------------------------------------------------*/
+/*
+ * FR_AB_XM_FC_REG(128bit):
+ * XGMAC flow control register
+ */
+#define FR_AB_XM_FC_REG_OFST 0x00001270
+/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */
+
+#define FRF_AB_XM_PAUSE_TIME_LBN 16
+#define FRF_AB_XM_PAUSE_TIME_WIDTH 16
+#define FRF_AB_XM_RX_MAC_STAT_LBN 11
+#define FRF_AB_XM_RX_MAC_STAT_WIDTH 1
+#define FRF_AB_XM_TX_MAC_STAT_LBN 10
+#define FRF_AB_XM_TX_MAC_STAT_WIDTH 1
+#define FRF_AB_XM_MCNTL_PASS_LBN 8
+#define FRF_AB_XM_MCNTL_PASS_WIDTH 2
+#define FRF_AB_XM_REJ_CNTL_UCAST_LBN 6
+#define FRF_AB_XM_REJ_CNTL_UCAST_WIDTH 1
+#define FRF_AB_XM_REJ_CNTL_MCAST_LBN 5
+#define FRF_AB_XM_REJ_CNTL_MCAST_WIDTH 1
+#define FRF_AB_XM_ZPAUSE_LBN 2
+#define FRF_AB_XM_ZPAUSE_WIDTH 1
+#define FRF_AB_XM_XMIT_PAUSE_LBN 1
+#define FRF_AB_XM_XMIT_PAUSE_WIDTH 1
+#define FRF_AB_XM_DIS_FCNTL_LBN 0
+#define FRF_AB_XM_DIS_FCNTL_WIDTH 1
+
+
+/*------------------------------------------------------------*/
+/*
+ * FR_AB_XM_PAUSE_TIME_REG(128bit):
+ * XGMAC pause time register
+ */
+#define FR_AB_XM_PAUSE_TIME_REG_OFST 0x00001290
+/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */
+
+#define FRF_AB_XM_TX_PAUSE_CNT_LBN 16
+#define FRF_AB_XM_TX_PAUSE_CNT_WIDTH 16
+#define FRF_AB_XM_RX_PAUSE_CNT_LBN 0
+#define FRF_AB_XM_RX_PAUSE_CNT_WIDTH 16
+
+
+/*------------------------------------------------------------*/
+/*
+ * FR_AB_XM_TX_PARAM_REG(128bit):
+ * XGMAC transmit parameter register
+ */
+#define FR_AB_XM_TX_PARAM_REG_OFST 0x000012d0
+/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */
+
+#define FRF_AB_XM_TX_JUMBO_MODE_LBN 31
+#define FRF_AB_XM_TX_JUMBO_MODE_WIDTH 1
+#define FRF_AB_XM_MAX_TX_FRM_SIZE_HI_LBN 19
+#define FRF_AB_XM_MAX_TX_FRM_SIZE_HI_WIDTH 11
+#define FRF_AB_XM_MAX_TX_FRM_SIZE_LO_LBN 16
+#define FRF_AB_XM_MAX_TX_FRM_SIZE_LO_WIDTH 3
+#define FRF_AB_XM_PAD_CHAR_LBN 0
+#define FRF_AB_XM_PAD_CHAR_WIDTH 8
+
+
+/*------------------------------------------------------------*/
+/*
+ * FR_AB_XM_RX_PARAM_REG(128bit):
+ * XGMAC receive parameter register
+ */
+#define FR_AB_XM_RX_PARAM_REG_OFST 0x000012e0
+/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */
+
+#define FRF_AB_XM_MAX_RX_FRM_SIZE_HI_LBN 3
+#define FRF_AB_XM_MAX_RX_FRM_SIZE_HI_WIDTH 11
+#define FRF_AB_XM_MAX_RX_FRM_SIZE_LO_LBN 0
+#define FRF_AB_XM_MAX_RX_FRM_SIZE_LO_WIDTH 3
+
+
+/*------------------------------------------------------------*/
+/*
+ * FR_AB_XM_MGT_INT_MSK_REG(128bit):
+ * XGMAC management interrupt mask register
+ */
+#define FR_AB_XM_MGT_INT_MSK_REG_OFST 0x000012f0
+/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */
+
+#define FRF_AB_XM_STAT_CNTR_OF_LBN 9
+#define FRF_AB_XM_STAT_CNTR_OF_WIDTH 1
+#define FRF_AB_XM_STAT_CNTR_HF_LBN 8
+#define FRF_AB_XM_STAT_CNTR_HF_WIDTH 1
+#define FRF_AB_XM_PRMBLE_ERR_LBN 2
+#define FRF_AB_XM_PRMBLE_ERR_WIDTH 1
+#define FRF_AB_XM_RMTFLT_LBN 1
+#define FRF_AB_XM_RMTFLT_WIDTH 1
+#define FRF_AB_XM_LCLFLT_LBN 0
+#define FRF_AB_XM_LCLFLT_WIDTH 1
+
+
+#endif /* HOST_MAC_PROGMODEL_DEFS_H */
--- /dev/null
+/****************************************************************************
+ * Driver for Solarflare network controllers -
+ * resource management for Xen backend, OpenOnload, etc
+ * (including support for SFE4001 10GBT NIC)
+ *
+ * This file provides EtherFabric NIC hardware interface common
+ * definitions.
+ *
+ * Copyright 2005-2010: Solarflare Communications Inc,
+ * 9501 Jeronimo Road, Suite 250,
+ * Irvine, CA 92618, USA
+ *
+ * Developed and maintained by Solarflare Communications:
+ * <linux-xen-drivers@solarflare.com>
+ * <onload-dev@solarflare.com>
+ *
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation, incorporated herein by reference.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ ****************************************************************************
+ */
+
+#ifndef PCI_PROGMODEL_DEFS_H
+#define PCI_PROGMODEL_DEFS_H
+
+/*------------------------------------------------------------*/
+/*
+ * PCR_AZ_PM_CS_REG(16bit):
+ * Power management control & status register
+ */
+#define PCR_AZ_PM_CS_REG 0x00000044
+/* falcona0,falconb0=pci_f0_config,sienaa0=pci_f0_config */
+
+#define PCRF_AZ_PM_PME_STAT_LBN 15
+#define PCRF_AZ_PM_PME_STAT_WIDTH 1
+#define PCRF_AZ_PM_DAT_SCALE_LBN 13
+#define PCRF_AZ_PM_DAT_SCALE_WIDTH 2
+#define PCRF_AZ_PM_DAT_SEL_LBN 9
+#define PCRF_AZ_PM_DAT_SEL_WIDTH 4
+#define PCRF_AZ_PM_PME_EN_LBN 8
+#define PCRF_AZ_PM_PME_EN_WIDTH 1
+#define PCRF_CZ_NO_SOFT_RESET_LBN 3
+#define PCRF_CZ_NO_SOFT_RESET_WIDTH 1
+#define PCRF_AZ_PM_PWR_ST_LBN 0
+#define PCRF_AZ_PM_PWR_ST_WIDTH 2
+
+
+/*------------------------------------------------------------*/
+/*
+ * PCR_AZ_VEND_ID_REG(16bit):
+ * Vendor ID register
+ */
+#define PCR_AZ_VEND_ID_REG 0x00000000
+/* sienaa0=pci_f0_config,falcona0,falconb0=pci_f0_config */
+
+#define PCRF_AZ_VEND_ID_LBN 0
+#define PCRF_AZ_VEND_ID_WIDTH 16
+
+
+/*------------------------------------------------------------*/
+/*
+ * PCR_AZ_DEV_ID_REG(16bit):
+ * Device ID register
+ */
+#define PCR_AZ_DEV_ID_REG 0x00000002
+/* sienaa0=pci_f0_config,falcona0,falconb0=pci_f0_config */
+
+#define PCRF_AZ_DEV_ID_LBN 0
+#define PCRF_AZ_DEV_ID_WIDTH 16
+
+
+/*------------------------------------------------------------*/
+/*
+ * PCR_AZ_REV_ID_REG(8bit):
+ * Class code & revision ID register
+ */
+#define PCR_AZ_REV_ID_REG 0x00000008
+/* sienaa0=pci_f0_config,falcona0,falconb0=pci_f0_config */
+
+#define PCRF_AZ_REV_ID_LBN 0
+#define PCRF_AZ_REV_ID_WIDTH 8
+
+
+/*------------------------------------------------------------*/
+/*
+ * PCR_AZ_CC_REG(24bit):
+ * Class code register
+ */
+#define PCR_AZ_CC_REG 0x00000009
+/* sienaa0=pci_f0_config,falcona0,falconb0=pci_f0_config */
+
+#define PCRF_AZ_BASE_CC_LBN 16
+#define PCRF_AZ_BASE_CC_WIDTH 8
+#define PCRF_AZ_SUB_CC_LBN 8
+#define PCRF_AZ_SUB_CC_WIDTH 8
+#define PCRF_AZ_PROG_IF_LBN 0
+#define PCRF_AZ_PROG_IF_WIDTH 8
+
+
+/*------------------------------------------------------------*/
+/*
+ * PCR_AZ_MST_LAT_REG(8bit):
+ * Master latency timer register
+ */
+#define PCR_AZ_MST_LAT_REG 0x0000000d
+/* sienaa0=pci_f0_config,falcona0,falconb0=pci_f0_config */
+
+#define PCRF_AZ_MST_LAT_LBN 0
+#define PCRF_AZ_MST_LAT_WIDTH 8
+
+
+/*------------------------------------------------------------*/
+/*
+ * PCR_AZ_HDR_TYPE_REG(8bit):
+ * Header type register
+ */
+#define PCR_AZ_HDR_TYPE_REG 0x0000000e
+/* sienaa0=pci_f0_config,falcona0,falconb0=pci_f0_config */
+
+#define PCRF_AZ_MULT_FUNC_LBN 7
+#define PCRF_AZ_MULT_FUNC_WIDTH 1
+#define PCRF_AZ_TYPE_LBN 0
+#define PCRF_AZ_TYPE_WIDTH 7
+
+
+/*------------------------------------------------------------*/
+/*
+ * PCR_AZ_BIST_REG(8bit):
+ * BIST register
+ */
+#define PCR_AZ_BIST_REG 0x0000000f
+/* sienaa0=pci_f0_config,falcona0,falconb0=pci_f0_config */
+
+#define PCRF_AZ_BIST_LBN 0
+#define PCRF_AZ_BIST_WIDTH 8
+
+
+/*------------------------------------------------------------*/
+/*
+ * PCR_CZ_BAR4_LO_REG(32bit):
+ * Primary function base address register 2 low bits
+ */
+#define PCR_CZ_BAR4_LO_REG 0x00000020
+/* sienaa0=pci_f0_config */
+
+#define PCRF_CZ_BAR4_LO_LBN 4
+#define PCRF_CZ_BAR4_LO_WIDTH 28
+#define PCRF_CZ_BAR4_PREF_LBN 3
+#define PCRF_CZ_BAR4_PREF_WIDTH 1
+#define PCRF_CZ_BAR4_TYPE_LBN 1
+#define PCRF_CZ_BAR4_TYPE_WIDTH 2
+#define PCRF_CZ_BAR4_IOM_LBN 0
+#define PCRF_CZ_BAR4_IOM_WIDTH 1
+
+
+/*------------------------------------------------------------*/
+/*
+ * PCR_AZ_SS_ID_REG(16bit):
+ * Sub-system ID register
+ */
+#define PCR_AZ_SS_ID_REG 0x0000002e
+/* sienaa0=pci_f0_config,falcona0,falconb0=pci_f0_config */
+
+#define PCRF_AZ_SS_ID_LBN 0
+#define PCRF_AZ_SS_ID_WIDTH 16
+
+
+/*------------------------------------------------------------*/
+/*
+ * PCR_AZ_EXPROM_BAR_REG(32bit):
+ * Expansion ROM base address register
+ */
+#define PCR_AZ_EXPROM_BAR_REG 0x00000030
+/* sienaa0=pci_f0_config,falcona0,falconb0=pci_f0_config */
+
+#define PCRF_AZ_EXPROM_BAR_LBN 11
+#define PCRF_AZ_EXPROM_BAR_WIDTH 21
+#define PCRF_AB_EXPROM_MIN_SIZE_LBN 2
+#define PCRF_AB_EXPROM_MIN_SIZE_WIDTH 9
+#define PCRF_CZ_EXPROM_MIN_SIZE_LBN 1
+#define PCRF_CZ_EXPROM_MIN_SIZE_WIDTH 10
+#define PCRF_AB_EXPROM_FEATURE_ENABLE_LBN 1
+#define PCRF_AB_EXPROM_FEATURE_ENABLE_WIDTH 1
+#define PCRF_AZ_EXPROM_EN_LBN 0
+#define PCRF_AZ_EXPROM_EN_WIDTH 1
+
+
+/*------------------------------------------------------------*/
+/*
+ * PCR_AZ_CAP_PTR_REG(8bit):
+ * Capability pointer register
+ */
+#define PCR_AZ_CAP_PTR_REG 0x00000034
+/* sienaa0=pci_f0_config,falcona0,falconb0=pci_f0_config */
+
+#define PCRF_AZ_CAP_PTR_LBN 0
+#define PCRF_AZ_CAP_PTR_WIDTH 8
+
+
+/*------------------------------------------------------------*/
+/*
+ * PCR_AZ_INT_LINE_REG(8bit):
+ * Interrupt line register
+ */
+#define PCR_AZ_INT_LINE_REG 0x0000003c
+/* sienaa0=pci_f0_config,falcona0,falconb0=pci_f0_config */
+
+#define PCRF_AZ_INT_LINE_LBN 0
+#define PCRF_AZ_INT_LINE_WIDTH 8
+
+
+/*------------------------------------------------------------*/
+/*
+ * PCR_AZ_INT_PIN_REG(8bit):
+ * Interrupt pin register
+ */
+#define PCR_AZ_INT_PIN_REG 0x0000003d
+/* sienaa0=pci_f0_config,falcona0,falconb0=pci_f0_config */
+
+#define PCRF_AZ_INT_PIN_LBN 0
+#define PCRF_AZ_INT_PIN_WIDTH 8
+
+
+/*------------------------------------------------------------*/
+/*
+ * PCR_AZ_MSI_CAP_ID_REG(8bit):
+ * MSI capability ID
+ */
+#define PCR_AZ_MSI_CAP_ID_REG 0x00000050
+/* sienaa0=pci_f0_config,falcona0,falconb0=pci_f0_config */
+
+#define PCRF_AZ_MSI_CAP_ID_LBN 0
+#define PCRF_AZ_MSI_CAP_ID_WIDTH 8
+
+
+/*------------------------------------------------------------*/
+/*
+ * PCR_AZ_MSI_NXT_PTR_REG(8bit):
+ * MSI next item pointer
+ */
+#define PCR_AZ_MSI_NXT_PTR_REG 0x00000051
+/* sienaa0=pci_f0_config,falcona0,falconb0=pci_f0_config */
+
+#define PCRF_AZ_MSI_NXT_PTR_LBN 0
+#define PCRF_AZ_MSI_NXT_PTR_WIDTH 8
+
+
+/*------------------------------------------------------------*/
+/*
+ * PCR_AZ_MSI_CTL_REG(16bit):
+ * MSI control register
+ */
+#define PCR_AZ_MSI_CTL_REG 0x00000052
+/* sienaa0=pci_f0_config,falcona0,falconb0=pci_f0_config */
+
+#define PCRF_AZ_MSI_64_EN_LBN 7
+#define PCRF_AZ_MSI_64_EN_WIDTH 1
+#define PCRF_AZ_MSI_MULT_MSG_EN_LBN 4
+#define PCRF_AZ_MSI_MULT_MSG_EN_WIDTH 3
+#define PCRF_AZ_MSI_MULT_MSG_CAP_LBN 1
+#define PCRF_AZ_MSI_MULT_MSG_CAP_WIDTH 3
+#define PCRF_AZ_MSI_EN_LBN 0
+#define PCRF_AZ_MSI_EN_WIDTH 1
+
+
+/*------------------------------------------------------------*/
+/*
+ * PCR_AZ_MSI_ADR_HI_REG(32bit):
+ * MSI high 32 bits address register
+ */
+#define PCR_AZ_MSI_ADR_HI_REG 0x00000058
+/* sienaa0=pci_f0_config,falcona0,falconb0=pci_f0_config */
+
+#define PCRF_AZ_MSI_ADR_HI_LBN 0
+#define PCRF_AZ_MSI_ADR_HI_WIDTH 32
+
+
+/*------------------------------------------------------------*/
+/*
+ * PCR_CZ_PCIE_CAP_LIST_REG(16bit):
+ * PCIe capability list register
+ */
+#define PCR_CZ_PCIE_CAP_LIST_REG 0x00000070
+/* sienaa0=pci_f0_config */
+/*
+ * PCR_AB_PCIE_CAP_LIST_REG(16bit):
+ * PCIe capability list register
+ */
+#define PCR_AB_PCIE_CAP_LIST_REG 0x00000060
+/* falcona0,falconb0=pci_f0_config */
+
+#define PCRF_AZ_PCIE_NXT_PTR_LBN 8
+#define PCRF_AZ_PCIE_NXT_PTR_WIDTH 8
+#define PCRF_AZ_PCIE_CAP_ID_LBN 0
+#define PCRF_AZ_PCIE_CAP_ID_WIDTH 8
+
+
+/*------------------------------------------------------------*/
+/*
+ * PCR_CZ_DEV_CAP_REG(28bit):
+ * PCIe device capabilities register
+ */
+#define PCR_CZ_DEV_CAP_REG 0x00000074
+/* sienaa0=pci_f0_config */
+/*
+ * PCR_AB_DEV_CAP_REG(28bit):
+ * PCIe device capabilities register
+ */
+#define PCR_AB_DEV_CAP_REG 0x00000064
+/* falcona0,falconb0=pci_f0_config */
+
+#define PCRF_CZ_CAP_FN_LEVEL_RESET_LBN 28
+#define PCRF_CZ_CAP_FN_LEVEL_RESET_WIDTH 1
+#define PCRF_AZ_CAP_SLOT_PWR_SCL_LBN 26
+#define PCRF_AZ_CAP_SLOT_PWR_SCL_WIDTH 2
+#define PCRF_AZ_CAP_SLOT_PWR_VAL_LBN 18
+#define PCRF_AZ_CAP_SLOT_PWR_VAL_WIDTH 8
+#define PCRF_CZ_ROLE_BASE_ERR_REPORTING_LBN 15
+#define PCRF_CZ_ROLE_BASE_ERR_REPORTING_WIDTH 1
+#define PCRF_AB_PWR_IND_LBN 14
+#define PCRF_AB_PWR_IND_WIDTH 1
+#define PCRF_AB_ATTN_IND_LBN 13
+#define PCRF_AB_ATTN_IND_WIDTH 1
+#define PCRF_AB_ATTN_BUTTON_LBN 12
+#define PCRF_AB_ATTN_BUTTON_WIDTH 1
+#define PCRF_AZ_ENDPT_L1_LAT_LBN 9
+#define PCRF_AZ_ENDPT_L1_LAT_WIDTH 3
+#define PCRF_AZ_ENDPT_L0_LAT_LBN 6
+#define PCRF_AZ_ENDPT_L0_LAT_WIDTH 3
+#define PCRF_AZ_TAG_FIELD_LBN 5
+#define PCRF_AZ_TAG_FIELD_WIDTH 1
+#define PCRF_AZ_PHAN_FUNC_LBN 3
+#define PCRF_AZ_PHAN_FUNC_WIDTH 2
+#define PCRF_AZ_MAX_PAYL_SIZE_SUPT_LBN 0
+#define PCRF_AZ_MAX_PAYL_SIZE_SUPT_WIDTH 3
+
+
+/*------------------------------------------------------------*/
+/*
+ * PCR_CZ_DEV_CTL_REG(16bit):
+ * PCIe device control register
+ */
+#define PCR_CZ_DEV_CTL_REG 0x00000078
+/* sienaa0=pci_f0_config */
+/*
+ * PCR_AB_DEV_CTL_REG(16bit):
+ * PCIe device control register
+ */
+#define PCR_AB_DEV_CTL_REG 0x00000068
+/* falcona0,falconb0=pci_f0_config */
+
+#define PCRF_CZ_FN_LEVEL_RESET_LBN 15
+#define PCRF_CZ_FN_LEVEL_RESET_WIDTH 1
+#define PCRF_AZ_MAX_RD_REQ_SIZE_LBN 12
+#define PCRF_AZ_MAX_RD_REQ_SIZE_WIDTH 3
+#define PCFE_AZ_MAX_RD_REQ_SIZE_4096 5
+#define PCFE_AZ_MAX_RD_REQ_SIZE_2048 4
+#define PCFE_AZ_MAX_RD_REQ_SIZE_1024 3
+#define PCFE_AZ_MAX_RD_REQ_SIZE_512 2
+#define PCFE_AZ_MAX_RD_REQ_SIZE_256 1
+#define PCFE_AZ_MAX_RD_REQ_SIZE_128 0
+#define PCRF_AZ_EN_NO_SNOOP_LBN 11
+#define PCRF_AZ_EN_NO_SNOOP_WIDTH 1
+#define PCRF_AZ_AUX_PWR_PM_EN_LBN 10
+#define PCRF_AZ_AUX_PWR_PM_EN_WIDTH 1
+#define PCRF_AZ_PHAN_FUNC_EN_LBN 9
+#define PCRF_AZ_PHAN_FUNC_EN_WIDTH 1
+#define PCRF_AB_DEV_CAP_REG_RSVD0_LBN 8
+#define PCRF_AB_DEV_CAP_REG_RSVD0_WIDTH 1
+#define PCRF_CZ_EXTENDED_TAG_EN_LBN 8
+#define PCRF_CZ_EXTENDED_TAG_EN_WIDTH 1
+#define PCRF_AZ_MAX_PAYL_SIZE_LBN 5
+#define PCRF_AZ_MAX_PAYL_SIZE_WIDTH 3
+#define PCFE_AZ_MAX_PAYL_SIZE_4096 5
+#define PCFE_AZ_MAX_PAYL_SIZE_2048 4
+#define PCFE_AZ_MAX_PAYL_SIZE_1024 3
+#define PCFE_AZ_MAX_PAYL_SIZE_512 2
+#define PCFE_AZ_MAX_PAYL_SIZE_256 1
+#define PCFE_AZ_MAX_PAYL_SIZE_128 0
+#define PCRF_AZ_EN_RELAX_ORDER_LBN 4
+#define PCRF_AZ_EN_RELAX_ORDER_WIDTH 1
+#define PCRF_AZ_UNSUP_REQ_RPT_EN_LBN 3
+#define PCRF_AZ_UNSUP_REQ_RPT_EN_WIDTH 1
+#define PCRF_AZ_FATAL_ERR_RPT_EN_LBN 2
+#define PCRF_AZ_FATAL_ERR_RPT_EN_WIDTH 1
+#define PCRF_AZ_NONFATAL_ERR_RPT_EN_LBN 1
+#define PCRF_AZ_NONFATAL_ERR_RPT_EN_WIDTH 1
+#define PCRF_AZ_CORR_ERR_RPT_EN_LBN 0
+#define PCRF_AZ_CORR_ERR_RPT_EN_WIDTH 1
+
+
+/*------------------------------------------------------------*/
+/*
+ * PCR_CZ_DEV_STAT_REG(16bit):
+ * PCIe device status register
+ */
+#define PCR_CZ_DEV_STAT_REG 0x0000007a
+/* sienaa0=pci_f0_config */
+/*
+ * PCR_AB_DEV_STAT_REG(16bit):
+ * PCIe device status register
+ */
+#define PCR_AB_DEV_STAT_REG 0x0000006a
+/* falcona0,falconb0=pci_f0_config */
+
+#define PCRF_AZ_TRNS_PEND_LBN 5
+#define PCRF_AZ_TRNS_PEND_WIDTH 1
+#define PCRF_AZ_AUX_PWR_DET_LBN 4
+#define PCRF_AZ_AUX_PWR_DET_WIDTH 1
+#define PCRF_AZ_UNSUP_REQ_DET_LBN 3
+#define PCRF_AZ_UNSUP_REQ_DET_WIDTH 1
+#define PCRF_AZ_FATAL_ERR_DET_LBN 2
+#define PCRF_AZ_FATAL_ERR_DET_WIDTH 1
+#define PCRF_AZ_NONFATAL_ERR_DET_LBN 1
+#define PCRF_AZ_NONFATAL_ERR_DET_WIDTH 1
+#define PCRF_AZ_CORR_ERR_DET_LBN 0
+#define PCRF_AZ_CORR_ERR_DET_WIDTH 1
+
+
+/*------------------------------------------------------------*/
+/*
+ * PCR_CZ_LNK_CAP_REG(32bit):
+ * PCIe link capabilities register
+ */
+#define PCR_CZ_LNK_CAP_REG 0x0000007c
+/* sienaa0=pci_f0_config */
+/*
+ * PCR_AB_LNK_CAP_REG(32bit):
+ * PCIe link capabilities register
+ */
+#define PCR_AB_LNK_CAP_REG 0x0000006c
+/* falcona0,falconb0=pci_f0_config */
+
+#define PCRF_AZ_PORT_NUM_LBN 24
+#define PCRF_AZ_PORT_NUM_WIDTH 8
+#define PCRF_CZ_LINK_BWDITH_NOTIF_CAP_LBN 21
+#define PCRF_CZ_LINK_BWDITH_NOTIF_CAP_WIDTH 1
+#define PCRF_CZ_DATA_LINK_ACTIVE_RPT_CAP_LBN 20
+#define PCRF_CZ_DATA_LINK_ACTIVE_RPT_CAP_WIDTH 1
+#define PCRF_CZ_SURPISE_DOWN_RPT_CAP_LBN 19
+#define PCRF_CZ_SURPISE_DOWN_RPT_CAP_WIDTH 1
+#define PCRF_CZ_CLOCK_PWR_MNGMNT_CAP_LBN 18
+#define PCRF_CZ_CLOCK_PWR_MNGMNT_CAP_WIDTH 1
+#define PCRF_AZ_DEF_L1_EXIT_LAT_LBN 15
+#define PCRF_AZ_DEF_L1_EXIT_LAT_WIDTH 3
+#define PCRF_AZ_DEF_L0_EXIT_LATPORT_NUM_LBN 12
+#define PCRF_AZ_DEF_L0_EXIT_LATPORT_NUM_WIDTH 3
+#define PCRF_AZ_AS_LNK_PM_SUPT_LBN 10
+#define PCRF_AZ_AS_LNK_PM_SUPT_WIDTH 2
+#define PCRF_AZ_MAX_LNK_WIDTH_LBN 4
+#define PCRF_AZ_MAX_LNK_WIDTH_WIDTH 6
+#define PCRF_AZ_MAX_LNK_SP_LBN 0
+#define PCRF_AZ_MAX_LNK_SP_WIDTH 4
+
+
+/*------------------------------------------------------------*/
+/*
+ * PCR_CZ_DEV_CTL2_REG(16bit):
+ * PCIe Device Control 2
+ */
+#define PCR_CZ_DEV_CTL2_REG 0x00000098
+/* sienaa0=pci_f0_config */
+
+#define PCRF_CZ_CMPL_TIMEOUT_DIS_CTL_LBN 4
+#define PCRF_CZ_CMPL_TIMEOUT_DIS_CTL_WIDTH 1
+#define PCRF_CZ_CMPL_TIMEOUT_CTL_LBN 0
+#define PCRF_CZ_CMPL_TIMEOUT_CTL_WIDTH 4
+
+
+/*------------------------------------------------------------*/
+/*
+ * PCR_CZ_LNK_STAT2_REG(16bit):
+ * PCIe Link Status 2
+ */
+#define PCR_CZ_LNK_STAT2_REG 0x000000a2
+/* sienaa0=pci_f0_config */
+
+#define PCRF_CZ_CURRENT_DEEMPH_LBN 0
+#define PCRF_CZ_CURRENT_DEEMPH_WIDTH 1
+
+
+/*------------------------------------------------------------*/
+/*
+ * PCR_CZ_MSIX_NXT_PTR_REG(8bit):
+ * MSIX Capability Next Capability Ptr
+ */
+#define PCR_CZ_MSIX_NXT_PTR_REG 0x000000b1
+/* sienaa0=pci_f0_config */
+/*
+ * PCR_BB_MSIX_NXT_PTR_REG(8bit):
+ * MSIX Capability Next Capability Ptr
+ */
+#define PCR_BB_MSIX_NXT_PTR_REG 0x00000091
+/* falconb0=pci_f0_config */
+
+#define PCRF_BZ_MSIX_NXT_PTR_LBN 0
+#define PCRF_BZ_MSIX_NXT_PTR_WIDTH 8
+
+
+/*------------------------------------------------------------*/
+/*
+ * PCR_CZ_MSIX_CTL_REG(16bit):
+ * MSIX control register
+ */
+#define PCR_CZ_MSIX_CTL_REG 0x000000b2
+/* sienaa0=pci_f0_config */
+/*
+ * PCR_BB_MSIX_CTL_REG(16bit):
+ * MSIX control register
+ */
+#define PCR_BB_MSIX_CTL_REG 0x00000092
+/* falconb0=pci_f0_config */
+
+#define PCRF_BZ_MSIX_EN_LBN 15
+#define PCRF_BZ_MSIX_EN_WIDTH 1
+#define PCRF_BZ_MSIX_FUNC_MASK_LBN 14
+#define PCRF_BZ_MSIX_FUNC_MASK_WIDTH 1
+#define PCRF_BZ_MSIX_TBL_SIZE_LBN 0
+#define PCRF_BZ_MSIX_TBL_SIZE_WIDTH 11
+
+
+/*------------------------------------------------------------*/
+/*
+ * PCR_AZ_AER_UNCORR_ERR_SEV_REG(32bit):
+ * AER Uncorrectable error severity register
+ */
+#define PCR_AZ_AER_UNCORR_ERR_SEV_REG 0x0000010c
+/* sienaa0=pci_f0_config,falcona0,falconb0=pci_f0_config */
+
+#define PCRF_AZ_UNSUPT_REQ_ERR_SEV_LBN 20
+#define PCRF_AZ_UNSUPT_REQ_ERR_SEV_WIDTH 1
+#define PCRF_AZ_ECRC_ERR_SEV_LBN 19
+#define PCRF_AZ_ECRC_ERR_SEV_WIDTH 1
+#define PCRF_AZ_MALF_TLP_SEV_LBN 18
+#define PCRF_AZ_MALF_TLP_SEV_WIDTH 1
+#define PCRF_AZ_RX_OVF_SEV_LBN 17
+#define PCRF_AZ_RX_OVF_SEV_WIDTH 1
+#define PCRF_AZ_UNEXP_COMP_SEV_LBN 16
+#define PCRF_AZ_UNEXP_COMP_SEV_WIDTH 1
+#define PCRF_AZ_COMP_ABRT_SEV_LBN 15
+#define PCRF_AZ_COMP_ABRT_SEV_WIDTH 1
+#define PCRF_AZ_COMP_TIMEOUT_SEV_LBN 14
+#define PCRF_AZ_COMP_TIMEOUT_SEV_WIDTH 1
+#define PCRF_AZ_FC_PROTO_ERR_SEV_LBN 13
+#define PCRF_AZ_FC_PROTO_ERR_SEV_WIDTH 1
+#define PCRF_AZ_PSON_TLP_SEV_LBN 12
+#define PCRF_AZ_PSON_TLP_SEV_WIDTH 1
+#define PCRF_AZ_DL_PROTO_ERR_SEV_LBN 4
+#define PCRF_AZ_DL_PROTO_ERR_SEV_WIDTH 1
+#define PCRF_AB_TRAIN_ERR_SEV_LBN 0
+#define PCRF_AB_TRAIN_ERR_SEV_WIDTH 1
+
+
+/*------------------------------------------------------------*/
+/*
+ * PCR_AZ_AER_CORR_ERR_STAT_REG(32bit):
+ * AER Correctable error status register
+ */
+#define PCR_AZ_AER_CORR_ERR_STAT_REG 0x00000110
+/* sienaa0=pci_f0_config,falcona0,falconb0=pci_f0_config */
+
+#define PCRF_CZ_ADVSY_NON_FATAL_STAT_LBN 13
+#define PCRF_CZ_ADVSY_NON_FATAL_STAT_WIDTH 1
+#define PCRF_AZ_RPLY_TMR_TOUT_STAT_LBN 12
+#define PCRF_AZ_RPLY_TMR_TOUT_STAT_WIDTH 1
+#define PCRF_AZ_RPLAY_NUM_RO_STAT_LBN 8
+#define PCRF_AZ_RPLAY_NUM_RO_STAT_WIDTH 1
+#define PCRF_AZ_BAD_DLLP_STAT_LBN 7
+#define PCRF_AZ_BAD_DLLP_STAT_WIDTH 1
+#define PCRF_AZ_BAD_TLP_STAT_LBN 6
+#define PCRF_AZ_BAD_TLP_STAT_WIDTH 1
+#define PCRF_AZ_RX_ERR_STAT_LBN 0
+#define PCRF_AZ_RX_ERR_STAT_WIDTH 1
+
+
+/*------------------------------------------------------------*/
+/*
+ * PCR_CZ_DEVSN_DWORD1_REG(32bit):
+ * Device serial number DWORD0
+ */
+#define PCR_CZ_DEVSN_DWORD1_REG 0x00000148
+/* sienaa0=pci_f0_config */
+
+#define PCRF_CZ_DEVSN_DWORD1_LBN 0
+#define PCRF_CZ_DEVSN_DWORD1_WIDTH 32
+
+
+/*------------------------------------------------------------*/
+/*
+ * PCR_CZ_ARI_CTL_REG(16bit):
+ * ARI Control
+ */
+#define PCR_CZ_ARI_CTL_REG 0x00000156
+/* sienaa0=pci_f0_config */
+
+#define PCRF_CZ_ARI_FN_GRP_LBN 4
+#define PCRF_CZ_ARI_FN_GRP_WIDTH 3
+#define PCRF_CZ_ARI_ACS_FNGRP_EN_LBN 1
+#define PCRF_CZ_ARI_ACS_FNGRP_EN_WIDTH 1
+#define PCRF_CZ_ARI_MFVC_FNGRP_EN_LBN 0
+#define PCRF_CZ_ARI_MFVC_FNGRP_EN_WIDTH 1
+
+
+/*------------------------------------------------------------*/
+/*
+ * PCR_CZ_SRIOV_CAP_HDR_REG(32bit):
+ * SRIOV capability header register
+ */
+#define PCR_CZ_SRIOV_CAP_HDR_REG 0x00000160
+/* sienaa0=pci_f0_config */
+
+#define PCRF_CZ_SRIOVCAPHDR_NXT_PTR_LBN 20
+#define PCRF_CZ_SRIOVCAPHDR_NXT_PTR_WIDTH 12
+#define PCRF_CZ_SRIOVCAPHDR_VER_LBN 16
+#define PCRF_CZ_SRIOVCAPHDR_VER_WIDTH 4
+#define PCRF_CZ_SRIOVCAPHDR_ID_LBN 0
+#define PCRF_CZ_SRIOVCAPHDR_ID_WIDTH 16
+
+
+/*------------------------------------------------------------*/
+/*
+ * PCR_CZ_SRIOV_INITIALVFS_REG(16bit):
+ * SRIOV Initial VFs
+ */
+#define PCR_CZ_SRIOV_INITIALVFS_REG 0x0000016c
+/* sienaa0=pci_f0_config */
+
+#define PCRF_CZ_VF_INITIALVFS_LBN 0
+#define PCRF_CZ_VF_INITIALVFS_WIDTH 16
+
+
+/*------------------------------------------------------------*/
+/*
+ * PCR_CZ_SRIOV_FN_DPND_LNK_REG(16bit):
+ * SRIOV Function dependency link
+ */
+#define PCR_CZ_SRIOV_FN_DPND_LNK_REG 0x00000172
+/* sienaa0=pci_f0_config */
+
+#define PCRF_CZ_SRIOV_FN_DPND_LNK_LBN 0
+#define PCRF_CZ_SRIOV_FN_DPND_LNK_WIDTH 8
+
+
+/*------------------------------------------------------------*/
+/*
+ * PCR_CZ_SRIOV_1STVF_OFFSET_REG(16bit):
+ * SRIOV First VF Offset
+ */
+#define PCR_CZ_SRIOV_1STVF_OFFSET_REG 0x00000174
+/* sienaa0=pci_f0_config */
+
+#define PCRF_CZ_VF_1STVF_OFFSET_LBN 0
+#define PCRF_CZ_VF_1STVF_OFFSET_WIDTH 16
+
+
+/*------------------------------------------------------------*/
+/*
+ * PCR_AZ_CMD_REG(16bit):
+ * Command register
+ */
+#define PCR_AZ_CMD_REG 0x00000004
+/* falcona0,falconb0=pci_f0_config,sienaa0=pci_f0_config */
+
+#define PCRF_AZ_INTX_DIS_LBN 10
+#define PCRF_AZ_INTX_DIS_WIDTH 1
+#define PCRF_AZ_FB2B_EN_LBN 9
+#define PCRF_AZ_FB2B_EN_WIDTH 1
+#define PCRF_AZ_SERR_EN_LBN 8
+#define PCRF_AZ_SERR_EN_WIDTH 1
+#define PCRF_AZ_IDSEL_CTL_LBN 7
+#define PCRF_AZ_IDSEL_CTL_WIDTH 1
+#define PCRF_AZ_PERR_EN_LBN 6
+#define PCRF_AZ_PERR_EN_WIDTH 1
+#define PCRF_AZ_VGA_PAL_SNP_LBN 5
+#define PCRF_AZ_VGA_PAL_SNP_WIDTH 1
+#define PCRF_AZ_MWI_EN_LBN 4
+#define PCRF_AZ_MWI_EN_WIDTH 1
+#define PCRF_AZ_SPEC_CYC_LBN 3
+#define PCRF_AZ_SPEC_CYC_WIDTH 1
+#define PCRF_AZ_MST_EN_LBN 2
+#define PCRF_AZ_MST_EN_WIDTH 1
+#define PCRF_AZ_MEM_EN_LBN 1
+#define PCRF_AZ_MEM_EN_WIDTH 1
+#define PCRF_AZ_IO_EN_LBN 0
+#define PCRF_AZ_IO_EN_WIDTH 1
+
+
+/*------------------------------------------------------------*/
+/*
+ * PCR_AB_VPD_CAP_DATA_REG(32bit):
+ * documentation to be written for sum_PC_VPD_CAP_DATA_REG
+ */
+#define PCR_AB_VPD_CAP_DATA_REG 0x000000b4
+/* falcona0,falconb0=pci_f0_config */
+/*
+ * PCR_CZ_VPD_CAP_DATA_REG(32bit):
+ * documentation to be written for sum_PC_VPD_CAP_DATA_REG
+ */
+#define PCR_CZ_VPD_CAP_DATA_REG 0x000000d4
+/* sienaa0=pci_f0_config */
+
+#define PCRF_AZ_VPD_DATA_LBN 0
+#define PCRF_AZ_VPD_DATA_WIDTH 32
+
+
+/*------------------------------------------------------------*/
+/*
+ * PCR_AZ_BAR2_HI_REG(32bit):
+ * Primary function base address register 2 high bits
+ */
+#define PCR_AZ_BAR2_HI_REG 0x0000001c
+/* sienaa0=pci_f0_config,falcona0,falconb0=pci_f0_config */
+
+#define PCRF_AZ_BAR2_HI_LBN 0
+#define PCRF_AZ_BAR2_HI_WIDTH 32
+
+
+/*------------------------------------------------------------*/
+/*
+ * PCR_AZ_SS_VEND_ID_REG(16bit):
+ * Sub-system vendor ID register
+ */
+#define PCR_AZ_SS_VEND_ID_REG 0x0000002c
+/* sienaa0=pci_f0_config,falcona0,falconb0=pci_f0_config */
+
+#define PCRF_AZ_SS_VEND_ID_LBN 0
+#define PCRF_AZ_SS_VEND_ID_WIDTH 16
+
+
+/*------------------------------------------------------------*/
+/*
+ * PCR_AZ_AER_CAP_HDR_REG(32bit):
+ * AER capability header register
+ */
+#define PCR_AZ_AER_CAP_HDR_REG 0x00000100
+/* sienaa0=pci_f0_config,falcona0,falconb0=pci_f0_config */
+
+#define PCRF_AZ_AERCAPHDR_NXT_PTR_LBN 20
+#define PCRF_AZ_AERCAPHDR_NXT_PTR_WIDTH 12
+#define PCRF_AZ_AERCAPHDR_VER_LBN 16
+#define PCRF_AZ_AERCAPHDR_VER_WIDTH 4
+#define PCRF_AZ_AERCAPHDR_ID_LBN 0
+#define PCRF_AZ_AERCAPHDR_ID_WIDTH 16
+
+
+/*------------------------------------------------------------*/
+/*
+ * PCR_AZ_AER_HDR_LOG_REG(128bit):
+ * AER Header log register
+ */
+#define PCR_AZ_AER_HDR_LOG_REG 0x0000011c
+/* sienaa0=pci_f0_config,falcona0,falconb0=pci_f0_config */
+
+#define PCRF_AZ_HDR_LOG_LBN 0
+#define PCRF_AZ_HDR_LOG_WIDTH 128
+
+
+/*------------------------------------------------------------*/
+/*
+ * PCR_CZ_SRIOV_VFSTRIDE_REG(16bit):
+ * SRIOV VF Stride
+ */
+#define PCR_CZ_SRIOV_VFSTRIDE_REG 0x00000176
+/* sienaa0=pci_f0_config */
+
+#define PCRF_CZ_VF_VFSTRIDE_LBN 0
+#define PCRF_CZ_VF_VFSTRIDE_WIDTH 16
+
+
+/*------------------------------------------------------------*/
+/*
+ * PCR_CZ_SRIOV_DEVID_REG(16bit):
+ * SRIOV VF Device ID
+ */
+#define PCR_CZ_SRIOV_DEVID_REG 0x0000017a
+/* sienaa0=pci_f0_config */
+
+#define PCRF_CZ_VF_DEVID_LBN 0
+#define PCRF_CZ_VF_DEVID_WIDTH 16
+
+
+/*------------------------------------------------------------*/
+/*
+ * PCR_CZ_SRIOV_SYS_PAGESZ_REG(32bit):
+ * SRIOV System Page Size
+ */
+#define PCR_CZ_SRIOV_SYS_PAGESZ_REG 0x00000180
+/* sienaa0=pci_f0_config */
+
+#define PCRF_CZ_VF_SYS_PAGESZ_LBN 0
+#define PCRF_CZ_VF_SYS_PAGESZ_WIDTH 16
+
+
+/*------------------------------------------------------------*/
+/*
+ * PCR_CZ_SRIOV_MIBR_SARRAY_OFFSET_REG(32bit):
+ * SRIOV VF Migration State Array Offset
+ */
+#define PCR_CZ_SRIOV_MIBR_SARRAY_OFFSET_REG 0x0000019c
+/* sienaa0=pci_f0_config */
+
+#define PCRF_CZ_VF_MIGR_OFFSET_LBN 3
+#define PCRF_CZ_VF_MIGR_OFFSET_WIDTH 29
+#define PCRF_CZ_VF_MIGR_BIR_LBN 0
+#define PCRF_CZ_VF_MIGR_BIR_WIDTH 3
+
+
+/*------------------------------------------------------------*/
+/*
+ * PCR_AZ_ACK_FREQ_REG(32bit):
+ * ACK frequency register
+ */
+#define PCR_AZ_ACK_FREQ_REG 0x0000070c
+/* sienaa0=pci_f0_config,falcona0,falconb0=pci_f0_config */
+
+#define PCRF_CZ_ALLOW_L1_WITHOUT_L0S_LBN 30
+#define PCRF_CZ_ALLOW_L1_WITHOUT_L0S_WIDTH 1
+#define PCRF_AZ_L1_ENTR_LAT_LBN 27
+#define PCRF_AZ_L1_ENTR_LAT_WIDTH 3
+#define PCRF_AZ_L0_ENTR_LAT_LBN 24
+#define PCRF_AZ_L0_ENTR_LAT_WIDTH 3
+#define PCRF_CZ_COMM_NFTS_LBN 16
+#define PCRF_CZ_COMM_NFTS_WIDTH 8
+#define PCRF_AB_ACK_FREQ_REG_RSVD0_LBN 16
+#define PCRF_AB_ACK_FREQ_REG_RSVD0_WIDTH 3
+#define PCRF_AZ_MAX_FTS_LBN 8
+#define PCRF_AZ_MAX_FTS_WIDTH 8
+#define PCRF_AZ_ACK_FREQ_LBN 0
+#define PCRF_AZ_ACK_FREQ_WIDTH 8
+
+
+/*------------------------------------------------------------*/
+/*
+ * PCR_AZ_DEBUG0_REG(32bit):
+ * Debug register 0
+ */
+#define PCR_AZ_DEBUG0_REG 0x00000728
+/* sienaa0=pci_f0_config,falcona0,falconb0=pci_f0_config */
+
+#define PCRF_AZ_CDI03_LBN 24
+#define PCRF_AZ_CDI03_WIDTH 8
+#define PCRF_AZ_CDI0_LBN 0
+#define PCRF_AZ_CDI0_WIDTH 32
+#define PCRF_AZ_CDI02_LBN 16
+#define PCRF_AZ_CDI02_WIDTH 8
+#define PCRF_AZ_CDI01_LBN 8
+#define PCRF_AZ_CDI01_WIDTH 8
+#define PCRF_AZ_CDI00_LBN 0
+#define PCRF_AZ_CDI00_WIDTH 8
+
+
+/*------------------------------------------------------------*/
+/*
+ * PCR_CZ_VC_XMIT_ARB2_REG(32bit):
+ * VC Transmit Arbitration Register 2
+ */
+#define PCR_CZ_VC_XMIT_ARB2_REG 0x00000744
+/* sienaa0=pci_f0_config */
+
+
+
+/*------------------------------------------------------------*/
+/*
+ * PCR_AZ_CACHE_LSIZE_REG(8bit):
+ * Cache line size
+ */
+#define PCR_AZ_CACHE_LSIZE_REG 0x0000000c
+/* falcona0,falconb0=pci_f0_config,sienaa0=pci_f0_config */
+
+#define PCRF_AZ_CACHE_LSIZE_LBN 0
+#define PCRF_AZ_CACHE_LSIZE_WIDTH 8
+
+
+/*------------------------------------------------------------*/
+/*
+ * PCR_AZ_PM_CAP_ID_REG(8bit):
+ * Power management capability ID
+ */
+#define PCR_AZ_PM_CAP_ID_REG 0x00000040
+/* falcona0,falconb0=pci_f0_config,sienaa0=pci_f0_config */
+
+#define PCRF_AZ_PM_CAP_ID_LBN 0
+#define PCRF_AZ_PM_CAP_ID_WIDTH 8
+
+
+/*------------------------------------------------------------*/
+/*
+ * PCR_AZ_MSI_DAT_REG(16bit):
+ * MSI data register
+ */
+#define PCR_AZ_MSI_DAT_REG 0x0000005c
+/* falcona0,falconb0=pci_f0_config,sienaa0=pci_f0_config */
+
+#define PCRF_AZ_MSI_DAT_LBN 0
+#define PCRF_AZ_MSI_DAT_WIDTH 16
+
+
+/*------------------------------------------------------------*/
+/*
+ * PCR_AZ_FORCE_LNK_REG(24bit):
+ * Port force link register
+ */
+#define PCR_AZ_FORCE_LNK_REG 0x00000708
+/* falcona0,falconb0=pci_f0_config,sienaa0=pci_f0_config */
+
+#define PCRF_AZ_LFS_LBN 16
+#define PCRF_AZ_LFS_WIDTH 6
+#define PCRF_AZ_FL_LBN 15
+#define PCRF_AZ_FL_WIDTH 1
+#define PCRF_AZ_LN_LBN 0
+#define PCRF_AZ_LN_WIDTH 8
+
+
+/*------------------------------------------------------------*/
+/*
+ * PCR_CZ_DEV_CAP2_REG(16bit):
+ * PCIe Device Capabilities 2
+ */
+#define PCR_CZ_DEV_CAP2_REG 0x00000094
+/* sienaa0=pci_f0_config */
+
+#define PCRF_CZ_CMPL_TIMEOUT_DIS_LBN 4
+#define PCRF_CZ_CMPL_TIMEOUT_DIS_WIDTH 1
+#define PCRF_CZ_CMPL_TIMEOUT_LBN 0
+#define PCRF_CZ_CMPL_TIMEOUT_WIDTH 4
+#define PCFE_CZ_CMPL_TIMEOUT_17000_TO_6400MS 14
+#define PCFE_CZ_CMPL_TIMEOUT_4000_TO_1300MS 13
+#define PCFE_CZ_CMPL_TIMEOUT_1000_TO_3500MS 10
+#define PCFE_CZ_CMPL_TIMEOUT_260_TO_900MS 9
+#define PCFE_CZ_CMPL_TIMEOUT_65_TO_210MS 6
+#define PCFE_CZ_CMPL_TIMEOUT_16_TO_55MS 5
+#define PCFE_CZ_CMPL_TIMEOUT_1_TO_10MS 2
+#define PCFE_CZ_CMPL_TIMEOUT_50_TO_100US 1
+#define PCFE_CZ_CMPL_TIMEOUT_DEFAULT 0
+
+
+/*------------------------------------------------------------*/
+/*
+ * PCR_AZ_AER_CAP_CTL_REG(32bit):
+ * AER capability and control register
+ */
+#define PCR_AZ_AER_CAP_CTL_REG 0x00000118
+/* sienaa0=pci_f0_config,falcona0,falconb0=pci_f0_config */
+
+#define PCRF_AZ_ECRC_CHK_EN_LBN 8
+#define PCRF_AZ_ECRC_CHK_EN_WIDTH 1
+#define PCRF_AZ_ECRC_CHK_CAP_LBN 7
+#define PCRF_AZ_ECRC_CHK_CAP_WIDTH 1
+#define PCRF_AZ_ECRC_GEN_EN_LBN 6
+#define PCRF_AZ_ECRC_GEN_EN_WIDTH 1
+#define PCRF_AZ_ECRC_GEN_CAP_LBN 5
+#define PCRF_AZ_ECRC_GEN_CAP_WIDTH 1
+#define PCRF_AZ_1ST_ERR_PTR_LBN 0
+#define PCRF_AZ_1ST_ERR_PTR_WIDTH 5
+
+
+/*------------------------------------------------------------*/
+/*
+ * PCR_CZ_SRIOV_BAR0_REG(32bit):
+ * SRIOV VF Bar0
+ */
+#define PCR_CZ_SRIOV_BAR0_REG 0x00000184
+/* sienaa0=pci_f0_config */
+
+#define PCRF_CZ_VF_BAR_ADDRESS_LBN 0
+#define PCRF_CZ_VF_BAR_ADDRESS_WIDTH 32
+
+
+/*------------------------------------------------------------*/
+/*
+ * PCR_CZ_SRIOV_BAR1_REG(32bit):
+ * SRIOV Bar1
+ */
+#define PCR_CZ_SRIOV_BAR1_REG 0x00000188
+/* sienaa0=pci_f0_config */
+
+/* defined as PCRF_CZ_VF_BAR_ADDRESS_LBN 0; access=rw reset=0x0 */
+/* defined as PCRF_CZ_VF_BAR_ADDRESS_WIDTH 32 */
+
+
+/*------------------------------------------------------------*/
+/*
+ * PCR_AZ_ACK_LAT_TMR_REG(32bit):
+ * ACK latency timer & replay timer register
+ */
+#define PCR_AZ_ACK_LAT_TMR_REG 0x00000700
+/* sienaa0=pci_f0_config,falcona0,falconb0=pci_f0_config */
+
+#define PCRF_AZ_RT_LBN 16
+#define PCRF_AZ_RT_WIDTH 16
+#define PCRF_AZ_ALT_LBN 0
+#define PCRF_AZ_ALT_WIDTH 16
+
+
+/*------------------------------------------------------------*/
+/*
+ * PCR_CZ_SYM_TMR_FLT_MSK_REG(16bit):
+ * Symbol timer and Filter Mask Register
+ */
+#define PCR_CZ_SYM_TMR_FLT_MSK_REG 0x0000071c
+/* sienaa0=pci_f0_config */
+
+#define PCRF_CZ_ET_LBN 11
+#define PCRF_CZ_ET_WIDTH 4
+#define PCRF_CZ_SI1_LBN 8
+#define PCRF_CZ_SI1_WIDTH 3
+#define PCRF_CZ_SI0_LBN 0
+#define PCRF_CZ_SI0_WIDTH 8
+
+
+/*------------------------------------------------------------*/
+/*
+ * PCR_CZ_FLT_MSK_REG(32bit):
+ * Filter Mask Register 2
+ */
+#define PCR_CZ_FLT_MSK_REG 0x00000720
+/* sienaa0=pci_f0_config */
+
+
+
+/*------------------------------------------------------------*/
+/*
+ * PCR_AZ_XCFCC_STAT_REG(24bit):
+ * documentation to be written for sum_PC_XCFCC_STAT_REG
+ */
+#define PCR_AZ_XCFCC_STAT_REG 0x00000738
+/* sienaa0=pci_f0_config,falcona0,falconb0=pci_f0_config */
+
+#define PCRF_AZ_XCDC_LBN 12
+#define PCRF_AZ_XCDC_WIDTH 8
+#define PCRF_AZ_XCHC_LBN 0
+#define PCRF_AZ_XCHC_WIDTH 12
+
+
+/*------------------------------------------------------------*/
+/*
+ * PCR_AZ_MSI_ADR_LO_REG(32bit):
+ * MSI low 32 bits address register
+ */
+#define PCR_AZ_MSI_ADR_LO_REG 0x00000054
+/* falcona0,falconb0=pci_f0_config,sienaa0=pci_f0_config */
+
+#define PCRF_AZ_MSI_ADR_LO_LBN 2
+#define PCRF_AZ_MSI_ADR_LO_WIDTH 30
+
+
+/*------------------------------------------------------------*/
+/*
+ * PCR_AB_SLOT_CAP_REG(32bit):
+ * PCIe slot capabilities register
+ */
+#define PCR_AB_SLOT_CAP_REG 0x00000074
+/* falcona0,falconb0=pci_f0_config */
+
+#define PCRF_AB_SLOT_NUM_LBN 19
+#define PCRF_AB_SLOT_NUM_WIDTH 13
+#define PCRF_AB_SLOT_PWR_LIM_SCL_LBN 15
+#define PCRF_AB_SLOT_PWR_LIM_SCL_WIDTH 2
+#define PCRF_AB_SLOT_PWR_LIM_VAL_LBN 7
+#define PCRF_AB_SLOT_PWR_LIM_VAL_WIDTH 8
+#define PCRF_AB_SLOT_HP_CAP_LBN 6
+#define PCRF_AB_SLOT_HP_CAP_WIDTH 1
+#define PCRF_AB_SLOT_HP_SURP_LBN 5
+#define PCRF_AB_SLOT_HP_SURP_WIDTH 1
+#define PCRF_AB_SLOT_PWR_IND_PRST_LBN 4
+#define PCRF_AB_SLOT_PWR_IND_PRST_WIDTH 1
+#define PCRF_AB_SLOT_ATTN_IND_PRST_LBN 3
+#define PCRF_AB_SLOT_ATTN_IND_PRST_WIDTH 1
+#define PCRF_AB_SLOT_MRL_SENS_PRST_LBN 2
+#define PCRF_AB_SLOT_MRL_SENS_PRST_WIDTH 1
+#define PCRF_AB_SLOT_PWR_CTL_PRST_LBN 1
+#define PCRF_AB_SLOT_PWR_CTL_PRST_WIDTH 1
+#define PCRF_AB_SLOT_ATTN_BUT_PRST_LBN 0
+#define PCRF_AB_SLOT_ATTN_BUT_PRST_WIDTH 1
+
+
+/*------------------------------------------------------------*/
+/*
+ * PCR_AZ_BAR0_REG(32bit):
+ * Primary function base address register 0
+ */
+#define PCR_AZ_BAR0_REG 0x00000010
+/* sienaa0=pci_f0_config,falcona0,falconb0=pci_f0_config */
+
+#define PCRF_AZ_BAR0_LBN 4
+#define PCRF_AZ_BAR0_WIDTH 28
+#define PCRF_AZ_BAR0_PREF_LBN 3
+#define PCRF_AZ_BAR0_PREF_WIDTH 1
+#define PCRF_AZ_BAR0_TYPE_LBN 1
+#define PCRF_AZ_BAR0_TYPE_WIDTH 2
+#define PCRF_AZ_BAR0_IOM_LBN 0
+#define PCRF_AZ_BAR0_IOM_WIDTH 1
+
+
+/*------------------------------------------------------------*/
+/*
+ * PCR_CZ_PCIE_CAP_REG(16bit):
+ * PCIe capability register
+ */
+#define PCR_CZ_PCIE_CAP_REG 0x00000072
+/* sienaa0=pci_f0_config */
+/*
+ * PCR_AB_PCIE_CAP_REG(16bit):
+ * PCIe capability register
+ */
+#define PCR_AB_PCIE_CAP_REG 0x00000062
+/* falcona0,falconb0=pci_f0_config */
+
+#define PCRF_AZ_PCIE_INT_MSG_NUM_LBN 9
+#define PCRF_AZ_PCIE_INT_MSG_NUM_WIDTH 5
+#define PCRF_AZ_PCIE_SLOT_IMP_LBN 8
+#define PCRF_AZ_PCIE_SLOT_IMP_WIDTH 1
+#define PCRF_AZ_PCIE_DEV_PORT_TYPE_LBN 4
+#define PCRF_AZ_PCIE_DEV_PORT_TYPE_WIDTH 4
+#define PCRF_AZ_PCIE_CAP_VER_LBN 0
+#define PCRF_AZ_PCIE_CAP_VER_WIDTH 4
+
+
+/*------------------------------------------------------------*/
+/*
+ * PCR_CZ_LNK_CTL2_REG(16bit):
+ * PCIe Link Control 2
+ */
+#define PCR_CZ_LNK_CTL2_REG 0x000000a0
+/* sienaa0=pci_f0_config */
+
+#define PCRF_CZ_POLLING_DEEMPH_LVL_LBN 12
+#define PCRF_CZ_POLLING_DEEMPH_LVL_WIDTH 1
+#define PCRF_CZ_COMPLIANCE_SOS_CTL_LBN 11
+#define PCRF_CZ_COMPLIANCE_SOS_CTL_WIDTH 1
+#define PCRF_CZ_ENTER_MODIFIED_COMPLIANCE_CTL_LBN 10
+#define PCRF_CZ_ENTER_MODIFIED_COMPLIANCE_CTL_WIDTH 1
+#define PCRF_CZ_TRANSMIT_MARGIN_LBN 7
+#define PCRF_CZ_TRANSMIT_MARGIN_WIDTH 3
+#define PCRF_CZ_SELECT_DEEMPH_LBN 6
+#define PCRF_CZ_SELECT_DEEMPH_WIDTH 1
+#define PCRF_CZ_HW_AUTONOMOUS_SPEED_DIS_LBN 5
+#define PCRF_CZ_HW_AUTONOMOUS_SPEED_DIS_WIDTH 1
+#define PCRF_CZ_ENTER_COMPLIANCE_CTL_LBN 4
+#define PCRF_CZ_ENTER_COMPLIANCE_CTL_WIDTH 1
+#define PCRF_CZ_TGT_LNK_SPEED_CTL_LBN 0
+#define PCRF_CZ_TGT_LNK_SPEED_CTL_WIDTH 4
+
+
+/*------------------------------------------------------------*/
+/*
+ * PCR_CZ_MSIX_PBA_BASE_REG(32bit):
+ * MSIX Capability PBA Base
+ */
+#define PCR_CZ_MSIX_PBA_BASE_REG 0x000000b8
+/* sienaa0=pci_f0_config */
+/*
+ * PCR_BB_MSIX_PBA_BASE_REG(32bit):
+ * MSIX Capability PBA Base
+ */
+#define PCR_BB_MSIX_PBA_BASE_REG 0x00000098
+/* falconb0=pci_f0_config */
+
+#define PCRF_BZ_MSIX_PBA_OFF_LBN 3
+#define PCRF_BZ_MSIX_PBA_OFF_WIDTH 29
+#define PCRF_BZ_MSIX_PBA_BIR_LBN 0
+#define PCRF_BZ_MSIX_PBA_BIR_WIDTH 3
+
+
+/*------------------------------------------------------------*/
+/*
+ * PCR_CZ_SRIOV_TOTALVFS_REG(10bit):
+ * SRIOV Total VFs
+ */
+#define PCR_CZ_SRIOV_TOTALVFS_REG 0x0000016e
+/* sienaa0=pci_f0_config */
+
+#define PCRF_CZ_VF_TOTALVFS_LBN 0
+#define PCRF_CZ_VF_TOTALVFS_WIDTH 16
+
+
+/*------------------------------------------------------------*/
+/*
+ * PCR_CZ_DEVSN_DWORD0_REG(32bit):
+ * Device serial number DWORD0
+ */
+#define PCR_CZ_DEVSN_DWORD0_REG 0x00000144
+/* sienaa0=pci_f0_config */
+
+#define PCRF_CZ_DEVSN_DWORD0_LBN 0
+#define PCRF_CZ_DEVSN_DWORD0_WIDTH 32
+
+
+/*------------------------------------------------------------*/
+/*
+ * PCR_CZ_SRIOV_CTL_REG(16bit):
+ * SRIOV Control
+ */
+#define PCR_CZ_SRIOV_CTL_REG 0x00000168
+/* sienaa0=pci_f0_config */
+
+#define PCRF_CZ_VF_ARI_CAP_HRCHY_LBN 4
+#define PCRF_CZ_VF_ARI_CAP_HRCHY_WIDTH 1
+#define PCRF_CZ_VF_MSE_LBN 3
+#define PCRF_CZ_VF_MSE_WIDTH 1
+#define PCRF_CZ_VF_MIGR_INT_EN_LBN 2
+#define PCRF_CZ_VF_MIGR_INT_EN_WIDTH 1
+#define PCRF_CZ_VF_MIGR_EN_LBN 1
+#define PCRF_CZ_VF_MIGR_EN_WIDTH 1
+#define PCRF_CZ_VF_EN_LBN 0
+#define PCRF_CZ_VF_EN_WIDTH 1
+
+
+/*------------------------------------------------------------*/
+/*
+ * PCR_CZ_SRIOV_NUMVFS_REG(16bit):
+ * SRIOV Number of VFs
+ */
+#define PCR_CZ_SRIOV_NUMVFS_REG 0x00000170
+/* sienaa0=pci_f0_config */
+
+#define PCRF_CZ_VF_NUMVFS_LBN 0
+#define PCRF_CZ_VF_NUMVFS_WIDTH 16
+
+
+/*------------------------------------------------------------*/
+/*
+ * PCR_CZ_SRIOV_SUP_PAGESZ_REG(16bit):
+ * SRIOV Supported Page Sizes
+ */
+#define PCR_CZ_SRIOV_SUP_PAGESZ_REG 0x0000017c
+/* sienaa0=pci_f0_config */
+
+#define PCRF_CZ_VF_SUP_PAGESZ_LBN 0
+#define PCRF_CZ_VF_SUP_PAGESZ_WIDTH 16
+
+
+/*------------------------------------------------------------*/
+/*
+ * PCR_CZ_SRIOV_BAR3_REG(32bit):
+ * SRIOV Bar3
+ */
+#define PCR_CZ_SRIOV_BAR3_REG 0x00000190
+/* sienaa0=pci_f0_config */
+
+/* defined as PCRF_CZ_VF_BAR_ADDRESS_LBN 0; access=rw reset=0x0 */
+/* defined as PCRF_CZ_VF_BAR_ADDRESS_WIDTH 32 */
+
+
+/*------------------------------------------------------------*/
+/*
+ * PCR_CZ_VC0_P_RQ_CTL_REG(32bit):
+ * VC0 Posted Receive Queue Control
+ */
+#define PCR_CZ_VC0_P_RQ_CTL_REG 0x00000748
+/* sienaa0=pci_f0_config */
+
+
+
+/*------------------------------------------------------------*/
+/*
+ * PCR_AZ_PM_CAP_REG(16bit):
+ * Power management capabilities register
+ */
+#define PCR_AZ_PM_CAP_REG 0x00000042
+/* falcona0,falconb0=pci_f0_config,sienaa0=pci_f0_config */
+
+#define PCRF_AZ_PM_PME_SUPT_LBN 11
+#define PCRF_AZ_PM_PME_SUPT_WIDTH 5
+#define PCRF_AZ_PM_D2_SUPT_LBN 10
+#define PCRF_AZ_PM_D2_SUPT_WIDTH 1
+#define PCRF_AZ_PM_D1_SUPT_LBN 9
+#define PCRF_AZ_PM_D1_SUPT_WIDTH 1
+#define PCRF_AZ_PM_AUX_CURR_LBN 6
+#define PCRF_AZ_PM_AUX_CURR_WIDTH 3
+#define PCRF_AZ_PM_DSI_LBN 5
+#define PCRF_AZ_PM_DSI_WIDTH 1
+#define PCRF_AZ_PM_PME_CLK_LBN 3
+#define PCRF_AZ_PM_PME_CLK_WIDTH 1
+#define PCRF_AZ_PM_PME_VER_LBN 0
+#define PCRF_AZ_PM_PME_VER_WIDTH 3
+
+
+/*------------------------------------------------------------*/
+/*
+ * PCR_AB_LNK_CTL_REG(16bit):
+ * PCIe link control register
+ */
+#define PCR_AB_LNK_CTL_REG 0x00000070
+/* falcona0,falconb0=pci_f0_config */
+/*
+ * PCR_CZ_LNK_CTL_REG(16bit):
+ * PCIe link control register
+ */
+#define PCR_CZ_LNK_CTL_REG 0x00000080
+/* sienaa0=pci_f0_config */
+
+#define PCRF_AZ_EXT_SYNC_LBN 7
+#define PCRF_AZ_EXT_SYNC_WIDTH 1
+#define PCRF_AZ_COMM_CLK_CFG_LBN 6
+#define PCRF_AZ_COMM_CLK_CFG_WIDTH 1
+#define PCRF_AB_LNK_CTL_REG_RSVD0_LBN 5
+#define PCRF_AB_LNK_CTL_REG_RSVD0_WIDTH 1
+#define PCRF_CZ_LNK_RETRAIN_LBN 5
+#define PCRF_CZ_LNK_RETRAIN_WIDTH 1
+#define PCRF_AZ_LNK_DIS_LBN 4
+#define PCRF_AZ_LNK_DIS_WIDTH 1
+#define PCRF_AZ_RD_COM_BDRY_LBN 3
+#define PCRF_AZ_RD_COM_BDRY_WIDTH 1
+#define PCRF_AZ_ACT_ST_LNK_PM_CTL_LBN 0
+#define PCRF_AZ_ACT_ST_LNK_PM_CTL_WIDTH 2
+
+
+/*------------------------------------------------------------*/
+/*
+ * PCR_BB_MSIX_TBL_BASE_REG(32bit):
+ * MSIX Capability Vector Table Base
+ */
+#define PCR_BB_MSIX_TBL_BASE_REG 0x00000094
+/* falconb0=pci_f0_config */
+/*
+ * PCR_CZ_MSIX_TBL_BASE_REG(32bit):
+ * MSIX Capability Vector Table Base
+ */
+#define PCR_CZ_MSIX_TBL_BASE_REG 0x000000b4
+/* sienaa0=pci_f0_config */
+
+#define PCRF_BZ_MSIX_TBL_OFF_LBN 3
+#define PCRF_BZ_MSIX_TBL_OFF_WIDTH 29
+#define PCRF_BZ_MSIX_TBL_BIR_LBN 0
+#define PCRF_BZ_MSIX_TBL_BIR_WIDTH 3
+
+
+/*------------------------------------------------------------*/
+/*
+ * PCR_AZ_XPFCC_STAT_REG(24bit):
+ * documentation to be written for sum_PC_XPFCC_STAT_REG
+ */
+#define PCR_AZ_XPFCC_STAT_REG 0x00000730
+/* falcona0,falconb0=pci_f0_config,sienaa0=pci_f0_config */
+
+#define PCRF_AZ_XPDC_LBN 12
+#define PCRF_AZ_XPDC_WIDTH 8
+#define PCRF_AZ_XPHC_LBN 0
+#define PCRF_AZ_XPHC_WIDTH 12
+
+
+/*------------------------------------------------------------*/
+/*
+ * PCR_AZ_XNPFCC_STAT_REG(24bit):
+ * documentation to be written for sum_PC_XNPFCC_STAT_REG
+ */
+#define PCR_AZ_XNPFCC_STAT_REG 0x00000734
+/* falcona0,falconb0=pci_f0_config,sienaa0=pci_f0_config */
+
+#define PCRF_AZ_XNPDC_LBN 12
+#define PCRF_AZ_XNPDC_WIDTH 8
+#define PCRF_AZ_XNPHC_LBN 0
+#define PCRF_AZ_XNPHC_WIDTH 12
+
+
+/*------------------------------------------------------------*/
+/*
+ * PCR_CZ_MSIX_CAP_ID_REG(8bit):
+ * MSIX Capability ID
+ */
+#define PCR_CZ_MSIX_CAP_ID_REG 0x000000b0
+/* sienaa0=pci_f0_config */
+/*
+ * PCR_BB_MSIX_CAP_ID_REG(8bit):
+ * MSIX Capability ID
+ */
+#define PCR_BB_MSIX_CAP_ID_REG 0x00000090
+/* falconb0=pci_f0_config */
+
+#define PCRF_BZ_MSIX_CAP_ID_LBN 0
+#define PCRF_BZ_MSIX_CAP_ID_WIDTH 8
+
+
+/*------------------------------------------------------------*/
+/*
+ * PCR_CZ_DEVSN_CAP_HDR_REG(32bit):
+ * Device serial number capability header register
+ */
+#define PCR_CZ_DEVSN_CAP_HDR_REG 0x00000140
+/* sienaa0=pci_f0_config */
+
+#define PCRF_CZ_DEVSNCAPHDR_NXT_PTR_LBN 20
+#define PCRF_CZ_DEVSNCAPHDR_NXT_PTR_WIDTH 12
+#define PCRF_CZ_DEVSNCAPHDR_VER_LBN 16
+#define PCRF_CZ_DEVSNCAPHDR_VER_WIDTH 4
+#define PCRF_CZ_DEVSNCAPHDR_ID_LBN 0
+#define PCRF_CZ_DEVSNCAPHDR_ID_WIDTH 16
+
+
+/*------------------------------------------------------------*/
+/*
+ * PCR_CZ_ARI_CAP_HDR_REG(32bit):
+ * ARI capability header register
+ */
+#define PCR_CZ_ARI_CAP_HDR_REG 0x00000150
+/* sienaa0=pci_f0_config */
+
+#define PCRF_CZ_ARICAPHDR_NXT_PTR_LBN 20
+#define PCRF_CZ_ARICAPHDR_NXT_PTR_WIDTH 12
+#define PCRF_CZ_ARICAPHDR_VER_LBN 16
+#define PCRF_CZ_ARICAPHDR_VER_WIDTH 4
+#define PCRF_CZ_ARICAPHDR_ID_LBN 0
+#define PCRF_CZ_ARICAPHDR_ID_WIDTH 16
+
+
+/*------------------------------------------------------------*/
+/*
+ * PCR_CZ_SRIOV_BAR4_REG(32bit):
+ * SRIOV Bar4
+ */
+#define PCR_CZ_SRIOV_BAR4_REG 0x00000194
+/* sienaa0=pci_f0_config */
+
+/* defined as PCRF_CZ_VF_BAR_ADDRESS_LBN 0; access=rw reset=0x0 */
+/* defined as PCRF_CZ_VF_BAR_ADDRESS_WIDTH 32 */
+
+
+/*------------------------------------------------------------*/
+/*
+ * PCR_CZ_VC0_C_RQ_CTL_REG(32bit):
+ * VC0 Completion Receive Queue Control
+ */
+#define PCR_CZ_VC0_C_RQ_CTL_REG 0x00000750
+/* sienaa0=pci_f0_config */
+
+
+
+/*------------------------------------------------------------*/
+/*
+ * PCR_AZ_LN_SKEW_REG(32bit):
+ * Lane skew register
+ */
+#define PCR_AZ_LN_SKEW_REG 0x00000714
+/* falcona0,falconb0=pci_f0_config,sienaa0=pci_f0_config */
+
+#define PCRF_AZ_DIS_LBN 31
+#define PCRF_AZ_DIS_WIDTH 1
+#define PCRF_AB_RST_LBN 30
+#define PCRF_AB_RST_WIDTH 1
+#define PCRF_AZ_AD_LBN 25
+#define PCRF_AZ_AD_WIDTH 1
+#define PCRF_AZ_FCD_LBN 24
+#define PCRF_AZ_FCD_WIDTH 1
+#define PCRF_AZ_LS2_LBN 16
+#define PCRF_AZ_LS2_WIDTH 8
+#define PCRF_AZ_LS1_LBN 8
+#define PCRF_AZ_LS1_WIDTH 8
+#define PCRF_AZ_LS0_LBN 0
+#define PCRF_AZ_LS0_WIDTH 8
+
+
+/*------------------------------------------------------------*/
+/*
+ * PCR_CZ_SRIOV_CAP_REG(32bit):
+ * SRIOV Capabilities
+ */
+#define PCR_CZ_SRIOV_CAP_REG 0x00000164
+/* sienaa0=pci_f0_config */
+
+#define PCRF_CZ_VF_MIGR_INT_MSG_NUM_LBN 21
+#define PCRF_CZ_VF_MIGR_INT_MSG_NUM_WIDTH 11
+#define PCRF_CZ_VF_MIGR_CAP_LBN 0
+#define PCRF_CZ_VF_MIGR_CAP_WIDTH 1
+
+
+/*------------------------------------------------------------*/
+/*
+ * PCR_CZ_SRIOV_BAR5_REG(32bit):
+ * SRIOV Bar5
+ */
+#define PCR_CZ_SRIOV_BAR5_REG 0x00000198
+/* sienaa0=pci_f0_config */
+
+/* defined as PCRF_CZ_VF_BAR_ADDRESS_LBN 0; access=rw reset=0x0 */
+/* defined as PCRF_CZ_VF_BAR_ADDRESS_WIDTH 32 */
+
+
+/*------------------------------------------------------------*/
+/*
+ * PCR_AZ_DEBUG1_REG(32bit):
+ * Debug register 1
+ */
+#define PCR_AZ_DEBUG1_REG 0x0000072c
+/* sienaa0=pci_f0_config,falcona0,falconb0=pci_f0_config */
+
+#define PCRF_AZ_CDI13_LBN 24
+#define PCRF_AZ_CDI13_WIDTH 8
+#define PCRF_AZ_CDI1_LBN 0
+#define PCRF_AZ_CDI1_WIDTH 32
+#define PCRF_AZ_CDI12_LBN 16
+#define PCRF_AZ_CDI12_WIDTH 8
+#define PCRF_AZ_CDI11_LBN 8
+#define PCRF_AZ_CDI11_WIDTH 8
+#define PCRF_AZ_CDI10_LBN 0
+#define PCRF_AZ_CDI10_WIDTH 8
+
+
+/*------------------------------------------------------------*/
+/*
+ * PCR_CZ_PHY_STAT_REG(32bit):
+ * PHY status register
+ */
+#define PCR_CZ_PHY_STAT_REG 0x00000810
+/* sienaa0=pci_f0_config */
+/*
+ * PCR_AB_PHY_STAT_REG(8bit):
+ * PHY status register
+ */
+#define PCR_AB_PHY_STAT_REG 0x00000720
+/* falcona0,falconb0=pci_f0_config */
+
+#define PCRF_AZ_SSL_LBN 3
+#define PCRF_AZ_SSL_WIDTH 1
+#define PCRF_AZ_SSR_LBN 2
+#define PCRF_AZ_SSR_WIDTH 1
+#define PCRF_AZ_SSCL_LBN 1
+#define PCRF_AZ_SSCL_WIDTH 1
+#define PCRF_AZ_SSCD_LBN 0
+#define PCRF_AZ_SSCD_WIDTH 1
+
+
+/*------------------------------------------------------------*/
+/*
+ * PCR_CZ_GEN2_REG(32bit):
+ * Gen2 Register
+ */
+#define PCR_CZ_GEN2_REG 0x0000080c
+/* sienaa0=pci_f0_config */
+
+#define PCRF_CZ_SET_DE_EMPHASIS_LBN 20
+#define PCRF_CZ_SET_DE_EMPHASIS_WIDTH 1
+#define PCRF_CZ_CFG_TX_COMPLIANCE_LBN 19
+#define PCRF_CZ_CFG_TX_COMPLIANCE_WIDTH 1
+#define PCRF_CZ_CFG_TX_SWING_LBN 18
+#define PCRF_CZ_CFG_TX_SWING_WIDTH 1
+#define PCRF_CZ_DIR_SPEED_CHANGE_LBN 17
+#define PCRF_CZ_DIR_SPEED_CHANGE_WIDTH 1
+#define PCRF_CZ_LANE_ENABLE_LBN 8
+#define PCRF_CZ_LANE_ENABLE_WIDTH 9
+#define PCRF_CZ_NUM_FTS_LBN 0
+#define PCRF_CZ_NUM_FTS_WIDTH 8
+
+
+/*------------------------------------------------------------*/
+/*
+ * PCR_AZ_BAR2_LO_REG(32bit):
+ * Primary function base address register 2 low bits
+ */
+#define PCR_AZ_BAR2_LO_REG 0x00000018
+/* falcona0,falconb0=pci_f0_config,sienaa0=pci_f0_config */
+
+#define PCRF_AZ_BAR2_LO_LBN 4
+#define PCRF_AZ_BAR2_LO_WIDTH 28
+#define PCRF_AZ_BAR2_PREF_LBN 3
+#define PCRF_AZ_BAR2_PREF_WIDTH 1
+#define PCRF_AZ_BAR2_TYPE_LBN 1
+#define PCRF_AZ_BAR2_TYPE_WIDTH 2
+#define PCRF_AZ_BAR2_IOM_LBN 0
+#define PCRF_AZ_BAR2_IOM_WIDTH 1
+
+
+/*------------------------------------------------------------*/
+/*
+ * PCR_AZ_PM_NXT_PTR_REG(8bit):
+ * Power management next item pointer
+ */
+#define PCR_AZ_PM_NXT_PTR_REG 0x00000041
+/* falcona0,falconb0=pci_f0_config,sienaa0=pci_f0_config */
+
+#define PCRF_AZ_PM_NXT_PTR_LBN 0
+#define PCRF_AZ_PM_NXT_PTR_WIDTH 8
+
+
+/*------------------------------------------------------------*/
+/*
+ * PCR_AB_SLOT_CTL_REG(16bit):
+ * PCIe slot control register
+ */
+#define PCR_AB_SLOT_CTL_REG 0x00000078
+/* falcona0,falconb0=pci_f0_config */
+
+#define PCRF_AB_SLOT_PWR_CTLR_CTL_LBN 10
+#define PCRF_AB_SLOT_PWR_CTLR_CTL_WIDTH 1
+#define PCRF_AB_SLOT_PWR_IND_CTL_LBN 8
+#define PCRF_AB_SLOT_PWR_IND_CTL_WIDTH 2
+#define PCRF_AB_SLOT_ATT_IND_CTL_LBN 6
+#define PCRF_AB_SLOT_ATT_IND_CTL_WIDTH 2
+#define PCRF_AB_SLOT_HP_INT_EN_LBN 5
+#define PCRF_AB_SLOT_HP_INT_EN_WIDTH 1
+#define PCRF_AB_SLOT_CMD_COMP_INT_EN_LBN 4
+#define PCRF_AB_SLOT_CMD_COMP_INT_EN_WIDTH 1
+#define PCRF_AB_SLOT_PRES_DET_CHG_EN_LBN 3
+#define PCRF_AB_SLOT_PRES_DET_CHG_EN_WIDTH 1
+#define PCRF_AB_SLOT_MRL_SENS_CHG_EN_LBN 2
+#define PCRF_AB_SLOT_MRL_SENS_CHG_EN_WIDTH 1
+#define PCRF_AB_SLOT_PWR_FLTDET_EN_LBN 1
+#define PCRF_AB_SLOT_PWR_FLTDET_EN_WIDTH 1
+#define PCRF_AB_SLOT_ATTN_BUT_EN_LBN 0
+#define PCRF_AB_SLOT_ATTN_BUT_EN_WIDTH 1
+
+
+/*------------------------------------------------------------*/
+/*
+ * PCR_AB_VPD_CAP_ID_REG(8bit):
+ * VPD data register
+ */
+#define PCR_AB_VPD_CAP_ID_REG 0x000000b0
+/* falcona0,falconb0=pci_f0_config */
+
+#define PCRF_AB_VPD_CAP_ID_LBN 0
+#define PCRF_AB_VPD_CAP_ID_WIDTH 8
+
+
+/*------------------------------------------------------------*/
+/*
+ * PCR_AB_VPD_NXT_PTR_REG(8bit):
+ * VPD next item pointer
+ */
+#define PCR_AB_VPD_NXT_PTR_REG 0x000000b1
+/* falcona0,falconb0=pci_f0_config */
+
+#define PCRF_AB_VPD_NXT_PTR_LBN 0
+#define PCRF_AB_VPD_NXT_PTR_WIDTH 8
+
+
+/*------------------------------------------------------------*/
+/*
+ * PCR_AZ_AER_UNCORR_ERR_STAT_REG(32bit):
+ * AER Uncorrectable error status register
+ */
+#define PCR_AZ_AER_UNCORR_ERR_STAT_REG 0x00000104
+/* falcona0,falconb0=pci_f0_config,sienaa0=pci_f0_config */
+
+#define PCRF_AZ_UNSUPT_REQ_ERR_STAT_LBN 20
+#define PCRF_AZ_UNSUPT_REQ_ERR_STAT_WIDTH 1
+#define PCRF_AZ_ECRC_ERR_STAT_LBN 19
+#define PCRF_AZ_ECRC_ERR_STAT_WIDTH 1
+#define PCRF_AZ_MALF_TLP_STAT_LBN 18
+#define PCRF_AZ_MALF_TLP_STAT_WIDTH 1
+#define PCRF_AZ_RX_OVF_STAT_LBN 17
+#define PCRF_AZ_RX_OVF_STAT_WIDTH 1
+#define PCRF_AZ_UNEXP_COMP_STAT_LBN 16
+#define PCRF_AZ_UNEXP_COMP_STAT_WIDTH 1
+#define PCRF_AZ_COMP_ABRT_STAT_LBN 15
+#define PCRF_AZ_COMP_ABRT_STAT_WIDTH 1
+#define PCRF_AZ_COMP_TIMEOUT_STAT_LBN 14
+#define PCRF_AZ_COMP_TIMEOUT_STAT_WIDTH 1
+#define PCRF_AZ_FC_PROTO_ERR_STAT_LBN 13
+#define PCRF_AZ_FC_PROTO_ERR_STAT_WIDTH 1
+#define PCRF_AZ_PSON_TLP_STAT_LBN 12
+#define PCRF_AZ_PSON_TLP_STAT_WIDTH 1
+#define PCRF_AZ_DL_PROTO_ERR_STAT_LBN 4
+#define PCRF_AZ_DL_PROTO_ERR_STAT_WIDTH 1
+#define PCRF_AB_TRAIN_ERR_STAT_LBN 0
+#define PCRF_AB_TRAIN_ERR_STAT_WIDTH 1
+
+
+/*------------------------------------------------------------*/
+/*
+ * PCR_AZ_STAT_REG(16bit):
+ * Status register
+ */
+#define PCR_AZ_STAT_REG 0x00000006
+/* sienaa0=pci_f0_config,falcona0,falconb0=pci_f0_config */
+
+#define PCRF_AZ_DET_PERR_LBN 15
+#define PCRF_AZ_DET_PERR_WIDTH 1
+#define PCRF_AZ_SIG_SERR_LBN 14
+#define PCRF_AZ_SIG_SERR_WIDTH 1
+#define PCRF_AZ_GOT_MABRT_LBN 13
+#define PCRF_AZ_GOT_MABRT_WIDTH 1
+#define PCRF_AZ_GOT_TABRT_LBN 12
+#define PCRF_AZ_GOT_TABRT_WIDTH 1
+#define PCRF_AZ_SIG_TABRT_LBN 11
+#define PCRF_AZ_SIG_TABRT_WIDTH 1
+#define PCRF_AZ_DEVSEL_TIM_LBN 9
+#define PCRF_AZ_DEVSEL_TIM_WIDTH 2
+#define PCRF_AZ_MDAT_PERR_LBN 8
+#define PCRF_AZ_MDAT_PERR_WIDTH 1
+#define PCRF_AZ_FB2B_CAP_LBN 7
+#define PCRF_AZ_FB2B_CAP_WIDTH 1
+#define PCRF_AZ_66MHZ_CAP_LBN 5
+#define PCRF_AZ_66MHZ_CAP_WIDTH 1
+#define PCRF_AZ_CAP_LIST_LBN 4
+#define PCRF_AZ_CAP_LIST_WIDTH 1
+#define PCRF_AZ_INTX_STAT_LBN 3
+#define PCRF_AZ_INTX_STAT_WIDTH 1
+
+
+/*------------------------------------------------------------*/
+/*
+ * PCR_CZ_BAR4_HI_REG(32bit):
+ * Primary function base address register 2 high bits
+ */
+#define PCR_CZ_BAR4_HI_REG 0x00000024
+/* sienaa0=pci_f0_config */
+
+#define PCRF_CZ_BAR4_HI_LBN 0
+#define PCRF_CZ_BAR4_HI_WIDTH 32
+
+
+/*------------------------------------------------------------*/
+/*
+ * PCR_CZ_LNK_STAT_REG(16bit):
+ * PCIe link status register
+ */
+#define PCR_CZ_LNK_STAT_REG 0x00000082
+/* sienaa0=pci_f0_config */
+/*
+ * PCR_AB_LNK_STAT_REG(16bit):
+ * PCIe link status register
+ */
+#define PCR_AB_LNK_STAT_REG 0x00000072
+/* falcona0,falconb0=pci_f0_config */
+
+#define PCRF_AZ_SLOT_CLK_CFG_LBN 12
+#define PCRF_AZ_SLOT_CLK_CFG_WIDTH 1
+#define PCRF_AZ_LNK_TRAIN_LBN 11
+#define PCRF_AZ_LNK_TRAIN_WIDTH 1
+#define PCRF_AB_TRAIN_ERR_LBN 10
+#define PCRF_AB_TRAIN_ERR_WIDTH 1
+#define PCRF_AZ_LNK_WIDTH_LBN 4
+#define PCRF_AZ_LNK_WIDTH_WIDTH 6
+#define PCRF_AZ_LNK_SP_LBN 0
+#define PCRF_AZ_LNK_SP_WIDTH 4
+
+
+/*------------------------------------------------------------*/
+/*
+ * PCR_AZ_AER_CORR_ERR_MASK_REG(32bit):
+ * AER Correctable error status register
+ */
+#define PCR_AZ_AER_CORR_ERR_MASK_REG 0x00000114
+/* falcona0,falconb0=pci_f0_config,sienaa0=pci_f0_config */
+
+#define PCRF_CZ_ADVSY_NON_FATAL_MASK_LBN 13
+#define PCRF_CZ_ADVSY_NON_FATAL_MASK_WIDTH 1
+#define PCRF_AZ_RPLY_TMR_TOUT_MASK_LBN 12
+#define PCRF_AZ_RPLY_TMR_TOUT_MASK_WIDTH 1
+#define PCRF_AZ_RPLAY_NUM_RO_MASK_LBN 8
+#define PCRF_AZ_RPLAY_NUM_RO_MASK_WIDTH 1
+#define PCRF_AZ_BAD_DLLP_MASK_LBN 7
+#define PCRF_AZ_BAD_DLLP_MASK_WIDTH 1
+#define PCRF_AZ_BAD_TLP_MASK_LBN 6
+#define PCRF_AZ_BAD_TLP_MASK_WIDTH 1
+#define PCRF_AZ_RX_ERR_MASK_LBN 0
+#define PCRF_AZ_RX_ERR_MASK_WIDTH 1
+
+
+/*------------------------------------------------------------*/
+/*
+ * PCR_AZ_SYM_NUM_REG(16bit):
+ * Symbol number register
+ */
+#define PCR_AZ_SYM_NUM_REG 0x00000718
+/* falcona0,falconb0=pci_f0_config,sienaa0=pci_f0_config */
+
+#define PCRF_CZ_MAX_FUNCTIONS_LBN 29
+#define PCRF_CZ_MAX_FUNCTIONS_WIDTH 3
+#define PCRF_CZ_FC_WATCHDOG_TMR_LBN 24
+#define PCRF_CZ_FC_WATCHDOG_TMR_WIDTH 5
+#define PCRF_CZ_ACK_NAK_TMR_MOD_LBN 19
+#define PCRF_CZ_ACK_NAK_TMR_MOD_WIDTH 5
+#define PCRF_CZ_REPLAY_TMR_MOD_LBN 14
+#define PCRF_CZ_REPLAY_TMR_MOD_WIDTH 5
+#define PCRF_AB_ES_LBN 12
+#define PCRF_AB_ES_WIDTH 3
+#define PCRF_AB_SYM_NUM_REG_RSVD0_LBN 11
+#define PCRF_AB_SYM_NUM_REG_RSVD0_WIDTH 1
+#define PCRF_CZ_NUM_SKP_SYMS_LBN 8
+#define PCRF_CZ_NUM_SKP_SYMS_WIDTH 3
+#define PCRF_AB_TS2_LBN 4
+#define PCRF_AB_TS2_WIDTH 4
+#define PCRF_AZ_TS1_LBN 0
+#define PCRF_AZ_TS1_WIDTH 4
+
+
+/*------------------------------------------------------------*/
+/*
+ * PCR_AZ_Q_STAT_REG(8bit):
+ * documentation to be written for sum_PC_Q_STAT_REG
+ */
+#define PCR_AZ_Q_STAT_REG 0x0000073c
+/* falcona0,falconb0=pci_f0_config,sienaa0=pci_f0_config */
+
+#define PCRF_AZ_RQNE_LBN 2
+#define PCRF_AZ_RQNE_WIDTH 1
+#define PCRF_AZ_XRNE_LBN 1
+#define PCRF_AZ_XRNE_WIDTH 1
+#define PCRF_AZ_RCNR_LBN 0
+#define PCRF_AZ_RCNR_WIDTH 1
+
+
+/*------------------------------------------------------------*/
+/*
+ * PCR_CZ_VPD_CAP_CTL_REG(8bit):
+ * VPD control and capabilities register
+ */
+#define PCR_CZ_VPD_CAP_CTL_REG 0x000000d0
+/* sienaa0=pci_f0_config */
+
+#define PCRF_CZ_VPD_FLAG_LBN 31
+#define PCRF_CZ_VPD_FLAG_WIDTH 1
+#define PCRF_CZ_VPD_ADDR_LBN 16
+#define PCRF_CZ_VPD_ADDR_WIDTH 15
+#define PCRF_CZ_VPD_NXT_PTR_LBN 8
+#define PCRF_CZ_VPD_NXT_PTR_WIDTH 8
+#define PCRF_CZ_VPD_CAP_ID_LBN 0
+#define PCRF_CZ_VPD_CAP_ID_WIDTH 8
+
+
+/*------------------------------------------------------------*/
+/*
+ * PCR_AZ_AER_UNCORR_ERR_MASK_REG(32bit):
+ * AER Uncorrectable error mask register
+ */
+#define PCR_AZ_AER_UNCORR_ERR_MASK_REG 0x00000108
+/* sienaa0=pci_f0_config,falcona0,falconb0=pci_f0_config */
+
+#define PCRF_AZ_UNSUPT_REQ_ERR_MASK_LBN 20
+#define PCRF_AZ_UNSUPT_REQ_ERR_MASK_WIDTH 1
+#define PCRF_AZ_ECRC_ERR_MASK_LBN 19
+#define PCRF_AZ_ECRC_ERR_MASK_WIDTH 1
+#define PCRF_AZ_MALF_TLP_MASK_LBN 18
+#define PCRF_AZ_MALF_TLP_MASK_WIDTH 1
+#define PCRF_AZ_RX_OVF_MASK_LBN 17
+#define PCRF_AZ_RX_OVF_MASK_WIDTH 1
+#define PCRF_AZ_UNEXP_COMP_MASK_LBN 16
+#define PCRF_AZ_UNEXP_COMP_MASK_WIDTH 1
+#define PCRF_AZ_COMP_ABRT_MASK_LBN 15
+#define PCRF_AZ_COMP_ABRT_MASK_WIDTH 1
+#define PCRF_AZ_COMP_TIMEOUT_MASK_LBN 14
+#define PCRF_AZ_COMP_TIMEOUT_MASK_WIDTH 1
+#define PCRF_AZ_FC_PROTO_ERR_MASK_LBN 13
+#define PCRF_AZ_FC_PROTO_ERR_MASK_WIDTH 1
+#define PCRF_AZ_PSON_TLP_MASK_LBN 12
+#define PCRF_AZ_PSON_TLP_MASK_WIDTH 1
+#define PCRF_AZ_DL_PROTO_ERR_MASK_LBN 4
+#define PCRF_AZ_DL_PROTO_ERR_MASK_WIDTH 1
+#define PCRF_AB_TRAIN_ERR_MASK_LBN 0
+#define PCRF_AB_TRAIN_ERR_MASK_WIDTH 1
+
+
+/*------------------------------------------------------------*/
+/*
+ * PCR_CZ_ARI_CAP_REG(16bit):
+ * ARI Capabilities
+ */
+#define PCR_CZ_ARI_CAP_REG 0x00000154
+/* sienaa0=pci_f0_config */
+
+#define PCRF_CZ_ARI_NXT_FN_NUM_LBN 8
+#define PCRF_CZ_ARI_NXT_FN_NUM_WIDTH 8
+#define PCRF_CZ_ARI_ACS_FNGRP_CAP_LBN 1
+#define PCRF_CZ_ARI_ACS_FNGRP_CAP_WIDTH 1
+#define PCRF_CZ_ARI_MFVC_FNGRP_CAP_LBN 0
+#define PCRF_CZ_ARI_MFVC_FNGRP_CAP_WIDTH 1
+
+
+/*------------------------------------------------------------*/
+/*
+ * PCR_CZ_SRIOV_STAT_REG(16bit):
+ * SRIOV Status
+ */
+#define PCR_CZ_SRIOV_STAT_REG 0x0000016a
+/* sienaa0=pci_f0_config */
+
+#define PCRF_CZ_VF_MIGR_STAT_LBN 0
+#define PCRF_CZ_VF_MIGR_STAT_WIDTH 1
+
+
+/*------------------------------------------------------------*/
+/*
+ * PCR_AZ_OTHER_MSG_REG(32bit):
+ * Other message register
+ */
+#define PCR_AZ_OTHER_MSG_REG 0x00000704
+/* sienaa0=pci_f0_config,falcona0,falconb0=pci_f0_config */
+
+#define PCRF_AZ_OM_CRPT3_LBN 24
+#define PCRF_AZ_OM_CRPT3_WIDTH 8
+#define PCRF_AZ_OM_CRPT2_LBN 16
+#define PCRF_AZ_OM_CRPT2_WIDTH 8
+#define PCRF_AZ_OM_CRPT1_LBN 8
+#define PCRF_AZ_OM_CRPT1_WIDTH 8
+#define PCRF_AZ_OM_CRPT0_LBN 0
+#define PCRF_AZ_OM_CRPT0_WIDTH 8
+
+
+/*------------------------------------------------------------*/
+/*
+ * PCR_AB_SLOT_STAT_REG(16bit):
+ * PCIe slot status register
+ */
+#define PCR_AB_SLOT_STAT_REG 0x0000007a
+/* falcona0,falconb0=pci_f0_config */
+
+#define PCRF_AB_PRES_DET_ST_LBN 6
+#define PCRF_AB_PRES_DET_ST_WIDTH 1
+#define PCRF_AB_MRL_SENS_ST_LBN 5
+#define PCRF_AB_MRL_SENS_ST_WIDTH 1
+#define PCRF_AB_SLOT_PWR_IND_LBN 4
+#define PCRF_AB_SLOT_PWR_IND_WIDTH 1
+#define PCRF_AB_SLOT_ATTN_IND_LBN 3
+#define PCRF_AB_SLOT_ATTN_IND_WIDTH 1
+#define PCRF_AB_SLOT_MRL_SENS_LBN 2
+#define PCRF_AB_SLOT_MRL_SENS_WIDTH 1
+#define PCRF_AB_PWR_FLTDET_LBN 1
+#define PCRF_AB_PWR_FLTDET_WIDTH 1
+#define PCRF_AB_ATTN_BUTDET_LBN 0
+#define PCRF_AB_ATTN_BUTDET_WIDTH 1
+
+
+/*------------------------------------------------------------*/
+/*
+ * PCR_CZ_SRIOV_BAR2_REG(32bit):
+ * SRIOV Bar2
+ */
+#define PCR_CZ_SRIOV_BAR2_REG 0x0000018c
+/* sienaa0=pci_f0_config */
+
+/* defined as PCRF_CZ_VF_BAR_ADDRESS_LBN 0; access=rw reset=0x0 */
+/* defined as PCRF_CZ_VF_BAR_ADDRESS_WIDTH 32 */
+
+
+/*------------------------------------------------------------*/
+/*
+ * PCR_AZ_PORT_LNK_CTL_REG(32bit):
+ * Port link control register
+ */
+#define PCR_AZ_PORT_LNK_CTL_REG 0x00000710
+/* sienaa0=pci_f0_config,falcona0,falconb0=pci_f0_config */
+
+#define PCRF_AZ_LRE_LBN 27
+#define PCRF_AZ_LRE_WIDTH 1
+#define PCRF_AZ_ESYNC_LBN 26
+#define PCRF_AZ_ESYNC_WIDTH 1
+#define PCRF_AZ_CRPT_LBN 25
+#define PCRF_AZ_CRPT_WIDTH 1
+#define PCRF_AZ_XB_LBN 24
+#define PCRF_AZ_XB_WIDTH 1
+#define PCRF_AZ_LC_LBN 16
+#define PCRF_AZ_LC_WIDTH 6
+#define PCRF_AZ_LDR_LBN 8
+#define PCRF_AZ_LDR_WIDTH 4
+#define PCRF_AZ_FLM_LBN 7
+#define PCRF_AZ_FLM_WIDTH 1
+#define PCRF_AZ_LKD_LBN 6
+#define PCRF_AZ_LKD_WIDTH 1
+#define PCRF_AZ_DLE_LBN 5
+#define PCRF_AZ_DLE_WIDTH 1
+#define PCRF_AZ_PORT_LNK_CTL_REG_RSVD0_LBN 4
+#define PCRF_AZ_PORT_LNK_CTL_REG_RSVD0_WIDTH 1
+#define PCRF_AZ_RA_LBN 3
+#define PCRF_AZ_RA_WIDTH 1
+#define PCRF_AZ_LE_LBN 2
+#define PCRF_AZ_LE_WIDTH 1
+#define PCRF_AZ_SD_LBN 1
+#define PCRF_AZ_SD_WIDTH 1
+#define PCRF_AZ_OMR_LBN 0
+#define PCRF_AZ_OMR_WIDTH 1
+
+
+/*------------------------------------------------------------*/
+/*
+ * PCR_CZ_VC_XMIT_ARB1_REG(32bit):
+ * VC Transmit Arbitration Register 1
+ */
+#define PCR_CZ_VC_XMIT_ARB1_REG 0x00000740
+/* sienaa0=pci_f0_config */
+
+
+
+/*------------------------------------------------------------*/
+/*
+ * PCR_CZ_VC0_NP_RQ_CTL_REG(32bit):
+ * VC0 Non-Posted Receive Queue Control
+ */
+#define PCR_CZ_VC0_NP_RQ_CTL_REG 0x0000074c
+/* sienaa0=pci_f0_config */
+
+
+
+/*------------------------------------------------------------*/
+/*
+ * PCR_CZ_PHY_CTL_REG(32bit):
+ * PHY control register
+ */
+#define PCR_CZ_PHY_CTL_REG 0x00000814
+/* sienaa0=pci_f0_config */
+/*
+ * PCR_AB_PHY_CTL_REG(32bit):
+ * PHY control register
+ */
+#define PCR_AB_PHY_CTL_REG 0x00000724
+/* falcona0,falconb0=pci_f0_config */
+
+#define PCRF_AZ_BD_LBN 31
+#define PCRF_AZ_BD_WIDTH 1
+#define PCRF_AZ_CDS_LBN 30
+#define PCRF_AZ_CDS_WIDTH 1
+#define PCRF_AZ_DWRAP_LB_LBN 29
+#define PCRF_AZ_DWRAP_LB_WIDTH 1
+#define PCRF_AZ_EBD_LBN 28
+#define PCRF_AZ_EBD_WIDTH 1
+#define PCRF_AZ_SNR_LBN 27
+#define PCRF_AZ_SNR_WIDTH 1
+#define PCRF_AZ_RX_NOT_DET_LBN 2
+#define PCRF_AZ_RX_NOT_DET_WIDTH 1
+#define PCRF_AZ_FORCE_LOS_VAL_LBN 1
+#define PCRF_AZ_FORCE_LOS_VAL_WIDTH 1
+#define PCRF_AZ_FORCE_LOS_EN_LBN 0
+#define PCRF_AZ_FORCE_LOS_EN_WIDTH 1
+
+
+/*------------------------------------------------------------*/
+/*
+ * PCR_AB_VPD_ADDR_REG(16bit):
+ * VPD address register
+ */
+#define PCR_AB_VPD_ADDR_REG 0x000000b2
+/* falcona0,falconb0=pci_f0_config */
+
+#define PCRF_AB_VPD_FLAG_LBN 15
+#define PCRF_AB_VPD_FLAG_WIDTH 1
+#define PCRF_AB_VPD_ADDR_LBN 0
+#define PCRF_AB_VPD_ADDR_WIDTH 15
+
+
+/*------------------------------------------------------------*/
+/*
+ * PCR_AB_SYM_TMR_REG(16bit):
+ * Symbol timer register
+ */
+#define PCR_AB_SYM_TMR_REG 0x0000071c
+/* falcona0,falconb0=pci_f0_config */
+
+#define PCRF_AB_ET_LBN 11
+#define PCRF_AB_ET_WIDTH 4
+#define PCRF_AB_SI1_LBN 8
+#define PCRF_AB_SI1_WIDTH 3
+#define PCRF_AB_SI0_LBN 0
+#define PCRF_AB_SI0_WIDTH 8
+
+
+#endif /* PCI_PROGMODEL_DEFS_H */
+++ /dev/null
-/****************************************************************************
- * Driver for Solarflare network controllers -
- * resource management for Xen backend, OpenOnload, etc
- * (including support for SFE4001 10GBT NIC)
- *
- * This file provides workaround settings for EtherFabric NICs.
- *
- * Copyright 2005-2007: Solarflare Communications Inc,
- * 9501 Jeronimo Road, Suite 250,
- * Irvine, CA 92618, USA
- *
- * Developed and maintained by Solarflare Communications:
- * <linux-xen-drivers@solarflare.com>
- * <onload-dev@solarflare.com>
- *
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published
- * by the Free Software Foundation, incorporated herein by reference.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- ****************************************************************************
- */
-
-#ifndef __CI_DRIVER_EFAB_WORKAROUNDS_H__
-#define __CI_DRIVER_EFAB_WORKAROUNDS_H__
-
-/*----------------------------------------------------------------------------
- *
- * Hardware workarounds which have global scope
- *
- *---------------------------------------------------------------------------*/
-
-#if defined(__CI_HARDWARE_CONFIG_FALCON__)
-
-#if defined(__CI_HARDWARE_CONFIG_FALCON_B0__)
-/*------------------------------- B0 ---------------------------------------*/
-
-#define BUG2175_WORKAROUND 0 /* TX event batching for dual port operation.
- This removes the effect (dup TX events)
- of the fix
- (TX event per packet + batch events) */
-#define BUG5302_WORKAROUND 0 /* unstick TX DMAQ after out-of-range wr ptr */
-#define BUG5475_WORKAROUND 1 /* 10G SNAP encapsulation broken */
-#define BUG5762_WORKAROUND 0 /* Set all queues to jumbo mode */
-#define BUG5391_WORKAROUND 0 /* Misaligned TX can't span 512-byte boundary */
-#define BUG7916_WORKAROUND 0 /* RX flush gets lost */
-
-#else
-/*------------------------------- A0/A1 ------------------------------------*/
-
-#define BUG2175_WORKAROUND 1 /* TX event batching for dual port operation.
- This removes the effect (dup TX events)
- of the fix
- (TX event per packet + batch events) */
-#define BUG5302_WORKAROUND 1 /* unstick TX DMAQ after out-of-range wr ptr */
-#define BUG5475_WORKAROUND 1 /* 10G SNAP encapsulation broken */
-#define BUG5762_WORKAROUND 1 /* Set all queues to jumbo mode */
-#define BUG5391_WORKAROUND 1 /* Misaligned TX can't span 512-byte boundary */
-#define BUG7916_WORKAROUND 1 /* RX flush gets lost */
-
-#endif /* B0/A01 */
-
-#else
-# error Need hw support.
-#endif
-
-#endif /* __CI_DRIVER_EFAB_WORKAROUNDS_H__ */
*
* This file contains public EFX VI API to Solarflare resource manager.
*
- * Copyright 2005-2007: Solarflare Communications Inc,
+ * Copyright 2005-2010: Solarflare Communications Inc,
* 9501 Jeronimo Road, Suite 250,
* Irvine, CA 92618, USA
*
* Allocate an efx_vi, including event queue and pt_endpoint
*
* \param vih_out Pointer to a handle that is set on success
- * \param nic_index Index of NIC to apply this resource to
+ * \param ifindex Index of the network interface desired
* \return Zero on success (and vih_out set), non-zero on failure.
*/
extern int
-efx_vi_alloc(struct efx_vi_state **vih_out, int nic_index);
+efx_vi_alloc(struct efx_vi_state **vih_out, int ifindex);
/*!
* Free a previously allocated efx_vi
*
* This file contains definition of the public type struct linux_efhw_nic.
*
- * Copyright 2005-2007: Solarflare Communications Inc,
+ * Copyright 2005-2010: Solarflare Communications Inc,
* 9501 Jeronimo Road, Suite 250,
* Irvine, CA 92618, USA
*
#ifndef __CI_DRIVER_RESOURCE_LINUX_RESOURCE__
#define __CI_DRIVER_RESOURCE_LINUX_RESOURCE__
+#ifndef __linux__
+# error Silly
+#endif
+#ifndef __KERNEL__
+# error Silly
+#endif
-#include <ci/efhw/efhw_types.h>
+#include <ci/efrm/efrm_nic.h>
#include <linux/interrupt.h>
************************************************************************/
struct linux_efhw_nic {
- struct efhw_nic nic;
+ struct efrm_nic efrm_nic;
struct pci_dev *pci_dev; /*!< pci descriptor */
struct tasklet_struct tasklet; /*!< for interrupt bottom half */
};
-#define linux_efhw_nic(efhw_nic) \
- container_of(efhw_nic, struct linux_efhw_nic, nic)
+#define linux_efhw_nic(_efhw_nic) \
+ container_of(_efhw_nic, struct linux_efhw_nic, efrm_nic.efhw_nic)
#endif /* __CI_DRIVER_RESOURCE_LINUX_RESOURCE__ */
* This file provides helpers to turn bit shifts into dword shifts and
* check that the bit fields haven't overflown the dword etc.
*
- * Copyright 2005-2007: Solarflare Communications Inc,
+ * Copyright 2005-2010: Solarflare Communications Inc,
* 9501 Jeronimo Road, Suite 250,
* Irvine, CA 92618, USA
*
#define __FALCON_MASKFIELD32(LBN, WIDTH) \
((uint32_t)(__FALCON_MASK32(WIDTH) << (LBN)))
-/* constructors for fields which span the first and second dwords */
-#define __LW(LBN) (32 - LBN)
-#define __LOW(v, LBN, WIDTH) \
- ((uint32_t)(((v) & __FALCON_MASK64(__LW((LBN)))) << (LBN)))
-#define __HIGH(v, LBN, WIDTH) \
- ((uint32_t)(((v) >> __LW((LBN))) & \
- __FALCON_MASK64((WIDTH - __LW((LBN))))))
-/* constructors for fields within the second dword */
+
+/* constructors for fields within one DWORD */
#define __DW2(LBN) ((LBN) - 32)
+#define __DW3(LBN) ((LBN) - 64)
+#define __DW4(LBN) ((LBN) - 96)
-/* constructors for fields which span the second and third dwords */
-#define __LW2(LBN) (64 - LBN)
-#define __LOW2(v, LBN, WIDTH) \
- ((uint32_t)(((v) & __FALCON_MASK64(__LW2((LBN)))) << ((LBN) - 32)))
-#define __HIGH2(v, LBN, WIDTH) \
- ((uint32_t)(((v) >> __LW2((LBN))) & \
- __FALCON_MASK64((WIDTH - __LW2((LBN))))))
-/* constructors for fields within the third dword */
-#define __DW3(LBN) ((LBN) - 64)
+/* width for lower portion of field spanning DWORDs */
+#define __LW(LBN) (32 - LBN) /* 0 -> 1 */
+#define __LW2(LBN) (64 - LBN) /* 1 -> 2 */
+#define __LW3(LBN) (96 - LBN) /* 2 -> 3 */
-/* constructors for fields which span the third and fourth dwords */
-#define __LW3(LBN) (96 - LBN)
-#define __LOW3(v, LBN, WIDTH) \
- ((uint32_t)(((v) & __FALCON_MASK64(__LW3((LBN)))) << ((LBN) - 64)))
-#define __HIGH3(v, LBN, WIDTH) \
- ((ci_unit32)(((v) >> __LW3((LBN))) & \
- __FALCON_MASK64((WIDTH - __LW3((LBN))))))
-/* constructors for fields within the fourth dword */
-#define __DW4(LBN) ((LBN) - 96)
+/* constructors for lower portion of field spanning DWORDs */
+#define __LOW(v, F) \
+ ((uint32_t)(((v) & __FALCON_MASK64(__LW(F##_LBN))) << (F##_LBN)))
+#define __LOW2(v, F) \
+ ((uint32_t)(((v) & __FALCON_MASK64(__LW2(F##_LBN))) << __DW2(F##_LBN)))
+#define __LOW3(v, F) \
+ ((uint32_t)(((v) & __FALCON_MASK64(__LW3(F##_LBN))) << __DW3(F##_LBN)))
+
+/* constructors for upper portion of field spanning DWORDs */
+#define __HIGH(v, F) \
+ ((uint32_t)(((v) >> __LW(F##_LBN)) & \
+ __FALCON_MASK64((F##_WIDTH - __LW(F##_LBN)))))
+#define __HIGH2(v, F) \
+ ((uint32_t)(((v) >> __LW2((F##_LBN))) & \
+ __FALCON_MASK64((F##_WIDTH - __LW2((F##_LBN))))))
+#define __HIGH3(v, F) \
+ ((unit32_t)(((v) >> __LW3((F##_LBN))) & \
+ __FALCON_MASK64((F##_WIDTH - __LW3((F##_LBN))))))
+
/* checks that the autogenerated headers are consistent with our model */
-#define __WIDTHCHCK(a, b) EFHW_ASSERT((a) == (b))
#define __RANGECHCK(v, WIDTH) \
EFHW_ASSERT(((uint64_t)(v) & ~(__FALCON_MASK64((WIDTH)))) == 0)
-/* fields within the first dword */
-#define __DWCHCK(LBN, WIDTH) \
- EFHW_ASSERT(((LBN) >= 0) && (((LBN)+(WIDTH)) <= 32))
-
-/* fields which span the first and second dwords */
-#define __LWCHK(LBN, WIDTH) EFHW_ASSERT(WIDTH >= __LW(LBN))
-
-/* fields within the second dword */
-#define __DW2CHCK(LBN, WIDTH) \
- EFHW_ASSERT(((LBN) >= 32) && (((LBN)+(WIDTH)) <= 64))
-/* fields which span the second and third dwords */
-#define __LW2CHK(LBN, WIDTH) EFHW_ASSERT(WIDTH >= __LW2(LBN))
+/* check field width if field within a DWORD */
+#define __DWCHCK(F) \
+ EFHW_BUILD_ASSERT(((F##_LBN) >= 0) && (((F##_LBN)+(F##_WIDTH)) <= 32))
+#define __DW2CHCK(F) \
+ EFHW_BUILD_ASSERT(((F##_LBN) >= 32) && (((F##_LBN)+(F##_WIDTH)) <= 64))
+#define __DW3CHCK(F) \
+ EFHW_BUILD_ASSERT(((F##_LBN) >= 64) && (((F##_LBN)+(F##_WIDTH)) <= 96))
+#define __DW4CHCK(F) \
+ EFHW_BUILD_ASSERT(((F##_LBN) >= 96) && (((F##_LBN)+(F##_WIDTH)) <= 128))
-/* fields within the third dword */
-#define __DW3CHCK(LBN, WIDTH) \
- EFHW_ASSERT(((LBN) >= 64) && (((LBN)+(WIDTH)) <= 96))
-/* fields which span the third and fourth dwords */
-#define __LW3CHK(LBN, WIDTH) EFHW_ASSERT(WIDTH >= __LW3(LBN))
+/* check field width if field spans a DWORD */
+#define __LWCHK(F) EFHW_BUILD_ASSERT(F##_WIDTH >= __LW(F##_LBN))
+#define __LW2CHK(F) EFHW_BUILD_ASSERT(F##_WIDTH >= __LW2(F##_LBN))
+#define __LW3CHK(F) EFHW_BUILD_ASSERT(F##_WIDTH >= __LW3(F##_LBN))
-/* fields within the fourth dword */
-#define __DW4CHCK(LBN, WIDTH) \
- EFHW_ASSERT(((LBN) >= 96) && (((LBN)+(WIDTH)) <= 128))
/* fields in the first qword */
-#define __QWCHCK(LBN, WIDTH) \
- EFHW_ASSERT(((LBN) >= 0) && (((LBN)+(WIDTH)) <= 64))
+#define __QWCHCK(F) \
+ EFHW_BUILD_ASSERT(((F##_LBN) >= 0) && (((F##_LBN)+(F##_WIDTH)) <= 64))
#endif /* __CI_EFHW_CHECK_H__ */
* This file provides API of the efhw library which may be used both from
* the kernel and from the user-space code.
*
- * Copyright 2005-2007: Solarflare Communications Inc,
+ * Copyright 2005-2010: Solarflare Communications Inc,
* 9501 Jeronimo Road, Suite 250,
* Irvine, CA 92618, USA
*
enum efhw_arch {
EFHW_ARCH_FALCON,
- EFHW_ARCH_SIENA,
};
typedef uint32_t efhw_buffer_addr_t;
} efhw_event_t;
/* Flags for TX/RX queues */
-#define EFHW_VI_JUMBO_EN 0x01 /*! scatter RX over multiple desc */
-#define EFHW_VI_ISCSI_RX_HDIG_EN 0x02 /*! iscsi rx header digest */
-#define EFHW_VI_ISCSI_TX_HDIG_EN 0x04 /*! iscsi tx header digest */
-#define EFHW_VI_ISCSI_RX_DDIG_EN 0x08 /*! iscsi rx data digest */
-#define EFHW_VI_ISCSI_TX_DDIG_EN 0x10 /*! iscsi tx data digest */
-#define EFHW_VI_TX_PHYS_ADDR_EN 0x20 /*! TX physical address mode */
-#define EFHW_VI_RX_PHYS_ADDR_EN 0x40 /*! RX physical address mode */
-#define EFHW_VI_RM_WITH_INTERRUPT 0x80 /*! VI with an interrupt */
-#define EFHW_VI_TX_IP_CSUM_DIS 0x100 /*! enable ip checksum generation */
-#define EFHW_VI_TX_TCPUDP_CSUM_DIS 0x200 /*! enable tcp/udp checksum
- generation */
-#define EFHW_VI_TX_TCPUDP_ONLY 0x400 /*! drop non-tcp/udp packets */
+#define EFHW_VI_JUMBO_EN 0x01 /*! scatter RX over multiple desc */
+#define EFHW_VI_ISCSI_RX_HDIG_EN 0x02 /*! iscsi rx header digest */
+#define EFHW_VI_ISCSI_TX_HDIG_EN 0x04 /*! iscsi tx header digest */
+#define EFHW_VI_ISCSI_RX_DDIG_EN 0x08 /*! iscsi rx data digest */
+#define EFHW_VI_ISCSI_TX_DDIG_EN 0x10 /*! iscsi tx data digest */
+#define EFHW_VI_TX_PHYS_ADDR_EN 0x20 /*! TX physical address mode */
+#define EFHW_VI_RX_PHYS_ADDR_EN 0x40 /*! RX physical address mode */
+#define EFHW_VI_RM_WITH_INTERRUPT 0x80 /*! VI with an interrupt */
+#define EFHW_VI_TX_IP_CSUM_DIS 0x100 /*! enable ip checksum generation */
+#define EFHW_VI_TX_TCPUDP_CSUM_DIS 0x200 /*! enable tcp/udp checksum
+ generation */
+#define EFHW_VI_TX_TCPUDP_ONLY 0x400 /*! drop non-tcp/udp packets */
+/* from here on, Siena only: */
+#define EFHW_VI_TX_IP_FILTER_EN 0x800 /*! TX IP filtering */
+#define EFHW_VI_TX_ETH_FILTER_EN 0x1000 /*! TX MAC filtering */
+#define EFHW_VI_TX_Q_MASK_WIDTH_0 0x2000 /*! TX filter q_mask_width bit 0 */
+#define EFHW_VI_TX_Q_MASK_WIDTH_1 0x4000 /*! TX filter q_mask_width bit 1 */
+#define EFHW_VI_RX_HDR_SPLIT 0x8000 /*! RX header split */
/* Types of hardware filter */
/* Each of these values implicitly selects scatter filters on B0 - or in
#define EFHW_IP_FILTER_BROADCAST (0x10000) /* driverlink filter
support */
+/* Similar for RX MAC filters -- Siena only */
+#define EFHW_MAC_FILTER_TYPE_WILDCARD (0)
+#define EFHW_MAC_FILTER_TYPE_FULL (1)
+#define EFHW_MAC_FILTER_TYPE_IPOVER_WILDCARD (2)
+#define EFHW_MAC_FILTER_TYPE_IPOVER_FULL (3)
+/* Same again, but with RSS */
+#define EFHW_MAC_FILTER_TYPE_WILDCARD_RSS (4)
+#define EFHW_MAC_FILTER_TYPE_FULL_RSS (5)
+#define EFHW_MAC_FILTER_TYPE_IPOVER_WILDCARD_RSS (6)
+#define EFHW_MAC_FILTER_TYPE_IPOVER_FULL_RSS (7)
+
+#define EFHW_MAC_FILTER_TYPE_FULL_MASK (0x1) /* Mask for full / wildcard */
+#define EFHW_MAC_FILTER_TYPE_IPOVER_MASK (0x2) /* Mask for IP override flg */
+#define EFHW_MAC_FILTER_TYPE_RSS_MASK (0x4) /* Mask for RSS enable */
+#define EFHW_MAC_FILTER_TYPE_NOSCAT_MASK (0x8) /* Mask for SCATTER dsbl */
+
+#define EFHW_MAC_FILTER_TYPE_MASK (0xffff) /* Mask of types above */
+
#endif /* __CI_EFHW_COMMON_H__ */
* userland-to-kernel interfaces.
* Only kernels >=2.6.9 are supported.
*
- * Copyright 2005-2007: Solarflare Communications Inc,
+ * Copyright 2005-2010: Solarflare Communications Inc,
* 9501 Jeronimo Road, Suite 250,
* Irvine, CA 92618, USA
*
/* Linux kernel also does not provide PRIx32... Sigh. */
#define PRIx32 "x"
-
+
#ifdef __ia64__
# define PRIx64 "lx"
#else
# define PRIx64 "llx"
#endif
-#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,19)
-enum {
- false = 0,
- true = 1
-};
-
-typedef _Bool bool;
-#endif /* LINUX_VERSION_CODE < 2.6.19 */
#endif /* __CI_EFHW_COMMON_LINUX_H__ */
* This file provides debug-related API for efhw library using Linux kernel
* primitives.
*
- * Copyright 2005-2007: Solarflare Communications Inc,
+ * Copyright 2005-2010: Solarflare Communications Inc,
* 9501 Jeronimo Road, Suite 250,
* Irvine, CA 92618, USA
*
#define EFHW_PRINTK_PREFIX "[sfc efhw] "
+#ifndef printk_nl
+#define printk_nl "\n"
+#endif
+
#define EFHW_PRINTK(level, fmt, ...) \
- printk(level EFHW_PRINTK_PREFIX fmt "\n", __VA_ARGS__)
+ printk(level EFHW_PRINTK_PREFIX fmt printk_nl, __VA_ARGS__)
/* Following macros should be used with non-zero format parameters
* due to __VA_ARGS__ limitations. Use "%s" with __FUNCTION__ if you can't
#define __EFHW_BUILD_ASSERT_NAME(_x) __EFHW_BUILD_ASSERT_ILOATHECPP(_x)
#define __EFHW_BUILD_ASSERT_ILOATHECPP(_x) __EFHW_BUILD_ASSERT__ ##_x
#define EFHW_BUILD_ASSERT(e) \
- typedef char __EFHW_BUILD_ASSERT_NAME(__LINE__)[(e) ? 1 : -1]
+ { typedef char __EFHW_BUILD_ASSERT_NAME(__LINE__)[(e) ? 1 : -1]; }
#endif
#endif /* __CI_EFHW_DEBUG_LINUX_H__ */
*
* This file provides some limits used in both kernel and userland code.
*
- * Copyright 2005-2007: Solarflare Communications Inc,
+ * Copyright 2005-2010: Solarflare Communications Inc,
* 9501 Jeronimo Road, Suite 250,
* Irvine, CA 92618, USA
*
*
* This file provides struct efhw_nic and some related types.
*
- * Copyright 2005-2007: Solarflare Communications Inc,
+ * Copyright 2005-2010: Solarflare Communications Inc,
* 9501 Jeronimo Road, Suite 250,
* Irvine, CA 92618, USA
*
struct eventq_resource_hardware {
/*!iobuffer allocated for eventq - can be larger than eventq */
struct efhw_iopages iobuff;
- unsigned iobuff_off;
struct efhw_buffer_table_allocation buf_tbl_alloc;
int capacity; /*!< capacity of event queue */
};
struct efhw_ev_handler *ev_handlers;
};
+/*--------------------------------------------------------------------
+ *
+ * filters
+ *
+ *--------------------------------------------------------------------*/
+
+enum efhw_filter_type {
+ EFHW_FILTER_TYPE_IP = 0, /* always supported */
+ EFHW_FILTER_TYPE_MAC, /* supported by Siena only */
+ EFHW_FILTER_TYPE_TX_IP, /* supported by Siena only */
+ EFHW_FILTER_TYPE_TX_MAC, /* supported by Siena only */
+ EFHW_FILTER_TYPES_NUM
+};
+
+struct efhw_filter_spec {
+ enum efhw_filter_type type;
+ uint dmaq_id;
+ union {
+ struct {
+ uint32_t saddr_le32;
+ uint32_t daddr_le32;
+ uint16_t sport_le16;
+ uint16_t dport_le16;
+ unsigned tcp : 1;
+ unsigned full : 1;
+ unsigned rss : 1; /* not supported on A1 */
+ unsigned scatter : 1; /* not supported on A1 */
+ } ip;
+ struct {
+ uint32_t saddr_le32;
+ uint32_t daddr_le32;
+ uint16_t sport_le16;
+ uint16_t dport_le16;
+ unsigned tcp : 1;
+ unsigned full : 1;
+ } tx_ip;
+ struct {
+ uint8_t mac[6];
+ uint16_t vlan_tag;
+ unsigned full : 1;
+ unsigned ip_override : 1;
+ unsigned rss : 1;
+ unsigned scatter : 1;
+ } mac;
+ struct {
+ uint8_t mac[6];
+ uint16_t vlan_tag;
+ unsigned full : 1;
+ } tx_mac;
+ } u;
+};
+
+struct efhw_filter_depth {
+ unsigned needed;
+ unsigned max;
+};
+
+struct efhw_filter_search_limits {
+ unsigned tcp_full;
+ unsigned tcp_wild;
+ unsigned udp_full;
+ unsigned udp_wild;
+ unsigned mac_full;
+ unsigned mac_wild;
+};
+
+
/**********************************************************************
* Portable HW interface. ***************************************
**********************************************************************/
/*! Set interrupt moderation strategy for the given IRQ unit
** val is in usec
*/
- void (*set_interrupt_moderation)(struct efhw_nic *nic,
+ void (*set_interrupt_moderation)(struct efhw_nic *nic, int evq,
uint val);
/*-------------- Event support ------------ */
void (*event_queue_enable) (struct efhw_nic *nic,
uint evq, /* evnt queue index */
uint evq_size, /* units of #entries */
- dma_addr_t q_base_addr, uint buf_base_id);
+ uint buf_base_id,
+ int interrupting,
+ int enable_dos_p);
/*! Disable the given event queue (and any associated timer) */
void (*event_queue_disable) (struct efhw_nic *nic, uint evq,
int timer_only);
/*! request wakeup from the NIC on a given event Q */
- void (*wakeup_request) (struct efhw_nic *nic, dma_addr_t q_base_addr,
- int next_i, int evq);
+ void (*wakeup_request) (struct efhw_nic *nic, int rd_ptr, int evq);
/*! Push a SW event on a given eventQ */
void (*sw_event) (struct efhw_nic *nic, int data, int evq);
- /*-------------- Filter support ------------ */
+ /*-------------- IP Filter API ------------ */
/*! Setup a given filter - The software can request a filter_i,
* but some EtherFabric implementations will override with
unsigned saddr_be32, unsigned sport_be16,
unsigned daddr_be32, unsigned dport_be16);
- /*! Attach a given filter to a DMAQ */
- void (*ipfilter_attach) (struct efhw_nic *nic, int filter_idx,
- int dmaq_idx);
-
- /*! Detach a filter from its DMAQ */
- void (*ipfilter_detach) (struct efhw_nic *nic, int filter_idx);
-
/*! Clear down a given filter */
void (*ipfilter_clear) (struct efhw_nic *nic, int filter_idx);
+ /*! Redirect given filter to a different RX DMAQ */
+ void (*ipfilter_redirect) (struct efhw_nic *nic, int filter_i,
+ int rxq_i);
+
/*-------------- DMA support ------------ */
/*! Initialise NIC state for a given TX DMAQ */
/*! Commit a buffer table update */
void (*buffer_table_commit) (struct efhw_nic *nic);
+ /*-------------- New filter API ------------ */
+
+ /*! Set a given filter */
+ int (*filter_set) (struct efhw_nic *nic, struct efhw_filter_spec *spec,
+ int *filter_idx_out);
+
+ /*! Clear a given filter */
+ void (*filter_clear) (struct efhw_nic *nic, enum efhw_filter_type type,
+ int filter_idx);
};
int arch; /* enum efhw_arch */
char variant; /* 'A', 'B', ... */
int revision; /* 0, 1, ... */
+ int in_fpga:1;
+ int in_cosim:1;
};
/*! EtherFabric Functional Units -- functions */
const struct efhw_func_ops *efhw_func;
- /* Value read from FPGA version register. Zero for asic. */
- unsigned fpga_version;
-
/*! This lock protects a number of misc NIC resources. It should
* only be used for things that can be at the bottom of the lock
* order. ie. You mustn't attempt to grab any other lock while
struct efhw_keventq non_interrupting_evq;
- struct efhw_iopage irq_iobuff; /*!< Falcon SYSERR interrupt */
-
- /* The new driverlink infrastructure. */
- struct efx_dl_device *net_driver_dev;
- struct efx_dlfilt_cb_s *dlfilter_cb;
-
/*! Bit masks of the sizes of event queues and dma queues supported
* by the nic. */
unsigned evq_sizes;
unsigned rxq_sizes;
unsigned txq_sizes;
- /* Size of filter table (including odd and even banks). */
- unsigned filter_tbl_size;
+ /* Size of filter tables. */
+ unsigned ip_filter_tbl_size;
+ unsigned mac_filter_tbl_size;
+ unsigned tx_ip_filter_tbl_size;
+ unsigned tx_mac_filter_tbl_size;
+
+ /* Number of filters currently used in each filter table */
+ unsigned ip_filter_tbl_used;
+ unsigned mac_filter_tbl_used;
+ unsigned tx_ip_filter_tbl_used;
+ unsigned tx_mac_filter_tbl_used;
+
+ /* Dynamically allocated filter state. */
+ uint8_t *filter_in_use;
+ struct efhw_filter_spec *filter_spec_cache;
+
+ /* Currently required and maximum filter table search depths. */
+ struct efhw_filter_depth tcp_full_srch;
+ struct efhw_filter_depth tcp_wild_srch;
+ struct efhw_filter_depth udp_full_srch;
+ struct efhw_filter_depth udp_wild_srch;
+ struct efhw_filter_depth mac_full_srch;
+ struct efhw_filter_depth mac_wild_srch;
+ struct efhw_filter_depth tx_tcp_full_srch;
+ struct efhw_filter_depth tx_tcp_wild_srch;
+ struct efhw_filter_depth tx_udp_full_srch;
+ struct efhw_filter_depth tx_udp_wild_srch;
+ struct efhw_filter_depth tx_mac_full_srch;
+ struct efhw_filter_depth tx_mac_wild_srch;
+
+ /* Number of event queues, DMA queues and timers. */
+ unsigned num_evqs;
+ unsigned num_dmaqs;
+ unsigned num_timers;
};
#define EFHW_KVA(nic) ((nic)->bar_ioaddr)
+static inline int efhw_in_fpga(struct efhw_nic *nic) {
+ return nic->devtype.in_fpga;
+}
+
+static inline int efhw_in_cosim(struct efhw_nic *nic) {
+ return nic->devtype.in_cosim;
+}
#endif /* __CI_EFHW_EFHW_TYPES_H__ */
* This file contains API provided by efhw/eventq.c file. This file is not
* designed for use outside of the SFC resource driver.
*
- * Copyright 2005-2007: Solarflare Communications Inc,
+ * Copyright 2005-2010: Solarflare Communications Inc,
* 9501 Jeronimo Road, Suite 250,
* Irvine, CA 92618, USA
*
struct efhw_ev_handler {
void (*wakeup_fn)(struct efhw_nic *nic, unsigned);
void (*timeout_fn)(struct efhw_nic *nic, unsigned);
- void (*dmaq_flushed_fn) (struct efhw_nic *, unsigned, int);
+ void (*dmaq_flushed_fn) (struct efhw_nic *, unsigned, int, int);
};
extern int efhw_keventq_ctor(struct efhw_nic *, int instance,
* This file provides some event-related macros. This file is designed for
* use from kernel and from the userland contexts.
*
- * Copyright 2005-2007: Solarflare Communications Inc,
+ * Copyright 2005-2010: Solarflare Communications Inc,
* 9501 Jeronimo Road, Suite 250,
* Irvine, CA 92618, USA
*
#define EFHW_EVENTQ_PREV(s) \
do { ((s)->evq_ptr -= sizeof(efhw_event_t)); } while (0)
-/* Be worried about this on byteswapped machines */
-#if defined(__CI_HARDWARE_CONFIG_FALCON__)
/* Due to crazy chipsets, we see the event words being written in
- ** arbitrary order (bug4539). So test for presence of event must ensure
- ** that both halves have changed from the null.
+ * arbitrary order (bug4539). So test for presence of event must ensure
+ * that both halves have changed from the null.
*/
#define EFHW_IS_EVENT(evp) \
(((evp)->opaque.a != (uint32_t)-1) && \
((evp)->opaque.b != (uint32_t)-1))
#define EFHW_CLEAR_EVENT(evp) ((evp)->u64 = (uint64_t)-1)
#define EFHW_CLEAR_EVENT_VALUE 0xff
-#else
- #error Fixme - unknown hardware configuration
-#endif
+
#define EFHW_EVENT_OVERFLOW(evq, s) \
(EFHW_IS_EVENT(EFHW_EVENT_PTR(evq, s, 1)))
* This file contains API provided by efhw/falcon.c file. This file is not
* designed for use outside of the SFC resource driver.
*
- * Copyright 2005-2007: Solarflare Communications Inc,
+ * Copyright 2005-2010: Solarflare Communications Inc,
* 9501 Jeronimo Road, Suite 250,
* Irvine, CA 92618, USA
*
/*! specify a pace value for a TX DMA Queue */
extern void falcon_nic_pace(struct efhw_nic *nic, uint dmaq, uint pace);
+/*! configure the pace engine */
+extern void falcon_nic_pace_cfg(struct efhw_nic *nic, int fb_base,
+ int bin_thresh);
+
+/*! Set wakeup mask. Falcon B0 and later. */
+extern void falcon_nic_wakeup_mask_set(struct efhw_nic *nic, unsigned mask);
+
/*! confirm buffer table updates - should be used for items where
loss of data would be unacceptable. E.g for the buffers that back
an event or DMA queue */
/*! Acknowledge to HW that processing is complete on a given event queue */
extern void falcon_nic_evq_ack(struct efhw_nic *nic, uint evq, /* evq id */
- uint rptr, /* new read pointer update */
- bool wakeup /* request a wakeup event if
- ptr's != */
- );
+ uint rptr /* new read pointer update */);
extern void
falcon_nic_buffer_table_set_n(struct efhw_nic *nic, int buffer_id,
dma_addr_t dma_addr, uint bufsz, uint region,
int n_pages, int own_id);
-extern void falcon_nic_ipfilter_ctor(struct efhw_nic *nic);
+extern int falcon_nic_filter_ctor(struct efhw_nic *nic);
+
#endif /* __CI_EFHW_FALCON_H__ */
* Function declared in this file are not exported from the Linux
* sfc_resource driver.
*
- * Copyright 2005-2007: Solarflare Communications Inc,
+ * Copyright 2005-2010: Solarflare Communications Inc,
* 9501 Jeronimo Road, Suite 250,
* Irvine, CA 92618, USA
*
#ifndef __CI_EFHW_FALCON_HASH_H__
#define __CI_EFHW_FALCON_HASH_H__
-/* All LE parameters */
+/* For Falcon and Siena: IP filter table key */
extern unsigned int
-falcon_hash_get_key(unsigned int src_ip, unsigned int src_port,
- unsigned int dest_ip, unsigned int dest_port,
- int tcp, int full);
+falcon_hash_get_ip_key(unsigned int src_ip, unsigned int src_port,
+ unsigned int dest_ip, unsigned int dest_port,
+ int tcp, int full);
-unsigned int falcon_hash_function1(unsigned int key, unsigned int nfilters);
+/* For Siena only: MAC filter table key */
+extern unsigned int
+falcon_hash_get_mac_key(unsigned char *mac, unsigned int vlan, int full);
+
+/* For Siena only: TX IP filter table key */
+extern unsigned int
+falcon_hash_get_tx_ip_key(unsigned int src_ip, unsigned int src_port,
+ unsigned int dest_ip, unsigned int dest_port,
+ int tcp, int full, unsigned int masked_q_id);
+
+/* For Siena only: TX MAC filter table key */
+extern unsigned int
+falcon_hash_get_tx_mac_key(unsigned char *mac, unsigned int vlan, int full,
+ unsigned int masked_q_id);
+
+extern unsigned int
+falcon_hash_function1(unsigned int key, unsigned int nfilters);
extern unsigned int
-falcon_hash_function2(unsigned int key, unsigned int nfitlers);
+falcon_hash_function2(unsigned int key, unsigned int nfilters);
extern unsigned int
falcon_hash_iterator(unsigned int hash1, unsigned int hash2,
* with hardware-related definitions (in ci/driver/efab/hardware*).
* Only kernels >=2.6.9 are supported.
*
- * Copyright 2005-2007: Solarflare Communications Inc,
+ * Copyright 2005-2010: Solarflare Communications Inc,
* 9501 Jeronimo Road, Suite 250,
* Irvine, CA 92618, USA
*
#ifndef __CI_EFHW_HARDWARE_LINUX_H__
#define __CI_EFHW_HARDWARE_LINUX_H__
+#include <linux/version.h>
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,16)
+#include <linux/io.h>
+#else
#include <asm/io.h>
+#endif
#ifdef __LITTLE_ENDIAN
#define EFHW_IS_LITTLE_ENDIAN
* The implementation of these functions is highly OS-dependent.
* This file is not designed for use outside of the SFC resource driver.
*
- * Copyright 2005-2007: Solarflare Communications Inc,
+ * Copyright 2005-2010: Solarflare Communications Inc,
* 9501 Jeronimo Road, Suite 250,
* Irvine, CA 92618, USA
*
* This file provides struct efhw_page and struct efhw_iopage for Linux
* kernel.
*
- * Copyright 2005-2007: Solarflare Communications Inc,
+ * Copyright 2005-2010: Solarflare Communications Inc,
* 9501 Jeronimo Road, Suite 250,
* Irvine, CA 92618, USA
*
* This file contains API provided by efhw/nic.c file. This file is not
* designed for use outside of the SFC resource driver.
*
- * Copyright 2005-2007: Solarflare Communications Inc,
+ * Copyright 2005-2010: Solarflare Communications Inc,
* 9501 Jeronimo Road, Suite 250,
* Irvine, CA 92618, USA
*
* This file provides public API of efhw library exported from the SFC
* resource driver.
*
- * Copyright 2005-2007: Solarflare Communications Inc,
+ * Copyright 2005-2010: Solarflare Communications Inc,
* 9501 Jeronimo Road, Suite 250,
* Irvine, CA 92618, USA
*
extern void falcon_nic_set_rx_usr_buf_size(struct efhw_nic *,
int rx_usr_buf_size);
+/*! Get RX filter search limits from RX_FILTER_CTL_REG.
+ * use_raw_values = 0 to get actual depth of search, or 1 to get raw values
+ * from register.
+ */
+extern void
+falcon_nic_get_rx_filter_search_limits(struct efhw_nic *nic,
+ struct efhw_filter_search_limits *lim,
+ int use_raw_values);
+
+/*! Set RX filter search limits in RX_FILTER_CTL_REG.
+ * use_raw_values = 0 if specifying actual depth of search, or 1 if specifying
+ * raw values to write to the register.
+ */
+extern void
+falcon_nic_set_rx_filter_search_limits(struct efhw_nic *nic,
+ struct efhw_filter_search_limits *lim,
+ int use_raw_values);
+
+/*! Get TX filter search limits from TX_CFG_REG (on Siena only).
+ * use_raw_values = 0 to get actual depth of search, or 1 to get raw values
+ * from register.
+ */
+extern void
+falcon_nic_get_tx_filter_search_limits(struct efhw_nic *nic,
+ struct efhw_filter_search_limits *lim,
+ int use_raw_values);
+
+/*! Set TX filter search limits in TX_CFG_REG (on Siena only).
+ * use_raw_values = 0 if specifying actual depth of search, or 1 if specifying
+ * raw values to write to the register.
+ */
+extern void
+falcon_nic_set_tx_filter_search_limits(struct efhw_nic *nic,
+ struct efhw_filter_search_limits *lim,
+ int use_raw_values);
+
+
+/*! Legacy RX IP filter search depth control interface */
extern void
falcon_nic_rx_filter_ctl_set(struct efhw_nic *nic, uint32_t tcp_full,
uint32_t tcp_wild,
uint32_t udp_full, uint32_t udp_wild);
+/*! Legacy RX IP filter search depth control interface */
extern void
falcon_nic_rx_filter_ctl_get(struct efhw_nic *nic, uint32_t *tcp_full,
uint32_t *tcp_wild,
* This file provides version-independent Linux kernel API for efhw library.
* Only kernels >=2.6.9 are supported.
*
- * Copyright 2005-2007: Solarflare Communications Inc,
+ * Copyright 2005-2010: Solarflare Communications Inc,
* 9501 Jeronimo Road, Suite 250,
* Irvine, CA 92618, USA
*
#include <linux/module.h>
#include <linux/spinlock.h>
#include <linux/delay.h>
+#include <linux/vmalloc.h>
#include <linux/if_ether.h>
#include <linux/netdevice.h> /* necessary for etherdevice.h on some kernels */
#include <linux/etherdevice.h>
-#if LINUX_VERSION_CODE <= KERNEL_VERSION(2,6,21)
-static inline int is_local_ether_addr(const u8 *addr)
-{
- return (0x02 & addr[0]);
-}
-#endif
+#include "kernel_compat.h"
+
typedef unsigned long irq_flags_t;
#define HAS_NET_NAMESPACE
#endif
-/* Funny, but linux has round_up for x86 only, defined in
- * x86-specific header */
-#ifndef round_up
-#define round_up(x, y) (((x) + (y) - 1) & ~((y)-1))
+#ifndef roundup
+#define roundup(x, y) (((x) + (y) - 1) & ~((y)-1))
#endif
#endif /* __CI_EFHW_SYSDEP_LINUX_H__ */
* This file provides private API for buddy allocator. This API is not
* designed for use outside of SFC resource driver.
*
- * Copyright 2005-2007: Solarflare Communications Inc,
+ * Copyright 2005-2010: Solarflare Communications Inc,
* 9501 Jeronimo Road, Suite 250,
* Irvine, CA 92618, USA
*
int efrm_buddy_alloc(struct efrm_buddy_allocator *b, unsigned order);
void efrm_buddy_free(struct efrm_buddy_allocator *b, unsigned addr,
unsigned order);
-void efrm_buddy_reserve_at_start(struct efrm_buddy_allocator *b, unsigned n);
-void efrm_buddy_reserve_at_end(struct efrm_buddy_allocator *b, unsigned n);
+
#endif /* __CI_EFRM_BUDDY_H__ */
* This file provides private buffer table API. This API is not designed
* for use outside of SFC resource driver.
*
- * Copyright 2005-2007: Solarflare Communications Inc,
+ * Copyright 2005-2010: Solarflare Communications Inc,
* 9501 Jeronimo Road, Suite 250,
* Irvine, CA 92618, USA
*
extern int efrm_buffer_table_alloc(unsigned order,
struct efhw_buffer_table_allocation *a);
-/*! current size of the buffer table.
- * FIXME This function should be inline, but it is never used from
- * the fast path, so let it as-is. */
-unsigned long efrm_buffer_table_size(void);
/*--------------------------------------------------------------------
*
extern void efrm_buffer_table_free(struct efhw_buffer_table_allocation *a);
/*! commit the update of a buffer table entry to every NIC */
-void efrm_buffer_table_commit(void);
+extern void efrm_buffer_table_commit(void);
+
+extern void efrm_buffer_table_set(struct efhw_buffer_table_allocation *,
+ struct efhw_nic *,
+ unsigned i, dma_addr_t dma_addr, int owner);
-/*! set a given buffer table entry. [pa] should be the physical
- address of pinned down memory. This function can only be called from
- the char driver */
-void efrm_buffer_table_set(struct efhw_buffer_table_allocation *a,
- unsigned i, dma_addr_t dma_addr, int owner);
#endif /* __CI_EFRM_BUFFER_TABLE_H__ */
* This file provides debug-related API for efrm library using Linux kernel
* primitives.
*
- * Copyright 2005-2007: Solarflare Communications Inc,
+ * Copyright 2005-2010: Solarflare Communications Inc,
* 9501 Jeronimo Road, Suite 250,
* Irvine, CA 92618, USA
*
#define EFRM_ERR(fmt, ...) EFRM_PRINTK(KERN_ERR, fmt, __VA_ARGS__)
#define EFRM_WARN(fmt, ...) EFRM_PRINTK(KERN_WARNING, fmt, __VA_ARGS__)
#define EFRM_NOTICE(fmt, ...) EFRM_PRINTK(KERN_NOTICE, fmt, __VA_ARGS__)
-#if 0 && !defined(NDEBUG)
+#if !defined(NDEBUG)
#define EFRM_TRACE(fmt, ...) EFRM_PRINTK(KERN_DEBUG, fmt, __VA_ARGS__)
#else
#define EFRM_TRACE(fmt, ...)
* This file provides private API of efrm library to be used from the SFC
* resource driver.
*
- * Copyright 2005-2007: Solarflare Communications Inc,
+ * Copyright 2005-2010: Solarflare Communications Inc,
* 9501 Jeronimo Road, Suite 250,
* Irvine, CA 92618, USA
*
*
*--------------------------------------------------------------------*/
-extern int efrm_driver_ctor(void);
-extern int efrm_driver_dtor(void);
-extern int efrm_driver_register_nic(struct efhw_nic *, int nic_index);
-extern int efrm_driver_unregister_nic(struct efhw_nic *);
+struct efrm_nic;
+
+extern void efrm_driver_ctor(void);
+extern void efrm_driver_dtor(void);
+extern int efrm_driver_register_nic(struct efrm_nic *, int nic_index,
+ int ifindex);
+extern int efrm_driver_unregister_nic(struct efrm_nic *);
/*--------------------------------------------------------------------
*
--- /dev/null
+/****************************************************************************
+ * Driver for Solarflare network controllers -
+ * resource management for Xen backend, OpenOnload, etc
+ * (including support for SFE4001 10GBT NIC)
+ *
+ * This file provides helpers to turn bit shifts into dword shifts and
+ * check that the bit fields haven't overflown the dword etc.
+ *
+ * Copyright 2005-2010: Solarflare Communications Inc,
+ * 9501 Jeronimo Road, Suite 250,
+ * Irvine, CA 92618, USA
+ *
+ * Developed and maintained by Solarflare Communications:
+ * <linux-xen-drivers@solarflare.com>
+ * <onload-dev@solarflare.com>
+ *
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation, incorporated herein by reference.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ ****************************************************************************
+ */
+
+#ifndef __EFRM_CLIENT_H__
+#define __EFRM_CLIENT_H__
+
+
+struct efrm_client;
+
+
+struct efrm_client_callbacks {
+ /* Called before device is reset. Callee may block. */
+ void (*pre_reset)(struct efrm_client *, void *user_data);
+ void (*stop)(struct efrm_client *, void *user_data);
+ void (*restart)(struct efrm_client *, void *user_data);
+};
+
+
+#define EFRM_IFINDEX_DEFAULT -1
+
+
+/* NB. Callbacks may be invoked even before this returns. */
+extern int efrm_client_get(int ifindex, struct efrm_client_callbacks *,
+ void *user_data, struct efrm_client **client_out);
+extern void efrm_client_put(struct efrm_client *);
+
+extern struct efhw_nic *efrm_client_get_nic(struct efrm_client *);
+extern int efrm_client_get_ifindex(struct efrm_client *);
+
+#if 0
+/* For each resource type... */
+extern void efrm_x_resource_resume(struct x_resource *);
+#endif
+
+
+#endif /* __EFRM_CLIENT_H__ */
--- /dev/null
+/****************************************************************************
+ * Driver for Solarflare network controllers -
+ * resource management for Xen backend, OpenOnload, etc
+ * (including support for SFE4001 10GBT NIC)
+ *
+ * This file provides helpers to turn bit shifts into dword shifts and
+ * check that the bit fields haven't overflown the dword etc.
+ *
+ * Copyright 2005-2010: Solarflare Communications Inc,
+ * 9501 Jeronimo Road, Suite 250,
+ * Irvine, CA 92618, USA
+ *
+ * Developed and maintained by Solarflare Communications:
+ * <linux-xen-drivers@solarflare.com>
+ * <onload-dev@solarflare.com>
+ *
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation, incorporated herein by reference.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ ****************************************************************************
+ */
+
+#ifndef __EFRM_NIC_H__
+#define __EFRM_NIC_H__
+
+#include <ci/efhw/efhw_types.h>
+
+
+struct efrm_nic_per_vi {
+ unsigned long state;
+ struct vi_resource *vi;
+};
+
+
+struct efrm_nic {
+ struct efhw_nic efhw_nic;
+ struct list_head link;
+ struct list_head clients;
+ struct efrm_nic_per_vi *vis;
+};
+
+
+#define efrm_nic(_efhw_nic) \
+ container_of(_efhw_nic, struct efrm_nic, efhw_nic)
+
+
+
+#endif /* __EFRM_NIC_H__ */
*
* This file provides public API for filter resource.
*
- * Copyright 2005-2007: Solarflare Communications Inc,
+ * Copyright 2005-2010: Solarflare Communications Inc,
* 9501 Jeronimo Road, Suite 250,
* Irvine, CA 92618, USA
*
#define __CI_EFRM_FILTER_H__
#include <ci/efrm/resource.h>
-#include <ci/efrm/vi_resource.h>
-#include <ci/efrm/nic_set.h>
#include <ci/efhw/common.h>
+#include <ci/efrm/debug.h>
-/*! Comment? */
-struct filter_resource {
- struct efrm_resource rs;
- struct vi_resource *pt;
- int filter_idx;
- efrm_nic_set_t nic_set;
-};
-#define filter_resource(rs1) container_of((rs1), struct filter_resource, rs)
+struct filter_resource;
+struct vi_resource;
+struct efrm_client;
+
/*!
* Allocate filter resource.
efrm_filter_resource_alloc(struct vi_resource *vi_parent,
struct filter_resource **frs_out);
-/* efrm_filter_resource_free should be called only if
- * __efrm_resource_ref_count_zero() returned true.
- * The easiest way is to call efrm_filter_resource_release() */
-void efrm_filter_resource_free(struct filter_resource *frs);
-static inline void efrm_filter_resource_release(struct filter_resource *frs)
-{
- unsigned id;
-
- EFRM_RESOURCE_ASSERT_VALID(&frs->rs, 0);
- id = EFRM_RESOURCE_INSTANCE(frs->rs.rs_handle);
-
- if (atomic_dec_and_test(&frs->rs.rs_ref_count)) {
- if (__efrm_resource_ref_count_zero(EFRM_RESOURCE_FILTER, id)) {
- EFRM_ASSERT(EFRM_RESOURCE_INSTANCE(frs->rs.rs_handle) ==
- id);
- efrm_filter_resource_free(frs);
- }
- }
-}
-
-/*--------------------------------------------------------------------
- *!
- * Called to set/change the PT endpoint of a filter
- *
- * Example of use is TCP helper when it finds a wildcard IP filter
- * needs to change which application it delivers traffic to
- *
- * \param frs filter resource
- * \param pt_handle handle of new PT endpoint
- *
- * \return standard error codes
- *
- *--------------------------------------------------------------------*/
-extern int
-efrm_filter_resource_set_ptresource(struct filter_resource *frs,
- struct vi_resource *virs);
+extern void
+efrm_filter_resource_release(struct filter_resource *);
-extern int efrm_filter_resource_clear(struct filter_resource *frs);
-extern int __efrm_filter_resource_set(struct filter_resource *frs, int type,
- unsigned saddr_be32, uint16_t sport_be16,
- unsigned daddr_be32, uint16_t dport_be16);
+extern int efrm_filter_resource_clear(struct filter_resource *frs);
-static inline int
-efrm_filter_resource_tcp_set(struct filter_resource *frs,
- unsigned saddr, uint16_t sport,
- unsigned daddr, uint16_t dport)
-{
- int type;
+extern int efrm_filter_resource_ip_set(struct filter_resource *frs,
+ int protocol,
+ unsigned saddr_be32, int sport_be16,
+ unsigned daddr_be32, int dport_be16);
- EFRM_ASSERT((saddr && sport) || (!saddr && !sport));
+extern int efrm_filter_resource_set(struct filter_resource *frs, int type,
+ unsigned saddr_be32, int sport_be16,
+ unsigned daddr_be32, int dport_be16);
- type =
- saddr ? EFHW_IP_FILTER_TYPE_TCP_FULL :
- EFHW_IP_FILTER_TYPE_TCP_WILDCARD;
+extern void efrm_filter_resource_redirect(struct filter_resource *frs,
+ struct vi_resource *vi);
- return __efrm_filter_resource_set(frs, type,
- saddr, sport, daddr, dport);
-}
+extern int
+efrm_filter_resource_instance(struct filter_resource *);
-static inline int
-efrm_filter_resource_udp_set(struct filter_resource *frs,
- unsigned saddr, uint16_t sport,
- unsigned daddr, uint16_t dport)
-{
- int type;
+extern struct efrm_resource *
+efrm_filter_resource_to_resource(struct filter_resource *);
- EFRM_ASSERT((saddr && sport) || (!saddr && !sport));
+extern struct filter_resource *
+efrm_filter_resource_from_resource(struct efrm_resource *);
- type =
- saddr ? EFHW_IP_FILTER_TYPE_UDP_FULL :
- EFHW_IP_FILTER_TYPE_UDP_WILDCARD;
+extern void
+efrm_filter_resource_free(struct filter_resource *);
- return __efrm_filter_resource_set(frs,
- type, saddr, sport, daddr, dport);
-}
#endif /* __CI_EFRM_FILTER_H__ */
/*! \cidoxg_end */
*
* This file provides public API for iobufset resource.
*
- * Copyright 2005-2007: Solarflare Communications Inc,
+ * Copyright 2005-2010: Solarflare Communications Inc,
* 9501 Jeronimo Road, Suite 250,
* Irvine, CA 92618, USA
*
struct iobufset_resource {
struct efrm_resource rs;
struct vi_resource *evq;
+ struct iobufset_resource *linked;
struct efhw_buffer_table_allocation buf_tbl_alloc;
- unsigned int faultonaccess;
unsigned int n_bufs;
unsigned int pages_per_contiguous_chunk;
- unsigned order;
+ unsigned chunk_order;
struct efhw_iopage bufs[1];
/*!< up to n_bufs can follow this, so this must be the last member */
};
/*!
* Allocate iobufset resource.
*
- * \param vi_evq VI resource to use. The function takes
- * reference to the VI resource on success.
- * \param iobrs_out pointer to return the new filter resource
+ * \param vi VI that "owns" these buffers. Grabs a reference
+ * on success.
+ * \param linked Uses memory from an existing iobufset. Grabs a
+ * reference on success.
+ * \param iobrs_out pointer to return the new filter resource
*
* \return status code; if non-zero, frs_out is unchanged
*/
extern int
efrm_iobufset_resource_alloc(int32_t n_pages,
int32_t pages_per_contiguous_chunk,
- struct vi_resource *vi_evq,
+ struct vi_resource *vi,
+ struct iobufset_resource *linked,
bool phys_addr_mode,
- uint32_t faultonaccess,
struct iobufset_resource **iobrs_out);
-/* efrm_iobufset_resource_free should be called only if
- * __efrm_resource_ref_count_zero() returned true.
- * The easiest way is to call efrm_iobufset_resource_release() */
-void efrm_iobufset_resource_free(struct iobufset_resource *rs);
-static inline void
-efrm_iobufset_resource_release(struct iobufset_resource *iobrs)
-{
- unsigned id;
-
- EFRM_RESOURCE_ASSERT_VALID(&iobrs->rs, 0);
- id = EFRM_RESOURCE_INSTANCE(iobrs->rs.rs_handle);
-
- if (atomic_dec_and_test(&iobrs->rs.rs_ref_count)) {
- if (__efrm_resource_ref_count_zero(EFRM_RESOURCE_IOBUFSET, id))
- efrm_iobufset_resource_free(iobrs);
- }
-}
+extern void efrm_iobufset_resource_free(struct iobufset_resource *);
+extern void efrm_iobufset_resource_release(struct iobufset_resource *);
static inline char *
efrm_iobufset_ptr(struct iobufset_resource *rs, unsigned offs)
*
* This file provides public API for NIC sets.
*
- * Copyright 2005-2007: Solarflare Communications Inc,
+ * Copyright 2005-2010: Solarflare Communications Inc,
* 9501 Jeronimo Road, Suite 250,
* Irvine, CA 92618, USA
*
*
* This file provides public API for NIC table.
*
- * Copyright 2005-2007: Solarflare Communications Inc,
+ * Copyright 2005-2010: Solarflare Communications Inc,
* 9501 Jeronimo Road, Suite 250,
* Irvine, CA 92618, USA
*
static inline int efrm_nic_table_held(void)
{
- return (atomic_read(&efrm_nic_tablep->ref_count) != 0);
+ return atomic_read(&efrm_nic_tablep->ref_count) != 0;
}
/* Run code block _x multiple times with variable nic set to each
* This file provides private API of efrm library -- resource handling.
* This API is not designed for use outside of SFC resource driver.
*
- * Copyright 2005-2007: Solarflare Communications Inc,
+ * Copyright 2005-2010: Solarflare Communications Inc,
* 9501 Jeronimo Road, Suite 250,
* Irvine, CA 92618, USA
*
efrm_create_vi_resource_manager(struct efrm_resource_manager **out,
const struct vi_resource_dimensions *);
-/*--------------------------------------------------------------------
- *
- * efrm_resource_handle_t handling
- *
- *--------------------------------------------------------------------*/
-
-/*! Initialize an area of memory to be used as a resource */
-static inline void efrm_resource_init(struct efrm_resource *rs,
- int type, int instance)
-{
- EFRM_ASSERT(instance >= 0);
- EFRM_ASSERT(type >= 0 && type < EFRM_RESOURCE_NUM);
- atomic_set(&rs->rs_ref_count, 1);
- rs->rs_handle.handle = (type << 28u) |
- (((unsigned)jiffies & 0xfff) << 16) | instance;
-}
/*--------------------------------------------------------------------
*
unsigned int i;
struct kfifo *ids;
unsigned char *buffer;
-#ifndef TCP_CHIMNEY_SUPPORT
unsigned int size = roundup_pow_of_two((limit - base) * sizeof(int));
-#else
- /* ### TODO - Linux kfifos really are a power of two, sysdep_ci2linux
- does ci_fifo2's, which only actually hold 2^n - 1.
- We need to double buffer size, not add one, because
- ci_fifo2 can only be a power of two. */
- unsigned int size = roundup_pow_of_two((limit - base) * 2 * sizeof(int));
-#endif
-
EFRM_ASSERT(base <= limit);
buffer = vmalloc(size);
ids = kfifo_init(buffer, size, GFP_KERNEL, lock);
extern int
efrm_resource_manager_ctor(struct efrm_resource_manager *rm,
void (*dtor)(struct efrm_resource_manager *),
- const char *name, unsigned type,
- int initial_table_size);
+ const char *name, unsigned type);
extern void efrm_resource_manager_dtor(struct efrm_resource_manager *rm);
-/*! Insert a resource into table in the resource manager.
- *
- * Caller should free the resource if this function returns non-zero.
- */
-extern int efrm_resource_manager_insert(struct efrm_resource *rs);
#endif /* __CI_EFRM_PRIVATE_H__ */
*
* This file provides public interface of efrm library -- resource handling.
*
- * Copyright 2005-2007: Solarflare Communications Inc,
+ * Copyright 2005-2010: Solarflare Communications Inc,
* 9501 Jeronimo Road, Suite 250,
* Irvine, CA 92618, USA
*
/*! Representation of an allocated resource */
struct efrm_resource {
- atomic_t rs_ref_count; /*!< users count; see
- * __efrm_resource_ref_count_zero() */
+ int rs_ref_count;
efrm_resource_handle_t rs_handle;
+ struct efrm_client *rs_client;
+ struct list_head rs_client_link;
+ struct list_head rs_manager_link;
};
/*--------------------------------------------------------------------
#endif
int rm_resources;
int rm_resources_hiwat;
- /*! table of allocated resources */
- struct efrm_resource **rm_table;
- unsigned rm_table_size;
+ struct list_head rm_resources_list;
/**
* Destructor for the resource manager. Other resource managers
* might be already dead, although the system guarantees that
efrm_resource_manager_assert_valid((rm), __FILE__, __LINE__)
#endif
-/*! Check the reference count on the resource provided and delete its
- * handle it in its owning resource manager if the
- * reference count has fallen to zero.
- *
- * Returns TRUE if the caller should really free the resource.
- */
-extern bool __efrm_resource_ref_count_zero(unsigned type, unsigned instance);
+
+extern void efrm_resource_ref(struct efrm_resource *rs);
+extern int __efrm_resource_release(struct efrm_resource *);
+
#endif /* __CI_EFRM_RESOURCE_H__ */
* This file provides public type and definitions resource handle, and the
* definitions of resource types.
*
- * Copyright 2005-2007: Solarflare Communications Inc,
+ * Copyright 2005-2010: Solarflare Communications Inc,
* 9501 Jeronimo Road, Suite 250,
* Irvine, CA 92618, USA
*
static inline unsigned EFRM_RESOURCE_PRI_ARG(efrm_resource_handle_t h)
{
- return (h.handle);
+ return h.handle;
}
static inline unsigned EFRM_RESOURCE_INSTANCE(efrm_resource_handle_t h)
{
- return (h.handle & 0x0000ffff);
+ return h.handle & 0x0000ffff;
}
static inline unsigned EFRM_RESOURCE_TYPE(efrm_resource_handle_t h)
*
* This file provides Linux-like system-independent API for efrm library.
*
- * Copyright 2005-2007: Solarflare Communications Inc,
+ * Copyright 2005-2010: Solarflare Communications Inc,
* 9501 Jeronimo Road, Suite 250,
* Irvine, CA 92618, USA
*
/* Spinlocks are defined in efhw/sysdep.h */
#include <ci/efhw/sysdep.h>
-
-# include <ci/efrm/sysdep_linux.h>
-
+#include <ci/efrm/sysdep_linux.h>
#endif /* __CI_EFRM_SYSDEP_H__ */
* This file provides version-independent Linux kernel API for efrm library.
* Only kernels >=2.6.9 are supported.
*
- * Copyright 2005-2007: Solarflare Communications Inc,
+ * Copyright 2005-2010: Solarflare Communications Inc,
* 9501 Jeronimo Road, Suite 250,
* Irvine, CA 92618, USA
*
#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,9))
static inline unsigned long __attribute_const__ roundup_pow_of_two(unsigned long x)
{
- return (1UL << fls(x - 1));
+ return 1UL << fls(x - 1);
}
#endif
*
********************************************************************/
-#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,10)
-
-#if !defined(RHEL_RELEASE_CODE) || (RHEL_RELEASE_CODE < 1029)
-typedef unsigned gfp_t;
-#endif
-
-#define HAS_NO_KFIFO
+#ifdef EFX_NEED_KFIFO
struct kfifo {
unsigned char *buffer; /* the buffer holding the data */
}
#else
-#include <linux/kfifo.h>
+# include <linux/kfifo.h>
#endif
static inline void kfifo_vfree(struct kfifo *fifo)
*
* This file contains public API for VI resource.
*
- * Copyright 2005-2007: Solarflare Communications Inc,
+ * Copyright 2005-2010: Solarflare Communications Inc,
* 9501 Jeronimo Road, Suite 250,
* Irvine, CA 92618, USA
*
EFRM_RESOURCE_PRI_ARG(efrm_from_vi_resource(virs)->rs_handle)
extern int
-efrm_vi_resource_alloc(struct vi_resource *evq_virs,
- uint16_t vi_flags, int32_t evq_capacity,
- int32_t txq_capacity, int32_t rxq_capacity,
- uint8_t tx_q_tag, uint8_t rx_q_tag,
+efrm_vi_resource_alloc(struct efrm_client *client,
+ struct vi_resource *evq_virs,
+ unsigned vi_flags, int evq_capacity,
+ int txq_capacity, int rxq_capacity,
+ int tx_q_tag, int rx_q_tag,
struct vi_resource **virs_in_out,
uint32_t *out_io_mmap_bytes,
uint32_t *out_mem_mmap_bytes,
uint32_t *out_txq_capacity,
uint32_t *out_rxq_capacity);
-static inline void efrm_vi_resource_ref(struct vi_resource *virs)
-{
- atomic_inc(&efrm_from_vi_resource(virs)->rs_ref_count);
-}
+extern void efrm_vi_resource_free(struct vi_resource *);
+extern void efrm_vi_resource_release(struct vi_resource *);
-/* efrm_vi_resource_free should be called only if
- * __efrm_resource_ref_count_zero() returned true.
- * The easiest way is to call efrm_vi_resource_release() */
-extern void efrm_vi_resource_free(struct vi_resource *virs);
-static inline void efrm_vi_resource_release(struct vi_resource *virs)
-{
- unsigned id;
- struct efrm_resource *rs = efrm_from_vi_resource(virs);
-
- id = EFRM_RESOURCE_INSTANCE(rs->rs_handle);
-
- if (atomic_dec_and_test(&rs->rs_ref_count)) {
- if (__efrm_resource_ref_count_zero(EFRM_RESOURCE_VI, id)) {
- EFRM_ASSERT(EFRM_RESOURCE_INSTANCE(rs->rs_handle) ==
- id);
- efrm_vi_resource_free(virs);
- }
- }
-}
/*--------------------------------------------------------------------
*
*--------------------------------------------------------------------*/
/*! Reset an event queue and clear any associated timers */
-extern void efrm_eventq_reset(struct vi_resource *virs, int nic_index);
+extern void efrm_eventq_reset(struct vi_resource *virs);
/*! Register a kernel-level handler for the event queue. This function is
* called whenever a timer expires, or whenever the event queue is woken
/*! Ask the NIC to generate a wakeup when an event is next delivered. */
extern void efrm_eventq_request_wakeup(struct vi_resource *rs,
- unsigned current_ptr,
- unsigned nic_index);
+ unsigned current_ptr);
/*! Register a kernel-level handler for flush completions.
* \TODO Currently, it is unsafe to install a callback more than once.
void (*handler)(void *),
void *arg);
-int efrm_vi_resource_flush_retry(struct vi_resource *virs);
-
/*! Comment? */
-extern int efrm_pt_flush(struct vi_resource *);
+extern void efrm_pt_flush(struct vi_resource *);
/*! Comment? */
extern int efrm_pt_pace(struct vi_resource *, unsigned int val);
uint32_t efrm_vi_rm_txq_bytes(struct vi_resource *virs
- /*,struct efhw_nic *nic */ );
+ /*,struct efhw_nic *nic */);
uint32_t efrm_vi_rm_rxq_bytes(struct vi_resource *virs
- /*,struct efhw_nic *nic */ );
+ /*,struct efhw_nic *nic */);
uint32_t efrm_vi_rm_evq_bytes(struct vi_resource *virs
- /*,struct efhw_nic *nic */ );
+ /*,struct efhw_nic *nic */);
/* Fill [out_vi_data] with information required to allow a VI to be init'd.
* [out_vi_data] must ref at least VI_MAPPINGS_SIZE bytes.
*/
-extern void efrm_vi_resource_mappings(struct vi_resource*, int nic_i,
- void* out_vi_data);
+extern void efrm_vi_resource_mappings(struct vi_resource *, void *out_vi_data);
#endif /* __CI_EFRM_VI_RESOURCE_H__ */
* may be used outside of the SFC resource driver, but such use is not
* recommended.
*
- * Copyright 2005-2007: Solarflare Communications Inc,
+ * Copyright 2005-2010: Solarflare Communications Inc,
* 9501 Jeronimo Road, Suite 250,
* Irvine, CA 92618, USA
*
#include <ci/efhw/common.h>
#include <ci/efrm/vi_resource.h>
-#include <ci/efrm/nic_set.h>
+
#define EFRM_VI_RM_DMA_QUEUE_COUNT 2
#define EFRM_VI_RM_DMA_QUEUE_TX 0
#define VI_RESOURCE_EVQ_STATE(X) \
(((int32_t)1) << (VI_RESOURCE_EVQ_STATE_##X))
-/** Information about an event queue. */
-struct vi_resource_evq_info {
- /** Flag bits indicating the state of wakeups. */
- unsigned long evq_state;
- /** A pointer to the resource instance for this queue. This member
- * is only valid if evq_state is non-zero or the resource is known
- * to have a non-zero reference count. */
- struct vi_resource *evq_virs;
-};
+#ifdef __ci_ul_driver__
+#define EFRM_VI_USE_WORKQUEUE 0
+#else
#define EFRM_VI_USE_WORKQUEUE 1
+#endif
/*! Global information for the VI resource manager. */
struct vi_resource_manager {
int with_interrupt_limit;
bool iscsi_dmaq_instance_is_free;
- struct vi_resource_evq_info *evq_infos;
/* We keep VI resources which need flushing on these lists. The VI
* is put on the outstanding list when the flush request is issued
#endif
};
-struct vi_resource_nic_info {
- struct eventq_resource_hardware evq_pages;
-#if defined(__CI_HARDWARE_CONFIG_FALCON__)
- struct efhw_iopages dmaq_pages[EFRM_VI_RM_DMA_QUEUE_COUNT];
-#endif
-};
struct vi_resource {
/* Some macros make the assumption that the struct efrm_resource is
struct efrm_resource rs;
atomic_t evq_refs; /*!< Number of users of the event queue. */
- efrm_nic_set_t nic_set;
-
uint32_t bar_mmap_bytes;
uint32_t mem_mmap_bytes;
- int32_t evq_capacity;
- int32_t dmaq_capacity[EFRM_VI_RM_DMA_QUEUE_COUNT];
-
+ int evq_capacity;
+ int dmaq_capacity[EFRM_VI_RM_DMA_QUEUE_COUNT];
uint8_t dmaq_tag[EFRM_VI_RM_DMA_QUEUE_COUNT];
- uint16_t flags;
+ unsigned flags;
/* we keep PT endpoints that have been destroyed on a list
* until we have seen their TX and RX DMAQs flush complete
*/
struct list_head rx_flush_link;
struct list_head tx_flush_link;
- efrm_nic_set_t rx_flush_nic_set;
- efrm_nic_set_t rx_flush_outstanding_nic_set;
- efrm_nic_set_t tx_flush_nic_set;
+ int rx_flushing;
+ int rx_flush_outstanding;
+ int tx_flushing;
uint64_t flush_time;
int flush_count;
struct vi_resource *evq_virs; /*!< EVQ for DMA queues */
-#if defined(__CI_HARDWARE_CONFIG_FALCON__)
- struct efhw_buffer_table_allocation
- dmaq_buf_tbl_alloc[EFRM_VI_RM_DMA_QUEUE_COUNT];
-#endif
-
- struct vi_resource_nic_info nic_info[EFHW_MAX_NR_DEVS];
+ struct eventq_resource_hardware evq_hw;
+ struct efhw_iopages dmaq_pages[EFRM_VI_RM_DMA_QUEUE_COUNT];
+ struct efhw_buffer_table_allocation
+ dmaq_buf_tbl_alloc[EFRM_VI_RM_DMA_QUEUE_COUNT];
};
#undef vi_resource
#define vi_resource(rs1) container_of((rs1), struct vi_resource, rs)
-static inline dma_addr_t
-efrm_eventq_dma_addr(struct vi_resource *virs, uint32_t nic_index)
-{
- struct eventq_resource_hardware *hw;
- EFRM_ASSERT(efrm_nic_set_read(&virs->nic_set, nic_index));
-
- hw = &(virs->nic_info[nic_index].evq_pages);
-
- return efhw_iopages_dma_addr(&(hw->iobuff)) + hw->iobuff_off;
-}
#endif /* __CI_DRIVER_EFAB_VI_RESOURCE_MANAGER_H__ */
* This file contains private API for VI resource. The API is not designed
* to be used outside of the SFC resource driver.
*
- * Copyright 2005-2007: Solarflare Communications Inc,
+ * Copyright 2005-2010: Solarflare Communications Inc,
* 9501 Jeronimo Road, Suite 250,
* Irvine, CA 92618, USA
*
void efrm_vi_rm_init_dmaq(struct vi_resource *virs, int queue_index,
struct efhw_nic *nic);
-static inline int
-efrm_eventq_bytes(struct vi_resource *virs, uint32_t nic_index)
-{
- EFRM_ASSERT(efrm_nic_set_read(&virs->nic_set, nic_index));
-
- return efrm_vi_rm_evq_bytes(virs);
-}
-
-static inline efhw_event_t *
-efrm_eventq_base(struct vi_resource *virs, uint32_t nic_index)
-{
- struct eventq_resource_hardware *hw;
-
- EFRM_ASSERT(efrm_nic_set_read(&virs->nic_set, nic_index));
-
- hw = &(virs->nic_info[nic_index].evq_pages);
-
- return (efhw_event_t *) (efhw_iopages_ptr(&(hw->iobuff)) +
- hw->iobuff_off);
-}
-
/*! Wakeup handler */
extern void efrm_handle_wakeup_event(struct efhw_nic *nic, unsigned id);
/*! DMA flush handler */
extern void efrm_handle_dmaq_flushed(struct efhw_nic *nic, unsigned id,
- int rx_flush);
+ int rx_flush, int failed);
/*! SRAM update handler */
extern void efrm_handle_sram_event(struct efhw_nic *nic);
*
* This file contains support for the global driver variables.
*
- * Copyright 2005-2007: Solarflare Communications Inc,
+ * Copyright 2005-2010: Solarflare Communications Inc,
* 9501 Jeronimo Road, Suite 250,
* Irvine, CA 92618, USA
*
#include <ci/efrm/nic_table.h>
#include <ci/efrm/resource.h>
#include <ci/efrm/debug.h>
+#include <ci/efrm/efrm_client.h>
+#include <ci/efrm/efrm_nic.h>
+#include "efrm_internal.h"
/* We use #define rather than static inline here so that the Windows
* "prefast" compiler can see its own locking primitive when these
struct efrm_nic_table *efrm_nic_tablep;
EXPORT_SYMBOL(efrm_nic_tablep);
+
/* Internal table with resource managers.
* We'd like to not export it, but we are still using efrm_rm_table
* in the char driver. So, it is declared in the private header with
struct efrm_resource_manager *efrm_rm_table[EFRM_RESOURCE_NUM];
EXPORT_SYMBOL(efrm_rm_table);
-int efrm_driver_ctor(void)
+
+/* List of registered nics. */
+static LIST_HEAD(efrm_nics);
+
+
+void efrm_driver_ctor(void)
{
- efrm_nic_tablep = &efrm_nic_table;
+ efrm_nic_tablep = &efrm_nic_table;
spin_lock_init(&efrm_nic_tablep->lock);
-
EFRM_TRACE("%s: driver created", __FUNCTION__);
- return 0;
}
-int efrm_driver_dtor(void)
+void efrm_driver_dtor(void)
{
EFRM_ASSERT(!efrm_nic_table_held());
spin_lock_destroy(&efrm_nic_tablep->lock);
memset(&efrm_nic_table, 0, sizeof(efrm_nic_table));
memset(&efrm_rm_table, 0, sizeof(efrm_rm_table));
-
EFRM_TRACE("%s: driver deleted", __FUNCTION__);
- return 0;
}
-int efrm_driver_register_nic(struct efhw_nic *nic, int nic_index)
+int efrm_driver_register_nic(struct efrm_nic *rnic, int nic_index,
+ int ifindex)
{
- int rc = 0;
+ struct efhw_nic *nic = &rnic->efhw_nic;
+ struct efrm_nic_per_vi *vis;
+ int max_vis, rc = 0;
irq_flags_t lock_flags;
EFRM_ASSERT(nic_index >= 0);
+ EFRM_ASSERT(ifindex >= 0);
+
+ max_vis = 4096; /* TODO: Get runtime value. */
+ vis = vmalloc(max_vis * sizeof(rnic->vis[0]));
+ if (vis == NULL) {
+ EFRM_ERR("%s: Out of memory", __FUNCTION__);
+ return -ENOMEM;
+ }
+ memset(vis, 0, max_vis * sizeof(vis[0]));
efrm_driver_lock(lock_flags);
if (efrm_nic_table_held()) {
- EFRM_WARN("%s: driver object is in use", __FUNCTION__);
+ EFRM_ERR("%s: driver object is in use", __FUNCTION__);
rc = -EBUSY;
goto done;
}
if (efrm_nic_tablep->nic_count == EFHW_MAX_NR_DEVS) {
- EFRM_WARN("%s: filled up NIC table size %d", __FUNCTION__,
- EFHW_MAX_NR_DEVS);
+ EFRM_ERR("%s: filled up NIC table size %d", __FUNCTION__,
+ EFHW_MAX_NR_DEVS);
rc = -E2BIG;
goto done;
}
+ rnic->vis = vis;
+
EFRM_ASSERT(efrm_nic_tablep->nic[nic_index] == NULL);
efrm_nic_tablep->nic[nic_index] = nic;
nic->index = nic_index;
+ nic->ifindex = ifindex;
if (efrm_nic_tablep->a_nic == NULL)
efrm_nic_tablep->a_nic = nic;
efrm_nic_tablep->nic_count++;
+
+ INIT_LIST_HEAD(&rnic->clients);
+ list_add(&rnic->link, &efrm_nics);
+
efrm_driver_unlock(lock_flags);
- return rc;
+ return 0;
done:
efrm_driver_unlock(lock_flags);
+ vfree(vis);
return rc;
}
-int efrm_driver_unregister_nic(struct efhw_nic *nic)
+int efrm_driver_unregister_nic(struct efrm_nic *rnic)
{
+ struct efhw_nic *nic = &rnic->efhw_nic;
int rc = 0;
int nic_index = nic->index;
irq_flags_t lock_flags;
efrm_driver_lock(lock_flags);
if (efrm_nic_table_held()) {
- EFRM_WARN("%s: driver object is in use", __FUNCTION__);
+ EFRM_ERR("%s: driver object is in use", __FUNCTION__);
+ rc = -EBUSY;
+ goto done;
+ }
+ if (!list_empty(&rnic->clients)) {
+ EFRM_ERR("%s: nic has active clients", __FUNCTION__);
rc = -EBUSY;
goto done;
}
EFRM_ASSERT(efrm_nic_tablep->nic[nic_index] == nic);
+ EFRM_ASSERT(list_empty(&rnic->clients));
+
+ list_del(&rnic->link);
nic->index = -1;
efrm_nic_tablep->nic[nic_index] = NULL;
efrm_driver_unlock(lock_flags);
return rc;
}
+
+
+#ifdef __KERNEL__
+
+
+int efrm_nic_pre_reset(struct efhw_nic *nic)
+{
+ struct efrm_nic *rnic = efrm_nic(nic);
+ struct efrm_client *client;
+ struct efrm_resource *rs;
+ struct list_head *client_link;
+ struct list_head *rs_link;
+ irq_flags_t lock_flags;
+
+ spin_lock_irqsave(&efrm_nic_tablep->lock, lock_flags);
+ list_for_each(client_link, &rnic->clients) {
+ client = container_of(client_link, struct efrm_client, link);
+ EFRM_ERR("%s: client %p", __FUNCTION__, client);
+ if (client->callbacks->pre_reset)
+ client->callbacks->pre_reset(client, client->user_data);
+ list_for_each(rs_link, &client->resources) {
+ rs = container_of(rs_link, struct efrm_resource,
+ rs_client_link);
+ EFRM_ERR("%s: resource %p", __FUNCTION__, rs);
+ /* TODO: mark rs defunct */
+ }
+ }
+ spin_unlock_irqrestore(&efrm_nic_tablep->lock, lock_flags);
+
+ return 0;
+}
+
+
+int efrm_nic_stop(struct efhw_nic *nic)
+{
+ /* TODO */
+ return 0;
+}
+
+
+int efrm_nic_resume(struct efhw_nic *nic)
+{
+ /* TODO */
+ return 0;
+}
+
+
+static void efrm_client_nullcb(struct efrm_client *client, void *user_data)
+{
+}
+
+static struct efrm_client_callbacks efrm_null_callbacks = {
+ efrm_client_nullcb,
+ efrm_client_nullcb,
+ efrm_client_nullcb
+};
+
+
+int efrm_client_get(int ifindex, struct efrm_client_callbacks *callbacks,
+ void *user_data, struct efrm_client **client_out)
+{
+ struct efrm_nic *n, *rnic = NULL;
+ irq_flags_t lock_flags;
+ struct list_head *link;
+ struct efrm_client *client;
+
+ if (callbacks == NULL)
+ callbacks = &efrm_null_callbacks;
+
+ client = kmalloc(sizeof(*client), GFP_KERNEL);
+ if (client == NULL)
+ return -ENOMEM;
+
+ spin_lock_irqsave(&efrm_nic_tablep->lock, lock_flags);
+ list_for_each(link, &efrm_nics) {
+ n = container_of(link, struct efrm_nic, link);
+ if (n->efhw_nic.ifindex == ifindex || ifindex < 0) {
+ rnic = n;
+ break;
+ }
+ }
+ if (rnic) {
+ client->user_data = user_data;
+ client->callbacks = callbacks;
+ client->nic = &rnic->efhw_nic;
+ client->ref_count = 1;
+ INIT_LIST_HEAD(&client->resources);
+ list_add(&client->link, &rnic->clients);
+ }
+ spin_unlock_irqrestore(&efrm_nic_tablep->lock, lock_flags);
+
+ if (rnic == NULL)
+ return -ENODEV;
+
+ *client_out = client;
+ return 0;
+}
+EXPORT_SYMBOL(efrm_client_get);
+
+
+void efrm_client_put(struct efrm_client *client)
+{
+ irq_flags_t lock_flags;
+
+ EFRM_ASSERT(client->ref_count > 0);
+
+ spin_lock_irqsave(&efrm_nic_tablep->lock, lock_flags);
+ if (--client->ref_count > 0)
+ client = NULL;
+ else
+ list_del(&client->link);
+ spin_unlock_irqrestore(&efrm_nic_tablep->lock, lock_flags);
+ kfree(client);
+}
+EXPORT_SYMBOL(efrm_client_put);
+
+
+struct efhw_nic *efrm_client_get_nic(struct efrm_client *client)
+{
+ return client->nic;
+}
+EXPORT_SYMBOL(efrm_client_get_nic);
+
+
+int efrm_client_get_ifindex(struct efrm_client *client)
+{
+ return client->nic->ifindex;
+}
+EXPORT_SYMBOL(efrm_client_get_ifindex);
+
+
+#endif /* __KERNEL__ */
* This file contains driverlink code which interacts with the sfc network
* driver.
*
- * Copyright 2005-2007: Solarflare Communications Inc,
+ * Copyright 2005-2010: Solarflare Communications Inc,
* 9501 Jeronimo Road, Suite 250,
* Irvine, CA 92618, USA
*
#include <linux/rtnetlink.h>
#include <linux/netdevice.h>
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,26)
+# include <net/net_namespace.h>
+#endif
/* The DL driver and associated calls */
static int efrm_dl_probe(struct efx_dl_device *efrm_dev,
res->txq_lim);
}
-/* We have a module parameter that can tell us to only load the char driver
- * for 1 NIC (if there are multiple NICs in the system), and if so which one.
- * This tells us the PCI bus and slot of the NIC to load for, or -1 to just
- * load on all NICs (the default).
- * Value is a hex number in the format
- * bbbbss
- * where:
- * bbbb - PCI bus number
- * ss - PCI slot number
- */
-unsigned int only_NIC = -1;
-
-/** @ingroup module_params */
-module_param(only_NIC, uint, 0444);
-MODULE_PARM_DESC(only_NIC,
- "Initialise sfc_resource driver for one NIC only, "
- "with specified PCI bus and slot");
-
static int
efrm_dl_probe(struct efx_dl_device *efrm_dev,
const struct net_device *net_dev,
if (res == NULL) {
EFRM_ERR("%s: Unable to find falcon driverlink resources",
- __FUNCTION__);
+ __func__);
return -EINVAL;
}
if (res->flags & EFX_DL_FALCON_USE_MSI)
probe_flags |= NIC_FLAG_TRY_MSI;
-#if defined(EFX_NOT_UPSTREAM)
- if (only_NIC != -1 &&
- (efrm_dev->pci_dev->bus->number !=
- ((only_NIC >> 8) & 0xFFFF)
- || PCI_SLOT(efrm_dev->pci_dev->devfn) !=
- (only_NIC & 0xFF))) {
- EFRM_NOTICE("Hiding char device %x:%x",
- efrm_dev->pci_dev->bus->number,
- PCI_SLOT(efrm_dev->pci_dev->devfn));
- return -ENODEV;
- }
-#endif
-
dev = efrm_dev->pci_dev;
if (res->flags & EFX_DL_FALCON_DUAL_FUNC) {
unsigned vendor = dev->vendor;
}
if (dev == NULL) {
EFRM_ERR("%s: Unable to find falcon secondary "
- "PCI device.", __FUNCTION__);
+ "PCI device.", __func__);
return -ENODEV;
}
pci_dev_put(dev);
init_vi_resource_dimensions(&res_dim, res);
+ /* Use top-most EVQ for SRAM update events etc. */
EFRM_ASSERT(res_dim.evq_timer_lim > res_dim.evq_timer_min);
res_dim.evq_timer_lim--;
non_irq_evq = res_dim.evq_timer_lim;
rc = efrm_nic_add(dev, probe_flags, net_dev->dev_addr, &lnic,
res->biu_lock,
res->buffer_table_min, res->buffer_table_lim,
- non_irq_evq, &res_dim);
+ non_irq_evq, &res_dim, net_dev->ifindex);
if (rc != 0)
return rc;
- nic = &lnic->nic;
+ nic = &lnic->efrm_nic.efhw_nic;
nic->mtu = net_dev->mtu + ETH_HLEN;
- nic->net_driver_dev = efrm_dev;
- nic->ifindex = net_dev->ifindex;
-#ifdef HAS_NET_NAMESPACE
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,26)) && defined(HAS_NET_NAMESPACE)
+ nic->nd_net = net_dev->nd_net;
+#endif
+#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,26)) && defined(CONFIG_NET_NS)
nic->nd_net = net_dev->nd_net;
#endif
efrm_dev->priv = nic;
+ EFRM_NOTICE("%s: index=%d ifindex=%d",
+ __func__, nic->index, nic->ifindex);
+
/* Register a callback so we're told when MTU changes.
* We dynamically allocate efx_dl_callbacks, because
* the callbacks that we want depends on the NIC type.
lnic->dl_callbacks =
kmalloc(sizeof(struct efx_dl_callbacks), GFP_KERNEL);
if (!lnic->dl_callbacks) {
- EFRM_ERR("Out of memory (%s)", __FUNCTION__);
+ EFRM_ERR("Out of memory (%s)", __func__);
efrm_nic_del(lnic);
return -ENOMEM;
}
rc = efx_dl_register_callbacks(efrm_dev, lnic->dl_callbacks);
if (rc < 0) {
EFRM_ERR("%s: efx_dl_register_callbacks failed (%d)",
- __FUNCTION__, rc);
+ __func__, rc);
kfree(lnic->dl_callbacks);
efrm_nic_del(lnic);
return rc;
{
struct efhw_nic *nic = efrm_dev->priv;
struct linux_efhw_nic *lnic = linux_efhw_nic(nic);
- EFRM_TRACE("%s called", __FUNCTION__);
+ EFRM_TRACE("%s called", __func__);
if (lnic->dl_callbacks) {
efx_dl_unregister_callbacks(efrm_dev, lnic->dl_callbacks);
kfree(lnic->dl_callbacks);
}
if (efrm_dev->priv)
efrm_nic_del(lnic);
- EFRM_TRACE("%s OK", __FUNCTION__);
+ EFRM_TRACE("%s OK", __func__);
}
static void efrm_dl_reset_suspend(struct efx_dl_device *efrm_dev)
{
- EFRM_NOTICE("%s:", __FUNCTION__);
+ EFRM_NOTICE("%s:", __func__);
}
static void efrm_dl_reset_resume(struct efx_dl_device *efrm_dev, int ok)
{
- EFRM_NOTICE("%s: ok=%d", __FUNCTION__, ok);
+ EFRM_NOTICE("%s: ok=%d", __func__, ok);
}
int efrm_driverlink_register(void)
{
- EFRM_TRACE("%s:", __FUNCTION__);
+ EFRM_TRACE("%s:", __func__);
return efx_dl_register_driver(&efrm_dl_driver);
}
void efrm_driverlink_unregister(void)
{
- EFRM_TRACE("%s:", __FUNCTION__);
+ EFRM_TRACE("%s:", __func__);
efx_dl_unregister_driver(&efrm_dl_driver);
}
ASSERT_RTNL(); /* Since we're looking at efx_dl_device::port_net_dev */
- EFRM_TRACE("%s: old=%d new=%d", __FUNCTION__, nic->mtu, mtu + ETH_HLEN);
+ EFRM_TRACE("%s: old=%d new=%d", __func__, nic->mtu, mtu + ETH_HLEN);
/* If this happened we must have agreed to it above */
nic->mtu = mtu + ETH_HLEN;
}
falcon_handle_char_event(nic, lnic->ev_handlers, ev);
break;
default:
- EFRM_WARN("%s: unknown event type=%x", __FUNCTION__,
+ EFRM_WARN("%s: unknown event type=%x", __func__,
(unsigned)FALCON_EVENT_CODE(ev));
break;
}
--- /dev/null
+/****************************************************************************
+ * Driver for Solarflare network controllers -
+ * resource management for Xen backend, OpenOnload, etc
+ * (including support for SFE4001 10GBT NIC)
+ *
+ * This file provides helpers to turn bit shifts into dword shifts and
+ * check that the bit fields haven't overflown the dword etc.
+ *
+ * Copyright 2005-2010: Solarflare Communications Inc,
+ * 9501 Jeronimo Road, Suite 250,
+ * Irvine, CA 92618, USA
+ *
+ * Developed and maintained by Solarflare Communications:
+ * <linux-xen-drivers@solarflare.com>
+ * <onload-dev@solarflare.com>
+ *
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation, incorporated herein by reference.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ ****************************************************************************
+ */
+
+#ifndef __EFRM_INTERNAL_H__
+#define __EFRM_INTERNAL_H__
+
+
+struct filter_resource {
+ struct efrm_resource rs;
+ struct vi_resource *pt;
+ int filter_idx;
+};
+
+#define filter_resource(rs1) container_of((rs1), struct filter_resource, rs)
+
+
+struct efrm_client {
+ void *user_data;
+ struct list_head link;
+ struct efrm_client_callbacks *callbacks;
+ struct efhw_nic *nic;
+ int ref_count;
+ struct list_head resources;
+};
+
+
+extern void efrm_client_add_resource(struct efrm_client *,
+ struct efrm_resource *);
+
+extern int efrm_buffer_table_size(void);
+
+
+static inline void efrm_resource_init(struct efrm_resource *rs,
+ int type, int instance)
+{
+ EFRM_ASSERT(instance >= 0);
+ EFRM_ASSERT(type >= 0 && type < EFRM_RESOURCE_NUM);
+ rs->rs_ref_count = 1;
+ rs->rs_handle.handle = (type << 28u) |
+ (((unsigned)jiffies & 0xfff) << 16) | instance;
+}
+
+
+#endif /* __EFRM_INTERNAL_H__ */
* This file provides implementation of EFX VI API, used from Xen
* acceleration driver.
*
- * Copyright 2005-2007: Solarflare Communications Inc,
+ * Copyright 2005-2010: Solarflare Communications Inc,
* 9501 Jeronimo Road, Suite 250,
* Irvine, CA 92618, USA
*
****************************************************************************
*/
+
#include "linux_resource_internal.h"
-#include <ci/efrm/nic_table.h>
#include <ci/efrm/vi_resource_manager.h>
#include <ci/driver/resource/efx_vi.h>
#include <ci/efrm/filter.h>
#include <ci/efrm/buffer_table.h>
+#include <ci/efrm/efrm_client.h>
#include <linux/pci.h>
#include "kernel_compat.h"
struct efx_vi_state {
struct vi_resource *vi_res;
- int nic_index;
+ int ifindex;
+ struct efrm_client *efrm_client;
+ struct efhw_nic *nic;
void (*callback_fn)(void *arg, int is_timeout);
void *callback_arg;
{
int rc;
- rc = efrm_vi_resource_alloc(NULL, EFHW_VI_JUMBO_EN,
+ rc = efrm_vi_resource_alloc(state->efrm_client, NULL, EFHW_VI_JUMBO_EN,
efx_vi_eventq_size,
FALCON_DMA_Q_DEFAULT_TX_SIZE,
FALCON_DMA_Q_DEFAULT_RX_SIZE,
NULL);
if (rc < 0) {
EFRM_ERR("%s: ERROR efrm_vi_resource_alloc error %d",
- __FUNCTION__, rc);
+ __func__, rc);
return rc;
}
&efx_state->fres[i].fres);
if (rc < 0) {
EFRM_ERR("%s: efrm_filter_resource_alloc failed: %d",
- __FUNCTION__, rc);
+ __func__, rc);
while (i > 0) {
i--;
efrm_filter_resource_release(efx_state->
}
#endif
-int efx_vi_alloc(struct efx_vi_state **vih_out, int nic_index)
+int efx_vi_alloc(struct efx_vi_state **vih_out, int ifindex)
{
struct efx_vi_state *efx_state;
int rc;
- BUG_ON(nic_index < 0 || nic_index >= EFHW_MAX_NR_DEVS);
-
efx_state = kmalloc(sizeof(struct efx_vi_state), GFP_KERNEL);
if (!efx_state) {
EFRM_ERR("%s: failed to allocate memory for efx_vi_state",
- __FUNCTION__);
+ __func__);
rc = -ENOMEM;
goto fail;
}
- efx_state->nic_index = nic_index;
+ efx_state->ifindex = ifindex;
+ rc = efrm_client_get(ifindex, NULL, NULL, &efx_state->efrm_client);
+ if (rc < 0) {
+ EFRM_ERR("%s: efrm_client_get(%d) failed: %d", __func__,
+ ifindex, rc);
+ rc = -ENODEV;
+ goto fail_no_ifindex;
+ }
+ efx_state->nic = efrm_client_get_nic(efx_state->efrm_client);
+
init_completion(&efx_state->flush_completion);
/* basically allocate_pt_endpoint() */
rc = alloc_ep(efx_state);
if (rc) {
- EFRM_ERR("%s: alloc_ep failed: %d", __FUNCTION__, rc);
+ EFRM_ERR("%s: alloc_ep failed: %d", __func__, rc);
goto fail_no_pt;
}
#if EFX_VI_STATIC_FILTERS
free_ep(efx_state);
#endif
fail_no_pt:
+ efrm_client_put(efx_state->efrm_client);
+fail_no_ifindex:
kfree(efx_state);
fail:
return rc;
if (efx_state->vi_res)
free_ep(efx_state);
+ efrm_client_put(efx_state->efrm_client);
+
kfree(efx_state);
}
EXPORT_SYMBOL(efx_vi_free);
while (wait_for_completion_timeout(&efx_state->flush_completion, HZ)
== 0)
- efrm_vi_resource_flush_retry(efx_state->vi_res);
+ EFRM_ERR("%s: still waiting for flush to complete", __func__);
/* Bosch the eventq */
- efrm_eventq_reset(efx_state->vi_res, 0);
+ efrm_eventq_reset(efx_state->vi_res);
return;
}
EXPORT_SYMBOL(efx_vi_reset);
if (n_pages != (1 << order)) {
EFRM_WARN("%s: Can only allocate buffers in power of 2 "
- "sizes (not %d)", __FUNCTION__, n_pages);
+ "sizes (not %d)", __func__, n_pages);
return -EINVAL;
}
for (i = 0; i < n_pages; i++) {
/* TODO do we need to get_page() here ? */
- dma_addr = pci_map_page
- (linux_efhw_nic(efrm_nic_tablep->nic[efx_state->nic_index])->
- pci_dev, pages[i], 0, PAGE_SIZE, PCI_DMA_TODEVICE);
+ dma_addr = pci_map_page(linux_efhw_nic(efx_state->nic)->
+ pci_dev, pages[i], 0, PAGE_SIZE,
+ PCI_DMA_TODEVICE);
- efrm_buffer_table_set(&dm_state->bt_handle, i, dma_addr,
- evq_id);
+ efrm_buffer_table_set(&dm_state->bt_handle, efx_state->nic,
+ i, dma_addr, evq_id);
dm_state->dma_addrs[i] = dma_addr;
if (n_pages != (1 << order)) {
EFRM_WARN("%s: Can only allocate buffers in power of 2 "
- "sizes (not %d)", __FUNCTION__, n_pages);
+ "sizes (not %d)", __func__, n_pages);
return -EINVAL;
}
evq_id = EFRM_RESOURCE_INSTANCE(efx_state->vi_res->rs.rs_handle);
#if 0
EFRM_WARN("%s: mapping %d pages to evq %d, bt_ids %d-%d\n",
- __FUNCTION__, n_pages, evq_id,
+ __func__, n_pages, evq_id,
dm_state->bt_handle.base,
dm_state->bt_handle.base + n_pages);
#endif
dma_addr = (dma_addr_t)bus_dev_addrs[i];
- efrm_buffer_table_set(&dm_state->bt_handle, i, dma_addr,
- evq_id);
+ efrm_buffer_table_set(&dm_state->bt_handle, efx_state->nic,
+ i, dma_addr, evq_id);
dm_state->dma_addrs[i] = dma_addr;
efrm_buffer_table_free(&dm_state->bt_handle);
for (i = 0; i < dm_state->n_pages; ++i)
- pci_unmap_page(linux_efhw_nic
- (efrm_nic_tablep->nic[efx_state->nic_index])->pci_dev,
- dm_state->dma_addrs[i], PAGE_SIZE, PCI_DMA_TODEVICE);
+ pci_unmap_page(linux_efhw_nic(efx_state->nic)->pci_dev,
+ dm_state->dma_addrs[i], PAGE_SIZE,
+ PCI_DMA_TODEVICE);
kfree(dm_state->dma_addrs);
kfree(dm_state);
prev = flist;
flist = flist->next;
}
- EFRM_ERR("%s: couldn't find filter", __FUNCTION__);
+ EFRM_ERR("%s: couldn't find filter", __func__);
#else
return efrm_filter_resource_release(fres);
#endif
/* Add the hardware filter. We pass in the source port and address
* as 0 (wildcard) to minimise the number of filters needed. */
- if (protocol == IPPROTO_TCP) {
- rc = efrm_filter_resource_tcp_set(frs, 0, 0, ip_addr_be32,
- port_le16);
- } else {
- rc = efrm_filter_resource_udp_set(frs, 0, 0, ip_addr_be32,
- port_le16);
- }
+ rc = efrm_filter_resource_ip_set(frs, protocol, 0, 0,
+ ip_addr_be32, port_le16);
*fh_out = (struct filter_resource_t *)frs;
struct efx_vi_hw_resource *hw_res_array,
int *length)
{
- EFRM_NOTICE("%s: TODO!", __FUNCTION__);
+ EFRM_NOTICE("%s: TODO!", __func__);
return 0;
}
EXPORT_SYMBOL(efx_vi_hw_resource_get_virt);
-#if defined(__CI_HARDWARE_CONFIG_FALCON__)
int
efx_vi_hw_resource_get_phys(struct efx_vi_state *vih,
struct efx_vi_hw_resource_metadata *mdata,
int *length)
{
struct efx_vi_state *efx_state = vih;
- int i, ni = efx_state->nic_index;
- struct linux_efhw_nic *lnic = linux_efhw_nic(efrm_nic_tablep->nic[ni]);
+ struct linux_efhw_nic *lnic = linux_efhw_nic(efx_state->nic);
unsigned long phys = lnic->ctr_ap_pci_addr;
struct efrm_resource *ep_res = &efx_state->vi_res->rs;
unsigned ep_mmap_bytes;
+ int i;
if (*length < EFX_VI_HW_RESOURCE_MAXSIZE)
return -EINVAL;
- mdata->nic_arch = efrm_nic_tablep->nic[ni]->devtype.arch;
- mdata->nic_variant = efrm_nic_tablep->nic[ni]->devtype.variant;
- mdata->nic_revision = efrm_nic_tablep->nic[ni]->devtype.revision;
+ mdata->nic_arch = efx_state->nic->devtype.arch;
+ mdata->nic_variant = efx_state->nic->devtype.variant;
+ mdata->nic_revision = efx_state->nic->devtype.revision;
- mdata->evq_order =
- efx_state->vi_res->nic_info[ni].evq_pages.iobuff.order;
- mdata->evq_offs = efx_state->vi_res->nic_info[ni].evq_pages.iobuff_off;
+ mdata->evq_order = efx_state->vi_res->evq_hw.iobuff.order;
+ mdata->evq_offs = 0;
mdata->evq_capacity = efx_vi_eventq_size;
mdata->instance = EFRM_RESOURCE_INSTANCE(ep_res->rs_handle);
mdata->rx_capacity = FALCON_DMA_Q_DEFAULT_RX_SIZE;
/* Check the lower bits of the TX doorbell will be
* consistent. */
- EFRM_ASSERT((TX_DESC_UPD_REG_PAGE4_OFST &
+ EFRM_ASSERT((FR_AA_TX_DESC_UPD_REGP0_OFST &
FALCON_DMA_PAGE_MASK) ==
- (TX_DESC_UPD_REG_PAGE123K_OFST &
+ (FR_AB_TX_DESC_UPD_REGP123_OFST &
FALCON_DMA_PAGE_MASK));
/* Check the lower bits of the RX doorbell will be
* consistent. */
- EFRM_ASSERT((RX_DESC_UPD_REG_PAGE4_OFST &
+ EFRM_ASSERT((FR_AA_RX_DESC_UPD_REGP0_OFST &
FALCON_DMA_PAGE_MASK) ==
- (RX_DESC_UPD_REG_PAGE123K_OFST &
+ (FR_AB_RX_DESC_UPD_REGP123_OFST &
FALCON_DMA_PAGE_MASK));
/* Check that the doorbells will be in the same page. */
- EFRM_ASSERT((TX_DESC_UPD_REG_PAGE4_OFST & PAGE_MASK) ==
- (RX_DESC_UPD_REG_PAGE4_OFST & PAGE_MASK));
+ EFRM_ASSERT((FR_AA_TX_DESC_UPD_REGP0_OFST & PAGE_MASK) ==
+ (FR_AA_RX_DESC_UPD_REGP0_OFST & PAGE_MASK));
/* Check that the doorbells are in the same page. */
EFRM_ASSERT((tx_dma_page_addr & PAGE_MASK) ==
(rx_dma_page_addr & PAGE_MASK));
/* Check that the TX doorbell offset is correct. */
- EFRM_ASSERT((TX_DESC_UPD_REG_PAGE4_OFST & ~PAGE_MASK) ==
+ EFRM_ASSERT((FR_AA_TX_DESC_UPD_REGP0_OFST & ~PAGE_MASK) ==
(tx_dma_page_addr & ~PAGE_MASK));
/* Check that the RX doorbell offset is correct. */
- EFRM_ASSERT((RX_DESC_UPD_REG_PAGE4_OFST & ~PAGE_MASK) ==
+ EFRM_ASSERT((FR_AA_RX_DESC_UPD_REGP0_OFST & ~PAGE_MASK) ==
(rx_dma_page_addr & ~PAGE_MASK));
}
#endif
hw_res_array[i].more_to_follow = 0;
hw_res_array[i].length = PAGE_SIZE;
hw_res_array[i].address =
- (unsigned long)efx_state->vi_res->nic_info[ni].
+ (unsigned long)efx_state->vi_res->
dmaq_pages[EFRM_VI_RM_DMA_QUEUE_TX].kva;
i++;
hw_res_array[i].more_to_follow = 0;
hw_res_array[i].length = PAGE_SIZE;
hw_res_array[i].address =
- (unsigned long)efx_state->vi_res->nic_info[ni].
+ (unsigned long)efx_state->vi_res->
dmaq_pages[EFRM_VI_RM_DMA_QUEUE_RX].kva;
i++;
/* NB EFX_VI_HW_RESOURCE_EVQPTR not used on Falcon */
i++;
- switch (efrm_nic_tablep->nic[ni]->devtype.variant) {
+ switch (efx_state->nic->devtype.variant) {
case 'A':
hw_res_array[i].type = EFX_VI_HW_RESOURCE_EVQRPTR;
hw_res_array[i].mem_type = EFX_VI_HW_RESOURCE_PERIPHERAL;
hw_res_array[i].more_to_follow = 0;
hw_res_array[i].length = PAGE_SIZE;
hw_res_array[i].address = (unsigned long)phys +
- EVQ_RPTR_REG_OFST +
+ FR_AZ_EVQ_RPTR_REG_OFST +
(FALCON_REGISTER128 * mdata->instance);
break;
case 'B':
+ case 'C':
hw_res_array[i].type = EFX_VI_HW_RESOURCE_EVQRPTR_OFFSET;
hw_res_array[i].mem_type = EFX_VI_HW_RESOURCE_PERIPHERAL;
hw_res_array[i].more_to_follow = 0;
hw_res_array[i].more_to_follow = 0;
hw_res_array[i].length = PAGE_SIZE;
hw_res_array[i].address = (unsigned long)efx_state->vi_res->
- nic_info[ni].evq_pages.iobuff.kva;
+ evq_hw.iobuff.kva;
i++;
hw_res_array[i].type = EFX_VI_HW_RESOURCE_BELLPAGE;
return 0;
}
EXPORT_SYMBOL(efx_vi_hw_resource_get_phys);
-#endif
*
* This file contains event queue support.
*
- * Copyright 2005-2007: Solarflare Communications Inc,
+ * Copyright 2005-2010: Solarflare Communications Inc,
* 9501 Jeronimo Road, Suite 250,
* Irvine, CA 92618, USA
*
/* Allocate an iobuffer. */
page_order = get_order(buf_bytes);
- h->iobuff_off = 0;
-
EFHW_TRACE("allocating eventq size %x",
1u << (page_order + PAGE_SHIFT));
rc = efhw_iopages_alloc(nic, &h->iobuff, page_order);
/* Set the eventq pages to match EFHW_CLEAR_EVENT() */
if (EFHW_CLEAR_EVENT_VALUE)
- memset(efhw_iopages_ptr(&h->iobuff) + h->iobuff_off,
+ memset(efhw_iopages_ptr(&h->iobuff),
EFHW_CLEAR_EVENT_VALUE, (1u << page_order) * PAGE_SIZE);
EFHW_TRACE("%s: allocated %u pages", __FUNCTION__, 1u << (page_order));
/* Initialise the buffer table entries. */
falcon_nic_buffer_table_set_n(nic, h->buf_tbl_alloc.base,
- efhw_iopages_dma_addr(&h->iobuff) +
- h->iobuff_off, EFHW_NIC_PAGE_SIZE, 0,
+ efhw_iopages_dma_addr(&h->iobuff),
+ EFHW_NIC_PAGE_SIZE, 0,
1 << page_order, 0);
-
- if (evq_instance >= FALCON_EVQ_TBL_RESERVED)
- falcon_nic_buffer_table_confirm(nic);
+ falcon_nic_buffer_table_confirm(nic);
return 0;
}
/* Zero the timer-value for this queue.
AND Tell the nic about the event queue. */
efhw_nic_event_queue_enable(nic, evq->instance, evq->hw.capacity,
- efhw_iopages_dma_addr(&evq->hw.iobuff) +
- evq->hw.iobuff_off,
- evq->hw.buf_tbl_alloc.base);
+ evq->hw.buf_tbl_alloc.base,
+ ev_handlers != NULL /* interrupting */,
+ 1 /* dos protection enable*/);
evq->lock = KEVQ_UNLOCKED;
- evq->evq_base = efhw_iopages_ptr(&evq->hw.iobuff) + evq->hw.iobuff_off;
+ evq->evq_base = efhw_iopages_ptr(&evq->hw.iobuff);
evq->evq_ptr = 0;
evq->evq_mask = (evq->hw.capacity * sizeof(efhw_event_t)) - 1u;
return;
}
- h->dmaq_flushed_fn(nic, instance, false);
+ h->dmaq_flushed_fn(nic, instance, false, false);
}
void
efhw_event_t *evp)
{
unsigned instance = (unsigned)FALCON_EVENT_RX_FLUSH_Q_ID(evp);
+ unsigned failed = (int)FALCON_EVENT_RX_FLUSH_FAIL(evp);
EFHW_TRACE("%s: instance=%d", __FUNCTION__, instance);
if (!h->dmaq_flushed_fn) {
return;
}
- h->dmaq_flushed_fn(nic, instance, true);
+ h->dmaq_flushed_fn(nic, instance, true, failed);
}
void
count++;
switch (FALCON_EVENT_CODE(ev)) {
-
-#if defined(__CI_HARDWARE_CONFIG_FALCON__)
case FALCON_EVENT_CODE_CHAR:
falcon_handle_char_event(nic, q->ev_handlers,
ev);
break;
-#endif
-
default:
EFHW_ERR("efhw_keventq_poll: [%d] UNEXPECTED "
"EVENT:"FALCON_EVENT_FMT,
return count;
clean_exit:
-#if defined(__CI_HARDWARE_CONFIG_FALCON__)
/* Ack the processed events so that this event queue can potentially
raise interrupts again */
- falcon_nic_evq_ack(nic, q->instance,
- (EFHW_EVENT_OFFSET(q, q, 0) / sizeof(efhw_event_t)),
- false);
-#endif
+ if (q->instance == nic->interrupting_evq.instance)
+ falcon_nic_evq_ack(nic, q->instance,
+ (EFHW_EVENT_OFFSET(q, q, 0)
+ / sizeof(efhw_event_t)));
return count;
}
*
* This file contains Falcon hardware support.
*
- * Copyright 2005-2007: Solarflare Communications Inc,
+ * Copyright 2005-2010: Solarflare Communications Inc,
* 9501 Jeronimo Road, Suite 250,
* Irvine, CA 92618, USA
*
/* Read filters back from the hardware to detect corruption. */
#define FALCON_VERIFY_FILTERS 0
-/* options */
+/* The maximum number of time to read to see that a buffer table entry is set */
+/*
+ * This is defined to investigate occasional failed assertion in snapper tests
+ * TODO: review and remove or do properly
+ */
+#define BUG_14512_WA
+
+#define MAX_BUF_TBL_READS 128
+#ifdef BUG_14512_WA
+#define MAX_MAX_BUF_TBL_READS 16*MAX_BUF_TBL_READS
+#endif
+
+/* Options */
#define RX_FILTER_CTL_SRCH_LIMIT_TCP_FULL 8 /* default search limit */
#define RX_FILTER_CTL_SRCH_LIMIT_TCP_WILD 8 /* default search limit */
#define RX_FILTER_CTL_SRCH_LIMIT_UDP_FULL 8 /* default search limit */
#define RX_FILTER_CTL_SRCH_LIMIT_UDP_WILD 8 /* default search limit */
-#define RX_FILTER_CTL_SRCH_FUDGE_WILD 3 /* increase the search limit */
-#define RX_FILTER_CTL_SRCH_FUDGE_FULL 1 /* increase the search limit */
-
-#define FALCON_MAC_SET_TYPE_BY_SPEED 1
+/* ...and some more for Siena only: */
+#define RX_FILTER_CTL_SRCH_LIMIT_MAC_WILD 8 /* default search limit */
+#define RX_FILTER_CTL_SRCH_LIMIT_MAC_FULL 8 /* default search limit */
+#define TX_FILTER_CTL_SRCH_LIMIT_TCP_FULL 8 /* default search limit */
+#define TX_FILTER_CTL_SRCH_LIMIT_TCP_WILD 8 /* default search limit */
+#define TX_FILTER_CTL_SRCH_LIMIT_UDP_FULL 8 /* default search limit */
+#define TX_FILTER_CTL_SRCH_LIMIT_UDP_WILD 8 /* default search limit */
+#define TX_FILTER_CTL_SRCH_LIMIT_MAC_WILD 8 /* default search limit */
+#define TX_FILTER_CTL_SRCH_LIMIT_MAC_FULL 8 /* default search limit */
/* FIXME: We should detect mode at runtime. */
#define FALCON_BUFFER_TABLE_FULL_MODE 1
+/* "Fudge factors" - difference between programmed value and actual depth.
+ * Due to pipelined implementation we need to program H/W with a value that
+ * is larger than the hop limit we want.
+ */
+#define RX_FILTER_CTL_SRCH_FUDGE_WILD 3 /* increase the search limit */
+#define RX_FILTER_CTL_SRCH_FUDGE_FULL 1 /* increase the search limit */
+#define TX_FILTER_CTL_SRCH_FUDGE_WILD 3 /* increase the search limit */
+#define TX_FILTER_CTL_SRCH_FUDGE_FULL 1 /* increase the search limit */
+
/*----------------------------------------------------------------------------
*
* Debug Macros
*
*---------------------------------------------------------------------------*/
-#define _DEBUG_SYM_ static inline
+#ifndef __KERNEL__
+#define _DEBUG_SYM_
+#else
+#define _DEBUG_SYM_ static
+#endif
/*----------------------------------------------------------------------------
*
*
*--------------------------------------------------------------------------*/
+#define Q0_READ(q0, name) \
+ ((unsigned)(((q0) >> name##_LBN) & (__FALCON_MASK64(name##_WIDTH))))
+#define Q0_MASK(name) \
+ ((__FALCON_MASK64(name##_WIDTH)) << name##_LBN)
+#define Q0_VALUE(name, value) \
+ (((uint64_t)(value)) << name##_LBN)
+
+#define Q1_READ(q1, name) \
+ ((unsigned)(((q1) >> (name##_LBN - 64)) & \
+ (__FALCON_MASK64(name##_WIDTH))))
+#define Q1_MASK(name) \
+ ((__FALCON_MASK64(name##_WIDTH)) << (name##_LBN - 64))
+#define Q1_VALUE(name, value) \
+ (((uint64_t)(value)) << (name##_LBN - 64))
+
#define FALCON_REGION_NUM 4 /* number of supported memory regions */
#define FALCON_BUFFER_TBL_HALF_BYTES 4
# define FALCON_USE_SHADOW_BUFFER_TABLE 0
#endif
-#if FALCON_USE_SHADOW_BUFFER_TABLE
-static uint64_t _falcon_buffer_table[FALCON_BUFFER_TBL_NUM];
-#endif
+static void falcon_nic_set_rx_filter_search_limits_needed(struct efhw_nic *);
+static void falcon_nic_set_tx_filter_search_limits_needed(struct efhw_nic *);
+static void falcon_nic_filter_dtor(struct efhw_nic *nic);
+
/*----------------------------------------------------------------------------
*
*/
-/*----------------------------------------------------------------------------
- *
- * Filters static data
- *
- *---------------------------------------------------------------------------*/
-
-/* Defaults are set here to support dma.c */
-static unsigned tcp_full_srch_limit = RX_FILTER_CTL_SRCH_LIMIT_TCP_FULL;
-static unsigned tcp_wild_srch_limit = RX_FILTER_CTL_SRCH_LIMIT_TCP_WILD;
-static unsigned udp_full_srch_limit = RX_FILTER_CTL_SRCH_LIMIT_UDP_FULL;
-static unsigned udp_wild_srch_limit = RX_FILTER_CTL_SRCH_LIMIT_UDP_WILD;
-
-#if FALCON_VERIFY_FILTERS
-static void _falcon_nic_ipfilter_sanity(struct efhw_nic *nic);
-#endif
-
-/*----------------------------------------------------------------------------
- *
- * Filters low-level register interface
- *
- *---------------------------------------------------------------------------*/
-
-/* Build the filter entry */
-static void
-_falcon_nic_ipfilter_build(struct efhw_nic *nic,
- int tcp, int full, int rss_b0, int scat_b0,
- uint filter_i, uint dmaq_id,
- unsigned saddr_le32, unsigned sport_le16,
- unsigned daddr_le32, unsigned dport_le16,
- uint64_t *q0, uint64_t *q1)
-{
- uint64_t v1, v2, v3, v4;
- int type = tcp << 4 | full;
-
- v4 = (((!tcp) << __DW4(TCP_UDP_1_LBN)) |
- (dmaq_id << __DW4(RXQ_ID_1_LBN)));
-
- switch (nic->devtype.variant) {
- case 'A':
- EFHW_ASSERT(!rss_b0);
- break;
- case 'B':
- case 'C':
- v4 |= scat_b0 << __DW4(SCATTER_EN_1_B0_LBN);
- v4 |= rss_b0 << __DW4(RSS_EN_1_B0_LBN);
- break;
- default:
- EFHW_ASSERT(0);
- break;
- }
-
- v3 = daddr_le32;
-
- switch (type) {
-
- case 0x11: /* TCP_FULL */
- case 0x01: /* UDP_FULL */
- v2 = ((dport_le16 << __DW2(DEST_PORT_TCP_1_LBN)) |
- (__HIGH(saddr_le32, SRC_IP_1_LBN, SRC_IP_1_WIDTH)));
- v1 = ((__LOW(saddr_le32, SRC_IP_1_LBN, SRC_IP_1_WIDTH)) |
- (sport_le16 << SRC_TCP_DEST_UDP_1_LBN));
- break;
-
- case 0x10: /* TCP_WILD */
- v2 = ((uint64_t) dport_le16 << __DW2(DEST_PORT_TCP_1_LBN));
- v1 = 0;
- break;
-
- case 0x00: /* UDP_WILD */
- v2 = 0;
- v1 = ((uint64_t) dport_le16 << SRC_TCP_DEST_UDP_0_LBN);
- break;
-
- default:
- EFHW_ASSERT(0);
- v2 = 0;
- v1 = 0;
- }
-
- *q0 = (v2 << 32) | v1;
- *q1 = (v4 << 32) | v3;
-}
-
-static void
-_falcon_nic_ipfilter_set(struct efhw_nic *nic, int tcp,
- int full, int rss_b0, int scat_b0,
- uint filter_i, uint dmaq_id,
- unsigned saddr_le32, unsigned sport_le16,
- unsigned daddr_le32, unsigned dport_le16)
-{
- uint64_t q0, q1;
-
- /* wish you wouldn't do this */
- EFHW_BUILD_ASSERT(RX_FILTER_TBL1_OFST ==
- RX_FILTER_TBL0_OFST + FALCON_REGISTER128);
- EFHW_BUILD_ASSERT(TCP_UDP_1_LBN == TCP_UDP_0_LBN);
- EFHW_BUILD_ASSERT(RXQ_ID_1_LBN == RXQ_ID_0_LBN);
- EFHW_BUILD_ASSERT(DEST_IP_1_LBN == DEST_IP_0_LBN);
- EFHW_BUILD_ASSERT(DEST_PORT_TCP_1_LBN == DEST_PORT_TCP_0_LBN);
- EFHW_BUILD_ASSERT(SRC_IP_1_LBN == SRC_IP_0_LBN);
- EFHW_BUILD_ASSERT(SRC_TCP_DEST_UDP_1_LBN == SRC_TCP_DEST_UDP_0_LBN);
- EFHW_BUILD_ASSERT(SCATTER_EN_1_B0_LBN == SCATTER_EN_0_B0_LBN);
- EFHW_BUILD_ASSERT(RSS_EN_1_B0_LBN == RSS_EN_0_B0_LBN);
-
- EFHW_BUILD_ASSERT(TCP_UDP_1_WIDTH == TCP_UDP_0_WIDTH);
- EFHW_BUILD_ASSERT(RXQ_ID_1_WIDTH == RXQ_ID_0_WIDTH);
- EFHW_BUILD_ASSERT(DEST_IP_1_WIDTH == DEST_IP_0_WIDTH);
- EFHW_BUILD_ASSERT(DEST_PORT_TCP_1_WIDTH == DEST_PORT_TCP_0_WIDTH);
- EFHW_BUILD_ASSERT(SRC_IP_1_WIDTH == SRC_IP_0_WIDTH);
- EFHW_BUILD_ASSERT(SRC_TCP_DEST_UDP_1_WIDTH == SRC_TCP_DEST_UDP_0_WIDTH);
- EFHW_BUILD_ASSERT(SCATTER_EN_1_B0_WIDTH == SCATTER_EN_0_B0_WIDTH);
- EFHW_BUILD_ASSERT(RSS_EN_1_B0_WIDTH == RSS_EN_0_B0_WIDTH);
-
- /* TODO: Use filter table 1 as well */
- ulong offset = RX_FILTER_TBL0_OFST + filter_i * 2 * FALCON_REGISTER128;
-
- EFHW_TRACE("%s[%x]: offset=%lx", __FUNCTION__, filter_i, offset);
-
- EFHW_TRACE("%s[%x]: filter %d tcp %d full %d src=%x:%x dest=%x:%x%s%s",
- __FUNCTION__, filter_i, tcp, full, dmaq_id,
- saddr_le32, sport_le16, daddr_le32, dport_le16,
- rss_b0 ? " RSS" : "", scat_b0 ? " SCAT" : "");
-
- EFHW_ASSERT(filter_i < nic->filter_tbl_size);
-
- /* dword 4 */
- __DW4CHCK(TCP_UDP_1_LBN, TCP_UDP_1_WIDTH);
- __DW4CHCK(RXQ_ID_1_LBN, RXQ_ID_1_WIDTH);
-
- __RANGECHCK(tcp, TCP_UDP_1_WIDTH);
- __RANGECHCK(dmaq_id, RXQ_ID_1_WIDTH);
-
- /* dword 3 */
- __DW3CHCK(DEST_IP_1_LBN, DEST_IP_1_WIDTH);
- __RANGECHCK(daddr_le32, DEST_IP_1_WIDTH);
-
- /* dword 2 */
- __DW2CHCK(DEST_PORT_TCP_1_LBN, DEST_PORT_TCP_1_WIDTH);
- __LWCHK(SRC_IP_1_LBN, SRC_IP_1_WIDTH);
- __RANGECHCK(saddr_le32, SRC_IP_1_WIDTH);
-
- /* dword 1 */
- __DWCHCK(SRC_TCP_DEST_UDP_1_LBN, SRC_TCP_DEST_UDP_1_WIDTH);
- __RANGECHCK(sport_le16, SRC_TCP_DEST_UDP_1_WIDTH);
- __RANGECHCK(dport_le16, SRC_TCP_DEST_UDP_1_WIDTH);
-
- /* Falcon requires 128 bit atomic access for this register */
- _falcon_nic_ipfilter_build(nic, tcp, full, rss_b0, scat_b0,
- filter_i, dmaq_id, saddr_le32, sport_le16,
- daddr_le32, dport_le16, &q0, &q1);
-
- EFHW_TRACE("%s[%x]@%p+%lx: %" PRIx64 " %" PRIx64, __FUNCTION__,
- filter_i, EFHW_KVA(nic), offset, q0, q1);
-
- falcon_write_qq(EFHW_KVA(nic) + offset, q0, q1);
- mmiowb();
-
-#if FALCON_VERIFY_FILTERS
- {
- uint64_t q0read, q1read;
-
- /* Read a different entry first - entry BIU flushed shadow */
- falcon_read_qq(EFHW_KVA(nic) + offset+0x10, &q0read, &q1read);
- falcon_read_qq(EFHW_KVA(nic) + offset, &q0read, &q1read);
- EFHW_ASSERT(q0read == q0);
- EFHW_ASSERT(q1read == q1);
-
- _falcon_nic_ipfilter_sanity(nic);
- }
-#endif
-}
-
-static void _falcon_nic_ipfilter_clear(struct efhw_nic *nic, uint filter_i)
-{
- /* TODO: Use filter table 1 as well */
- ulong offset = RX_FILTER_TBL0_OFST + filter_i * 2 * FALCON_REGISTER128;
-
- EFHW_ASSERT(filter_i < nic->filter_tbl_size);
-
- EFHW_TRACE("%s[%x]", __FUNCTION__, filter_i);
-
- /* Falcon requires 128 bit atomic access for this register */
- falcon_write_qq(EFHW_KVA(nic) + offset, 0, 0);
- mmiowb();
-#if FALCON_VERIFY_FILTERS
- {
- uint64_t q0read, q1read;
-
- /* Read a different entry first - entry BIU flushed shadow */
- falcon_read_qq(EFHW_KVA(nic) + offset+0x10, &q0read, &q1read);
- falcon_read_qq(EFHW_KVA(nic) + offset, &q0read, &q1read);
- EFHW_ASSERT(q0read == 0);
- EFHW_ASSERT(q1read == 0);
-
- _falcon_nic_ipfilter_sanity(nic);
- }
-#endif
-}
/*----------------------------------------------------------------------------
*
static inline ulong falcon_dma_tx_q_offset(struct efhw_nic *nic, unsigned dmaq)
{
- EFHW_ASSERT(dmaq < FALCON_DMAQ_NUM);
- return TX_DESC_PTR_TBL_OFST + dmaq * FALCON_REGISTER128;
+ EFHW_ASSERT(dmaq < nic->num_dmaqs);
+ return FR_AZ_TX_DESC_PTR_TBL_OFST + dmaq * FALCON_REGISTER128;
}
static inline uint falcon_dma_tx_q_size_index(uint dmaq_size)
int csum_ip_dis = ((flags & EFHW_VI_TX_IP_CSUM_DIS) != 0);
int csum_tcp_dis = ((flags & EFHW_VI_TX_TCPUDP_CSUM_DIS) != 0);
int non_ip_drop_dis = ((flags & EFHW_VI_TX_TCPUDP_ONLY) == 0);
+ int tx_ip_filter_en = ((flags & EFHW_VI_TX_IP_FILTER_EN) != 0);
+ int tx_eth_filter_en = ((flags & EFHW_VI_TX_ETH_FILTER_EN) != 0);
+ int q_mask_width = ((flags & EFHW_VI_TX_Q_MASK_WIDTH_0) != 0) |
+ (((flags & EFHW_VI_TX_Q_MASK_WIDTH_1) != 0) << 1);
/* initialise the TX descriptor queue pointer table */
EFHW_ASSERT((own_id > 0) || desc_type == 0);
/* dword 1 */
- __DWCHCK(TX_DESCQ_FLUSH_LBN, TX_DESCQ_FLUSH_WIDTH);
- __DWCHCK(TX_DESCQ_TYPE_LBN, TX_DESCQ_TYPE_WIDTH);
- __DWCHCK(TX_DESCQ_SIZE_LBN, TX_DESCQ_SIZE_WIDTH);
- __DWCHCK(TX_DESCQ_LABEL_LBN, TX_DESCQ_LABEL_WIDTH);
- __DWCHCK(TX_DESCQ_OWNER_ID_LBN, TX_DESCQ_OWNER_ID_WIDTH);
-
- __LWCHK(TX_DESCQ_EVQ_ID_LBN, TX_DESCQ_EVQ_ID_WIDTH);
-
- __RANGECHCK(1, TX_DESCQ_FLUSH_WIDTH);
- __RANGECHCK(desc_type, TX_DESCQ_TYPE_WIDTH);
- __RANGECHCK(index, TX_DESCQ_SIZE_WIDTH);
- __RANGECHCK(tag, TX_DESCQ_LABEL_WIDTH);
- __RANGECHCK(own_id, TX_DESCQ_OWNER_ID_WIDTH);
- __RANGECHCK(evq_id, TX_DESCQ_EVQ_ID_WIDTH);
-
- val1 = ((desc_type << TX_DESCQ_TYPE_LBN) |
- (index << TX_DESCQ_SIZE_LBN) |
- (tag << TX_DESCQ_LABEL_LBN) |
- (own_id << TX_DESCQ_OWNER_ID_LBN) |
- (__LOW(evq_id, TX_DESCQ_EVQ_ID_LBN, TX_DESCQ_EVQ_ID_WIDTH)));
+ __DWCHCK(FRF_AZ_TX_DESCQ_FLUSH);
+ __DWCHCK(FRF_AZ_TX_DESCQ_TYPE);
+ __DWCHCK(FRF_AZ_TX_DESCQ_SIZE);
+ __DWCHCK(FRF_AZ_TX_DESCQ_LABEL);
+ __DWCHCK(FRF_AZ_TX_DESCQ_OWNER_ID);
+
+ __LWCHK(FRF_AZ_TX_DESCQ_EVQ_ID);
+
+ __RANGECHCK(1, FRF_AZ_TX_DESCQ_FLUSH_WIDTH);
+ __RANGECHCK(desc_type, FRF_AZ_TX_DESCQ_TYPE_WIDTH);
+ __RANGECHCK(index, FRF_AZ_TX_DESCQ_SIZE_WIDTH);
+ __RANGECHCK(tag, FRF_AZ_TX_DESCQ_LABEL_WIDTH);
+ __RANGECHCK(own_id, FRF_AZ_TX_DESCQ_OWNER_ID_WIDTH);
+ __RANGECHCK(evq_id, FRF_AZ_TX_DESCQ_EVQ_ID_WIDTH);
+
+ val1 = ((desc_type << FRF_AZ_TX_DESCQ_TYPE_LBN) |
+ (index << FRF_AZ_TX_DESCQ_SIZE_LBN) |
+ (tag << FRF_AZ_TX_DESCQ_LABEL_LBN) |
+ (own_id << FRF_AZ_TX_DESCQ_OWNER_ID_LBN) |
+ (__LOW(evq_id, FRF_AZ_TX_DESCQ_EVQ_ID)));
/* dword 2 */
- __DW2CHCK(TX_DESCQ_BUF_BASE_ID_LBN, TX_DESCQ_BUF_BASE_ID_WIDTH);
- __RANGECHCK(buf_idx, TX_DESCQ_BUF_BASE_ID_WIDTH);
+ __DW2CHCK(FRF_AZ_TX_DESCQ_BUF_BASE_ID);
+ __RANGECHCK(buf_idx, FRF_AZ_TX_DESCQ_BUF_BASE_ID_WIDTH);
- val2 = ((__HIGH(evq_id, TX_DESCQ_EVQ_ID_LBN, TX_DESCQ_EVQ_ID_WIDTH)) |
- (buf_idx << __DW2(TX_DESCQ_BUF_BASE_ID_LBN)));
+ val2 = ((__HIGH(evq_id, FRF_AZ_TX_DESCQ_EVQ_ID)) |
+ (buf_idx << __DW2(FRF_AZ_TX_DESCQ_BUF_BASE_ID_LBN)));
/* dword 3 */
- __DW3CHCK(TX_ISCSI_HDIG_EN_LBN, TX_ISCSI_HDIG_EN_WIDTH);
- __DW3CHCK(TX_ISCSI_DDIG_EN_LBN, TX_ISCSI_DDIG_EN_WIDTH);
- __RANGECHCK(iscsi_hdig_en, TX_ISCSI_HDIG_EN_WIDTH);
- __RANGECHCK(iscsi_ddig_en, TX_ISCSI_DDIG_EN_WIDTH);
-
- val3 = ((iscsi_hdig_en << __DW3(TX_ISCSI_HDIG_EN_LBN)) |
- (iscsi_ddig_en << __DW3(TX_ISCSI_DDIG_EN_LBN)) |
- (1 << __DW3(TX_DESCQ_EN_LBN))); /* queue enable bit */
-
+ __DW3CHCK(FRF_AZ_TX_ISCSI_HDIG_EN);
+ __DW3CHCK(FRF_AZ_TX_ISCSI_DDIG_EN);
+ __DW3CHCK(FRF_BZ_TX_IP_CHKSM_DIS);
+ __DW3CHCK(FRF_BZ_TX_NON_IP_DROP_DIS);
+ __DW3CHCK(FRF_BZ_TX_TCP_CHKSM_DIS);
+ __RANGECHCK(iscsi_hdig_en, FRF_AZ_TX_ISCSI_HDIG_EN_WIDTH);
+ __RANGECHCK(iscsi_ddig_en, FRF_AZ_TX_ISCSI_DDIG_EN_WIDTH);
+
+ val3 = ((iscsi_hdig_en << __DW3(FRF_AZ_TX_ISCSI_HDIG_EN_LBN)) |
+ (iscsi_ddig_en << __DW3(FRF_AZ_TX_ISCSI_DDIG_EN_LBN)) |
+ (1 << __DW3(FRF_AZ_TX_DESCQ_EN_LBN))); /* queue enable bit */
+
+ /* Cummulative features - check nothing is invalid */
switch (nic->devtype.variant) {
- case 'B':
- case 'C':
- __DW3CHCK(TX_NON_IP_DROP_DIS_B0_LBN,
- TX_NON_IP_DROP_DIS_B0_WIDTH);
- __DW3CHCK(TX_IP_CHKSM_DIS_B0_LBN, TX_IP_CHKSM_DIS_B0_WIDTH);
- __DW3CHCK(TX_TCP_CHKSM_DIS_B0_LBN, TX_TCP_CHKSM_DIS_B0_WIDTH);
-
- val3 |= ((non_ip_drop_dis << __DW3(TX_NON_IP_DROP_DIS_B0_LBN))|
- (csum_ip_dis << __DW3(TX_IP_CHKSM_DIS_B0_LBN)) |
- (csum_tcp_dis << __DW3(TX_TCP_CHKSM_DIS_B0_LBN)));
- break;
case 'A':
if (csum_ip_dis || csum_tcp_dis || !non_ip_drop_dis)
EFHW_WARN
"csum_tcp_dis=%d non_ip_drop_dis=%d",
__FUNCTION__, csum_ip_dis,
csum_tcp_dis, non_ip_drop_dis);
+ /* fall-through */
+ case 'B':
+ if (tx_ip_filter_en || tx_eth_filter_en || q_mask_width) {
+ EFHW_WARN
+ ("%s: bad settings for B0 tx_ip_filter_en=%d "
+ "tx_eth_filter_en=%d q_mask_width=%d",
+ __FUNCTION__, tx_ip_filter_en,
+ tx_eth_filter_en, q_mask_width);
+ tx_ip_filter_en = 0;
+ tx_eth_filter_en = 0;
+ q_mask_width = 0;
+ }
break;
+ case 'C':
+ break;
default:
+ EFHW_WARN("%s: unknown NIC variant '\\x%02x'",
+ __FUNCTION__, nic->devtype.variant);
EFHW_ASSERT(0);
break;
}
+ val3 |= ((non_ip_drop_dis << __DW3(FRF_BZ_TX_NON_IP_DROP_DIS_LBN)) |
+ (csum_ip_dis << __DW3(FRF_BZ_TX_IP_CHKSM_DIS_LBN)) |
+ (csum_tcp_dis << __DW3(FRF_BZ_TX_TCP_CHKSM_DIS_LBN)) |
+ (tx_ip_filter_en << __DW3(FRF_CZ_TX_DPT_IP_FILT_EN_LBN)) |
+ (tx_eth_filter_en << __DW3(FRF_CZ_TX_DPT_ETH_FILT_EN_LBN)) |
+ (q_mask_width << __DW3(FRF_CZ_TX_DPT_Q_MASK_WIDTH_LBN)));
+
EFHW_TRACE("%s: txq %x evq %u tag %x id %x buf %x "
"%x:%x:%x->%" PRIx64 ":%" PRIx64 ":%" PRIx64,
__FUNCTION__,
static inline ulong
falcon_dma_rx_q_offset(struct efhw_nic *nic, unsigned dmaq)
{
- EFHW_ASSERT(dmaq < FALCON_DMAQ_NUM);
- return RX_DESC_PTR_TBL_OFST + dmaq * FALCON_REGISTER128;
+ EFHW_ASSERT(dmaq < nic->num_dmaqs);
+ return FR_AZ_RX_DESC_PTR_TBL_OFST + dmaq * FALCON_REGISTER128;
}
static void
volatile char __iomem *efhw_kva = EFHW_KVA(nic);
/* Q attributes */
-#if BUG5762_WORKAROUND
- int jumbo = 1; /* Queues must not have mixed types */
-#else
int jumbo = ((flags & EFHW_VI_JUMBO_EN) != 0);
-#endif
int iscsi_hdig_en = ((flags & EFHW_VI_ISCSI_RX_HDIG_EN) != 0);
int iscsi_ddig_en = ((flags & EFHW_VI_ISCSI_RX_DDIG_EN) != 0);
+ int hdr_split_en = ((flags & EFHW_VI_RX_HDR_SPLIT) != 0);
/* initialise the TX descriptor queue pointer table */
offset = falcon_dma_rx_q_offset(nic, dmaq);
EFHW_ASSERT((own_id > 0) || desc_type == 0);
/* dword 1 */
- __DWCHCK(RX_DESCQ_EN_LBN, RX_DESCQ_EN_WIDTH);
- __DWCHCK(RX_DESCQ_JUMBO_LBN, RX_DESCQ_JUMBO_WIDTH);
- __DWCHCK(RX_DESCQ_TYPE_LBN, RX_DESCQ_TYPE_WIDTH);
- __DWCHCK(RX_DESCQ_SIZE_LBN, RX_DESCQ_SIZE_WIDTH);
- __DWCHCK(RX_DESCQ_LABEL_LBN, RX_DESCQ_LABEL_WIDTH);
- __DWCHCK(RX_DESCQ_OWNER_ID_LBN, RX_DESCQ_OWNER_ID_WIDTH);
-
- __LWCHK(RX_DESCQ_EVQ_ID_LBN, RX_DESCQ_EVQ_ID_WIDTH);
-
- __RANGECHCK(1, RX_DESCQ_EN_WIDTH);
- __RANGECHCK(jumbo, RX_DESCQ_JUMBO_WIDTH);
- __RANGECHCK(desc_type, RX_DESCQ_TYPE_WIDTH);
- __RANGECHCK(i, RX_DESCQ_SIZE_WIDTH);
- __RANGECHCK(tag, RX_DESCQ_LABEL_WIDTH);
- __RANGECHCK(own_id, RX_DESCQ_OWNER_ID_WIDTH);
- __RANGECHCK(evq_id, RX_DESCQ_EVQ_ID_WIDTH);
-
- val1 = ((1 << RX_DESCQ_EN_LBN) |
- (jumbo << RX_DESCQ_JUMBO_LBN) |
- (desc_type << RX_DESCQ_TYPE_LBN) |
- (i << RX_DESCQ_SIZE_LBN) |
- (tag << RX_DESCQ_LABEL_LBN) |
- (own_id << RX_DESCQ_OWNER_ID_LBN) |
- (__LOW(evq_id, RX_DESCQ_EVQ_ID_LBN, RX_DESCQ_EVQ_ID_WIDTH)));
+ __DWCHCK(FRF_AZ_RX_DESCQ_EN);
+ __DWCHCK(FRF_AZ_RX_DESCQ_JUMBO);
+ __DWCHCK(FRF_AZ_RX_DESCQ_TYPE);
+ __DWCHCK(FRF_AZ_RX_DESCQ_SIZE);
+ __DWCHCK(FRF_AZ_RX_DESCQ_LABEL);
+ __DWCHCK(FRF_AZ_RX_DESCQ_OWNER_ID);
+
+ __LWCHK(FRF_AZ_RX_DESCQ_EVQ_ID);
+
+ __RANGECHCK(1, FRF_AZ_RX_DESCQ_EN_WIDTH);
+ __RANGECHCK(jumbo, FRF_AZ_RX_DESCQ_JUMBO_WIDTH);
+ __RANGECHCK(desc_type, FRF_AZ_RX_DESCQ_TYPE_WIDTH);
+ __RANGECHCK(i, FRF_AZ_RX_DESCQ_SIZE_WIDTH);
+ __RANGECHCK(tag, FRF_AZ_RX_DESCQ_LABEL_WIDTH);
+ __RANGECHCK(own_id, FRF_AZ_RX_DESCQ_OWNER_ID_WIDTH);
+ __RANGECHCK(evq_id, FRF_AZ_RX_DESCQ_EVQ_ID_WIDTH);
+
+ val1 = ((1 << FRF_AZ_RX_DESCQ_EN_LBN) |
+ (jumbo << FRF_AZ_RX_DESCQ_JUMBO_LBN) |
+ (desc_type << FRF_AZ_RX_DESCQ_TYPE_LBN) |
+ (i << FRF_AZ_RX_DESCQ_SIZE_LBN) |
+ (tag << FRF_AZ_RX_DESCQ_LABEL_LBN) |
+ (own_id << FRF_AZ_RX_DESCQ_OWNER_ID_LBN) |
+ (__LOW(evq_id, FRF_AZ_RX_DESCQ_EVQ_ID)));
/* dword 2 */
- __DW2CHCK(RX_DESCQ_BUF_BASE_ID_LBN, RX_DESCQ_BUF_BASE_ID_WIDTH);
- __RANGECHCK(buf_idx, RX_DESCQ_BUF_BASE_ID_WIDTH);
+ __DW2CHCK(FRF_AZ_RX_DESCQ_BUF_BASE_ID);
+ __RANGECHCK(buf_idx, FRF_AZ_RX_DESCQ_BUF_BASE_ID_WIDTH);
- val2 = ((__HIGH(evq_id, RX_DESCQ_EVQ_ID_LBN, RX_DESCQ_EVQ_ID_WIDTH)) |
- (buf_idx << __DW2(RX_DESCQ_BUF_BASE_ID_LBN)));
+ val2 = ((__HIGH(evq_id, FRF_AZ_RX_DESCQ_EVQ_ID)) |
+ (buf_idx << __DW2(FRF_AZ_RX_DESCQ_BUF_BASE_ID_LBN)));
/* dword 3 */
- __DW3CHCK(RX_ISCSI_HDIG_EN_LBN, RX_ISCSI_HDIG_EN_WIDTH);
- __DW3CHCK(RX_ISCSI_DDIG_EN_LBN, RX_ISCSI_DDIG_EN_WIDTH);
- __RANGECHCK(iscsi_hdig_en, RX_ISCSI_HDIG_EN_WIDTH);
- __RANGECHCK(iscsi_ddig_en, RX_ISCSI_DDIG_EN_WIDTH);
+ __DW3CHCK(FRF_AZ_RX_ISCSI_HDIG_EN);
+ __DW3CHCK(FRF_AZ_RX_ISCSI_DDIG_EN);
+ __DW3CHCK(FRF_CZ_RX_HDR_SPLIT);
- val3 = (iscsi_hdig_en << __DW3(RX_ISCSI_HDIG_EN_LBN)) |
- (iscsi_ddig_en << __DW3(RX_ISCSI_DDIG_EN_LBN));
+ val3 = (iscsi_hdig_en << __DW3(FRF_AZ_RX_ISCSI_HDIG_EN_LBN)) |
+ (iscsi_ddig_en << __DW3(FRF_AZ_RX_ISCSI_DDIG_EN_LBN)) |
+ (hdr_split_en << __DW3(FRF_CZ_RX_HDR_SPLIT_LBN));
EFHW_TRACE("%s: rxq %x evq %u tag %x id %x buf %x %s "
- "%x:%x:%x -> %" PRIx64 ":%" PRIx64 ":%" PRIx64,
+ "%x:%x:%x:%x -> %" PRIx64 ":%" PRIx64 ":%" PRIx64,
__FUNCTION__,
dmaq, evq_id, tag, own_id, buf_idx,
jumbo ? "jumbo" : "normal", dmaq_size,
- iscsi_hdig_en, iscsi_ddig_en, val1, val2, val3);
+ iscsi_hdig_en, iscsi_ddig_en, hdr_split_en,
+ val1, val2, val3);
/* Falcon requires 128 bit atomic access for this register */
FALCON_LOCK_LOCK(nic);
offset = falcon_dma_tx_q_offset(nic, dmaq);
/* dword 1 */
- __DWCHCK(TX_DESCQ_TYPE_LBN, TX_DESCQ_TYPE_WIDTH);
+ __DWCHCK(FRF_AZ_TX_DESCQ_TYPE);
- val1 = ((uint64_t) 1 << TX_DESCQ_TYPE_LBN);
+ val1 = ((uint64_t) 1 << FRF_AZ_TX_DESCQ_TYPE_LBN);
/* dword 2 */
val2 = 0;
/* dword 3 */
- val3 = (0 << __DW3(TX_DESCQ_EN_LBN)); /* queue enable bit */
+ val3 = (0 << __DW3(FRF_AZ_TX_DESCQ_EN_LBN)); /* queue enable bit */
EFHW_TRACE("%s: %x->%" PRIx64 ":%" PRIx64 ":%" PRIx64,
__FUNCTION__, dmaq, val1, val2, val3);
offset = falcon_dma_rx_q_offset(nic, dmaq);
/* dword 1 */
- __DWCHCK(RX_DESCQ_EN_LBN, RX_DESCQ_EN_WIDTH);
- __DWCHCK(RX_DESCQ_TYPE_LBN, RX_DESCQ_TYPE_WIDTH);
+ __DWCHCK(FRF_AZ_RX_DESCQ_EN);
+ __DWCHCK(FRF_AZ_RX_DESCQ_TYPE);
- val1 = ((0 << RX_DESCQ_EN_LBN) | (1 << RX_DESCQ_TYPE_LBN));
+ val1 = ((0 << FRF_AZ_RX_DESCQ_EN_LBN) | (1 << FRF_AZ_RX_DESCQ_TYPE_LBN));
/* dword 2 */
val2 = 0;
uint32_t dma_addr32 = FALCON_BUFFER_4K_PAGE(dma_addr_to_u32(dma_addr));
/* don't do this to me */
- EFHW_BUILD_ASSERT(BUF_ADR_HBUF_ODD_LBN == BUF_ADR_HBUF_EVEN_LBN + 32);
- EFHW_BUILD_ASSERT(BUF_OWNER_ID_HBUF_ODD_LBN ==
- BUF_OWNER_ID_HBUF_EVEN_LBN + 32);
+ EFHW_BUILD_ASSERT(FRF_AZ_BUF_ADR_HBUF_ODD_LBN ==
+ FRF_AZ_BUF_ADR_HBUF_EVEN_LBN + 32);
+ EFHW_BUILD_ASSERT(FRF_AZ_BUF_OWNER_ID_HBUF_ODD_LBN ==
+ FRF_AZ_BUF_OWNER_ID_HBUF_EVEN_LBN + 32);
- EFHW_BUILD_ASSERT(BUF_OWNER_ID_HBUF_ODD_WIDTH ==
- BUF_OWNER_ID_HBUF_EVEN_WIDTH);
- EFHW_BUILD_ASSERT(BUF_ADR_HBUF_ODD_WIDTH == BUF_ADR_HBUF_EVEN_WIDTH);
+ EFHW_BUILD_ASSERT(FRF_AZ_BUF_OWNER_ID_HBUF_ODD_WIDTH ==
+ FRF_AZ_BUF_OWNER_ID_HBUF_EVEN_WIDTH);
+ EFHW_BUILD_ASSERT(FRF_AZ_BUF_ADR_HBUF_ODD_WIDTH ==
+ FRF_AZ_BUF_ADR_HBUF_EVEN_WIDTH);
- __DWCHCK(BUF_ADR_HBUF_EVEN_LBN, BUF_ADR_HBUF_EVEN_WIDTH);
- __DWCHCK(BUF_OWNER_ID_HBUF_EVEN_LBN, BUF_OWNER_ID_HBUF_EVEN_WIDTH);
+ __DWCHCK(FRF_AZ_BUF_ADR_HBUF_EVEN);
+ __DWCHCK(FRF_AZ_BUF_OWNER_ID_HBUF_EVEN);
- __RANGECHCK(dma_addr32, BUF_ADR_HBUF_EVEN_WIDTH);
- __RANGECHCK(own_id, BUF_OWNER_ID_HBUF_EVEN_WIDTH);
+ __RANGECHCK(dma_addr32, FRF_AZ_BUF_ADR_HBUF_EVEN_WIDTH);
+ __RANGECHCK(own_id, FRF_AZ_BUF_OWNER_ID_HBUF_EVEN_WIDTH);
- return ((dma_addr32 << BUF_ADR_HBUF_EVEN_LBN) |
- (own_id << BUF_OWNER_ID_HBUF_EVEN_LBN));
+ return (dma_addr32 << FRF_AZ_BUF_ADR_HBUF_EVEN_LBN) |
+ (own_id << FRF_AZ_BUF_OWNER_ID_HBUF_EVEN_LBN);
}
static inline uint64_t
int bufsz, /* bytes */
int region, int own_id)
{
- __DW2CHCK(IP_DAT_BUF_SIZE_LBN, IP_DAT_BUF_SIZE_WIDTH);
- __DW2CHCK(BUF_ADR_REGION_LBN, BUF_ADR_REGION_WIDTH);
- __LWCHK(BUF_ADR_FBUF_LBN, BUF_ADR_FBUF_WIDTH);
- __DWCHCK(BUF_OWNER_ID_FBUF_LBN, BUF_OWNER_ID_FBUF_WIDTH);
+ __DW2CHCK(FRF_AZ_IP_DAT_BUF_SIZE);
+ __DW2CHCK(FRF_AZ_BUF_ADR_REGION);
+ __LWCHK(FRF_AZ_BUF_ADR_FBUF);
+ __DWCHCK(FRF_AZ_BUF_OWNER_ID_FBUF);
EFHW_ASSERT((bufsz == EFHW_4K) || (bufsz == EFHW_8K));
- dma_addr = (dma_addr >> 12) & __FALCON_MASK64(BUF_ADR_FBUF_WIDTH);
+ dma_addr = (dma_addr >> 12) & __FALCON_MASK64(FRF_AZ_BUF_ADR_FBUF_WIDTH);
- __RANGECHCK(dma_addr, BUF_ADR_FBUF_WIDTH);
- __RANGECHCK(1, IP_DAT_BUF_SIZE_WIDTH);
- __RANGECHCK(region, BUF_ADR_REGION_WIDTH);
- __RANGECHCK(own_id, BUF_OWNER_ID_FBUF_WIDTH);
+ __RANGECHCK(dma_addr, FRF_AZ_BUF_ADR_FBUF_WIDTH);
+ __RANGECHCK(1, FRF_AZ_IP_DAT_BUF_SIZE_WIDTH);
+ __RANGECHCK(region, FRF_AZ_BUF_ADR_REGION_WIDTH);
+ __RANGECHCK(own_id, FRF_AZ_BUF_OWNER_ID_FBUF_WIDTH);
- return (((uint64_t) (bufsz == EFHW_8K) << IP_DAT_BUF_SIZE_LBN) |
- ((uint64_t) region << BUF_ADR_REGION_LBN) |
- ((uint64_t) dma_addr << BUF_ADR_FBUF_LBN) |
- ((uint64_t) own_id << BUF_OWNER_ID_FBUF_LBN));
+ return ((uint64_t) (bufsz == EFHW_8K) << FRF_AZ_IP_DAT_BUF_SIZE_LBN) |
+ ((uint64_t) region << FRF_AZ_BUF_ADR_REGION_LBN) |
+ ((uint64_t) dma_addr << FRF_AZ_BUF_ADR_FBUF_LBN) |
+ ((uint64_t) own_id << FRF_AZ_BUF_OWNER_ID_FBUF_LBN);
}
static inline void
volatile char __iomem *efhw_kva = EFHW_KVA(nic);
volatile char __iomem *offset;
- EFHW_BUILD_ASSERT(BUF_ADR_HBUF_ODD_LBN == BUF_ADR_HBUF_EVEN_LBN + 32);
- EFHW_BUILD_ASSERT(BUF_OWNER_ID_HBUF_ODD_LBN ==
- BUF_OWNER_ID_HBUF_EVEN_LBN + 32);
+ EFHW_BUILD_ASSERT(FRF_AZ_BUF_ADR_HBUF_ODD_LBN ==
+ FRF_AZ_BUF_ADR_HBUF_EVEN_LBN + 32);
+ EFHW_BUILD_ASSERT(FRF_AZ_BUF_OWNER_ID_HBUF_ODD_LBN ==
+ FRF_AZ_BUF_OWNER_ID_HBUF_EVEN_LBN + 32);
shift = (buffer_id & 1) ? 32 : 0;
- offset = (efhw_kva + BUF_HALF_TBL_OFST +
+ offset = (efhw_kva + FR_AZ_BUF_HALF_TBL_OFST +
((buffer_id & ~1) * FALCON_BUFFER_TBL_HALF_BYTES));
entry = falcon_nic_buffer_table_entry32_mk(dma_addr_to_u32(dma_addr),
/* Falcon requires that access to this register is serialised */
falcon_write_q(offset, val);
- /* NB. No mmiowb(). Caller should do that e.g by calling commit */
#if FALCON_USE_SHADOW_BUFFER_TABLE
_falcon_buffer_table[buffer_id & ~1] = val;
/* Confirm the entry if the event queues haven't been set up. */
if (!nic->irq_handler) {
uint64_t new_val;
- int count = 0;
+ int count = MAX_BUF_TBL_READS;
+#ifdef BUG_14512_WA
+ int count2 = MAX_BUF_TBL_READS;
+ count = MAX_MAX_BUF_TBL_READS;
+#endif
while (1) {
mmiowb();
falcon_read_q(offset, &new_val);
if (new_val == val)
break;
- count++;
- if (count > 1000) {
- EFHW_WARN("%s: poll Timeout", __FUNCTION__);
+ count--;
+#ifdef BUG_14512_WA
+ if (count2-- <= 0 ) {
+ EFHW_ERR("%s: WARNING MAX_BUF_TBL_READS exceeded "
+ "at ID %d (offset 0x%x)",
+ __FUNCTION__, buffer_id,
+ (unsigned)(offset - efhw_kva));
+ count2 = MAX_BUF_TBL_READS;
+ }
+#endif
+ if (count <= 0) {
+ EFHW_ERR("%s: poll Timeout waiting at ID %d "
+ "(offset 0x%x) for value %"PRIx64
+ " (last was %"PRIx64")",
+ __FUNCTION__, buffer_id,
+ (unsigned)(offset - efhw_kva),
+ val, new_val);
+ EFHW_ASSERT(0);
break;
}
udelay(1);
EFHW_ASSERT((bufsz == EFHW_4K) ||
(bufsz == EFHW_8K && FALCON_BUFFER_TABLE_FULL_MODE));
- offset = (efhw_kva + BUF_FULL_TBL_OFST +
+ offset = (efhw_kva + FR_AZ_BUF_FULL_TBL_OFST +
(buffer_id * FALCON_BUFFER_TBL_FULL_BYTES));
entry = falcon_nic_buffer_table_entry64_mk(dma_addr, bufsz, region,
/* Falcon requires that access to this register is serialised */
falcon_write_q(offset, entry);
- /* NB. No mmiowb(). Caller should do that e.g by calling commit */
-
/* Confirm the entry if the event queues haven't been set up. */
if (!nic->irq_handler) {
uint64_t new_entry;
- int count = 0;
+ int count = MAX_BUF_TBL_READS;
+#ifdef BUG_14512_WA
+ int count2 = MAX_BUF_TBL_READS;
+ count = MAX_MAX_BUF_TBL_READS;
+#endif
while (1) {
mmiowb();
falcon_read_q(offset, &new_entry);
if (new_entry == entry)
return;
- count++;
- if (count > 1000) {
- EFHW_WARN("%s: poll Timeout waiting for "
- "value %"PRIx64
- " (last was %"PRIx64")",
- __FUNCTION__, entry, new_entry);
- break;
+ count--;
+#ifdef BUG_14512_WA
+ if (count2-- <= 0 ) {
+ EFHW_ERR("%s: WARNING MAX_BUF_TBL_READS exceeded "
+ "at ID %d (offset 0x%x)",
+ __FUNCTION__, buffer_id,
+ (unsigned)(offset - efhw_kva));
+ count2 = MAX_BUF_TBL_READS;
+ }
+#endif
+ if (count <= 0) {
+ EFHW_ERR("%s: poll Timeout waiting at ID %d "
+ "(offset 0x%x) for value %"PRIx64
+ " (last was %"PRIx64")",
+ __FUNCTION__, buffer_id,
+ (unsigned)(offset - efhw_kva),
+ entry, new_entry);
+ EFHW_ASSERT(0);
}
udelay(1);
}
volatile char __iomem *efhw_kva = EFHW_KVA(nic);
uint64_t cmd;
- EFHW_BUILD_ASSERT(BUF_TBL_UPD_REG_KER_OFST == BUF_TBL_UPD_REG_OFST);
- __DW2CHCK(BUF_UPD_CMD_LBN, BUF_UPD_CMD_WIDTH);
- __RANGECHCK(1, BUF_UPD_CMD_WIDTH);
+ __DW2CHCK(FRF_AZ_BUF_UPD_CMD);
+ __RANGECHCK(1, FRF_AZ_BUF_UPD_CMD_WIDTH);
- cmd = ((uint64_t) 1 << BUF_UPD_CMD_LBN);
+ cmd = ((uint64_t) 1 << FRF_AZ_BUF_UPD_CMD_LBN);
/* Falcon requires 128 bit atomic access for this register */
- falcon_write_qq(efhw_kva + BUF_TBL_UPD_REG_OFST,
+ falcon_write_qq(efhw_kva + FR_AZ_BUF_TBL_UPD_REG_OFST,
cmd, FALCON_ATOMIC_UPD_REG);
mmiowb();
uint64_t end_id = buffer_id + num - 1;
volatile char __iomem *efhw_kva = EFHW_KVA(nic);
- volatile char __iomem *offset = (efhw_kva + BUF_TBL_UPD_REG_OFST);
+ volatile char __iomem *offset = (efhw_kva + FR_AZ_BUF_TBL_UPD_REG_OFST);
+
- EFHW_BUILD_ASSERT(BUF_TBL_UPD_REG_KER_OFST == BUF_TBL_UPD_REG_OFST);
#if !FALCON_BUFFER_TABLE_FULL_MODE
/* buffer_ids in half buffer mode reference pairs of buffers */
EFHW_ASSERT(num >= 1);
- __DWCHCK(BUF_CLR_START_ID_LBN, BUF_CLR_START_ID_WIDTH);
- __DW2CHCK(BUF_CLR_END_ID_LBN, BUF_CLR_END_ID_WIDTH);
+ __DWCHCK(FRF_AZ_BUF_CLR_START_ID);
+ __DW2CHCK(FRF_AZ_BUF_CLR_END_ID);
- __DW2CHCK(BUF_CLR_CMD_LBN, BUF_CLR_CMD_WIDTH);
- __RANGECHCK(1, BUF_CLR_CMD_WIDTH);
+ __DW2CHCK(FRF_AZ_BUF_CLR_CMD);
+ __RANGECHCK(1, FRF_AZ_BUF_CLR_CMD_WIDTH);
- __RANGECHCK(start_id, BUF_CLR_START_ID_WIDTH);
- __RANGECHCK(end_id, BUF_CLR_END_ID_WIDTH);
+ __RANGECHCK(start_id, FRF_AZ_BUF_CLR_START_ID_WIDTH);
+ __RANGECHCK(end_id, FRF_AZ_BUF_CLR_END_ID_WIDTH);
- cmd = (((uint64_t) 1 << BUF_CLR_CMD_LBN) |
- (start_id << BUF_CLR_START_ID_LBN) |
- (end_id << BUF_CLR_END_ID_LBN));
+ cmd = (((uint64_t) 1 << FRF_AZ_BUF_CLR_CMD_LBN) |
+ (start_id << FRF_AZ_BUF_CLR_START_ID_LBN) |
+ (end_id << FRF_AZ_BUF_CLR_END_ID_LBN));
/* Falcon requires 128 bit atomic access for this register */
falcon_write_qq(offset, cmd, FALCON_ATOMIC_UPD_REG);
FALCON_LOCK_DECL;
volatile char __iomem *efhw_kva = EFHW_KVA(nic);
- EFHW_BUILD_ASSERT(SRM_UPD_EVQ_REG_OFST == SRM_UPD_EVQ_REG_KER_OFST);
- __DWCHCK(SRM_UPD_EVQ_ID_LBN, SRM_UPD_EVQ_ID_WIDTH);
- __RANGECHCK(evq, SRM_UPD_EVQ_ID_WIDTH);
+ __DWCHCK(FRF_AZ_SRM_UPD_EVQ_ID);
+ __RANGECHCK(evq, FRF_AZ_SRM_UPD_EVQ_ID_WIDTH);
/* Falcon requires 128 bit atomic access for this register */
FALCON_LOCK_LOCK(nic);
- falcon_write_qq(efhw_kva + SRM_UPD_EVQ_REG_OFST,
- ((uint64_t) evq << SRM_UPD_EVQ_ID_LBN),
+ falcon_write_qq(efhw_kva + FR_AZ_SRM_UPD_EVQ_REG_OFST,
+ ((uint64_t) evq << FRF_AZ_SRM_UPD_EVQ_ID_LBN),
FALCON_ATOMIC_SRPM_UDP_EVQ_REG);
mmiowb();
FALCON_LOCK_UNLOCK(nic);
}
-static inline void
+static void
falcon_nic_evq_ptr_tbl(struct efhw_nic *nic,
uint evq, /* evq id */
uint enable, /* 1 to enable, 0 to disable */
uint buf_base_id,/* Buffer table base for EVQ */
- uint evq_size /* Number of events */ )
+ uint evq_size, /* Number of events */
+ uint enable_dos_p/* 1 to enable RPTR dos protection, 0 to disable*/)
{
FALCON_LOCK_DECL;
- uint i, val;
+ uint i;
+ uint64_t val;
ulong offset;
volatile char __iomem *efhw_kva = EFHW_KVA(nic);
}
EFHW_ASSERT(i < N_EVENTQ_SIZES);
- __DWCHCK(EVQ_BUF_BASE_ID_LBN, EVQ_BUF_BASE_ID_WIDTH);
- __DWCHCK(EVQ_SIZE_LBN, EVQ_SIZE_WIDTH);
- __DWCHCK(EVQ_EN_LBN, EVQ_EN_WIDTH);
+ __DWCHCK(FRF_AZ_EVQ_BUF_BASE_ID);
+ __DWCHCK(FRF_AZ_EVQ_SIZE);
+ __DWCHCK(FRF_AZ_EVQ_EN);
+
+ __RANGECHCK(i, FRF_AZ_EVQ_SIZE_WIDTH);
+ __RANGECHCK(buf_base_id, FRF_AZ_EVQ_BUF_BASE_ID_WIDTH);
+ __RANGECHCK(1, FRF_AZ_EVQ_EN_WIDTH);
- __RANGECHCK(i, EVQ_SIZE_WIDTH);
- __RANGECHCK(buf_base_id, EVQ_BUF_BASE_ID_WIDTH);
- __RANGECHCK(1, EVQ_EN_WIDTH);
+ if (nic->devtype.variant >= 'C') {
+ __DW2CHCK(FRF_CZ_EVQ_DOS_PROTECT_EN);
+ __RANGECHCK(1, FRF_CZ_EVQ_DOS_PROTECT_EN_WIDTH);
+ }
/* if !enable then only evq needs to be correct, although valid
* values need to be passed in for other arguments to prevent
* assertions */
-
- val = ((i << EVQ_SIZE_LBN) | (buf_base_id << EVQ_BUF_BASE_ID_LBN) |
- (enable ? (1 << EVQ_EN_LBN) : 0));
-
- EFHW_ASSERT(evq < FALCON_EVQ_TBL_NUM);
-
- offset = EVQ_PTR_TBL_CHAR_OFST;
+
+ if (nic->devtype.variant >= 'C')
+ val = ((i << FRF_AZ_EVQ_SIZE_LBN) |
+ (buf_base_id << FRF_AZ_EVQ_BUF_BASE_ID_LBN) |
+ (enable_dos_p ? ((uint64_t)1 << FRF_CZ_EVQ_DOS_PROTECT_EN_LBN) : 0) |
+ (enable ? (1 << FRF_AZ_EVQ_EN_LBN) : 0));
+ else
+ val = ((i << FRF_AZ_EVQ_SIZE_LBN) |
+ (buf_base_id << FRF_AZ_EVQ_BUF_BASE_ID_LBN) |
+ (enable ? (1 << FRF_AZ_EVQ_EN_LBN) : 0) );
+
+ EFHW_ASSERT(evq < nic->num_evqs);
+
+ offset = FR_AZ_EVQ_PTR_TBL_OFST;
offset += evq * FALCON_REGISTER128;
EFHW_TRACE("%s: evq %u en=%x:buf=%x:size=%x->%x at %lx",
- __FUNCTION__, evq, enable, buf_base_id, evq_size, val,
- offset);
+ __FUNCTION__, evq, enable, buf_base_id, evq_size,
+ (int) val, offset);
/* Falcon requires 128 bit atomic access for this register */
FALCON_LOCK_LOCK(nic);
void
falcon_nic_evq_ack(struct efhw_nic *nic,
uint evq, /* evq id */
- uint rptr, /* new read pointer update */
- bool wakeup /* request a wakeup event if ptr's != */
- )
+ uint rptr /* new read pointer update */)
{
- uint val;
- ulong offset;
volatile char __iomem *efhw_kva = EFHW_KVA(nic);
+ unsigned offset;
- EFHW_BUILD_ASSERT(FALCON_EVQ_CHAR == 4);
-
- __DWCHCK(EVQ_RPTR_LBN, EVQ_RPTR_WIDTH);
- __RANGECHCK(rptr, EVQ_RPTR_WIDTH);
-
- val = (rptr << EVQ_RPTR_LBN);
-
- EFHW_ASSERT(evq < FALCON_EVQ_TBL_NUM);
-
- if (evq < FALCON_EVQ_CHAR) {
- offset = EVQ_RPTR_REG_KER_OFST;
- offset += evq * FALCON_REGISTER128;
-
- EFHW_ASSERT(!wakeup); /* don't try this at home */
- } else {
- offset = EVQ_RPTR_REG_OFST + (FALCON_EVQ_CHAR *
- FALCON_REGISTER128);
- offset += (evq - FALCON_EVQ_CHAR) * FALCON_REGISTER128;
-
- /* nothing to do for interruptless event queues which do
- * not want a wakeup */
- if (evq != FALCON_EVQ_CHAR && !wakeup)
- return;
- }
+ EFHW_ASSERT(evq < nic->num_evqs);
- EFHW_TRACE("%s: %x %x %x->%x", __FUNCTION__, evq, rptr, wakeup, val);
+ __DWCHCK(FRF_AZ_EVQ_RPTR);
+ __RANGECHCK(rptr, FRF_AZ_EVQ_RPTR_WIDTH);
- writel(val, efhw_kva + offset);
+ offset = FR_AZ_EVQ_RPTR_REG_OFST + evq * FALCON_REGISTER128;
+ writel(rptr << FRF_AZ_EVQ_RPTR_LBN, efhw_kva + offset);
mmiowb();
}
volatile char __iomem *efhw_kva = EFHW_KVA(nic);
/* send an event from one driver to the other */
- EFHW_BUILD_ASSERT(DRV_EV_REG_KER_OFST == DRV_EV_REG_OFST);
- EFHW_BUILD_ASSERT(DRV_EV_DATA_LBN == 0);
- EFHW_BUILD_ASSERT(DRV_EV_DATA_WIDTH == 64);
- EFHW_BUILD_ASSERT(DRV_EV_QID_LBN == 64);
- EFHW_BUILD_ASSERT(DRV_EV_QID_WIDTH == 12);
+ EFHW_BUILD_ASSERT(FRF_AZ_DRV_EV_DATA_LBN == 0);
+ EFHW_BUILD_ASSERT(FRF_AZ_DRV_EV_DATA_WIDTH == 64);
+ EFHW_BUILD_ASSERT(FRF_AZ_DRV_EV_QID_LBN == 64);
+ EFHW_BUILD_ASSERT(FRF_AZ_DRV_EV_QID_WIDTH == 12);
FALCON_LOCK_LOCK(nic);
- falcon_write_qq(efhw_kva + DRV_EV_REG_OFST, data, qid);
+ falcon_write_qq(efhw_kva + FR_AZ_DRV_EV_REG_OFST, data, qid);
mmiowb();
FALCON_LOCK_UNLOCK(nic);
}
_DEBUG_SYM_ void
-falcon_timer_cmd(struct efhw_nic *nic,
- uint evq, /* timer id */
- uint mode, /* mode bits */
- uint countdown /* counting value to set */ )
+falcon_ab_timer_tbl_set(struct efhw_nic *nic,
+ uint evq, /* timer id */
+ uint mode, /* mode bits */
+ uint countdown /* counting value to set */)
{
FALCON_LOCK_DECL;
uint val;
ulong offset;
volatile char __iomem *efhw_kva = EFHW_KVA(nic);
- EFHW_BUILD_ASSERT(TIMER_VAL_LBN == 0);
+ EFHW_BUILD_ASSERT(FRF_AB_TIMER_VAL_LBN == 0);
- __DWCHCK(TIMER_MODE_LBN, TIMER_MODE_WIDTH);
- __DWCHCK(TIMER_VAL_LBN, TIMER_VAL_WIDTH);
+ __DWCHCK(FRF_AB_TIMER_MODE);
+ __DWCHCK(FRF_AB_TIMER_VAL);
- __RANGECHCK(mode, TIMER_MODE_WIDTH);
- __RANGECHCK(countdown, TIMER_VAL_WIDTH);
+ __RANGECHCK(mode, FRF_AB_TIMER_MODE_WIDTH);
+ __RANGECHCK(countdown, FRF_AB_TIMER_VAL_WIDTH);
- val = ((mode << TIMER_MODE_LBN) | (countdown << TIMER_VAL_LBN));
+ val = ((mode << FRF_AB_TIMER_MODE_LBN) | (countdown << FRF_AB_TIMER_VAL_LBN));
- if (evq < FALCON_EVQ_CHAR) {
- offset = TIMER_CMD_REG_KER_OFST;
+ if ((nic->devtype.variant == 'A') && (evq < FALCON_A_EVQ_CHAR)) {
+ /* Assert that this is the CHAR bar */
+ EFHW_ASSERT(nic->ctr_ap_bar == FALCON_S_CTR_AP_BAR);
+ offset = FR_AA_TIMER_COMMAND_REG_KER_OFST;
offset += evq * EFHW_8K; /* PAGE mapped register */
} else {
- offset = TIMER_TBL_OFST;
+ offset = FR_AZ_TIMER_TBL_OFST;
offset += evq * FALCON_REGISTER128;
}
- EFHW_ASSERT(evq < FALCON_EVQ_TBL_NUM);
+ EFHW_ASSERT(evq < nic->num_evqs);
EFHW_TRACE("%s: evq %u mode %x (%s) time %x -> %08x",
__FUNCTION__, evq, mode,
return;
}
+
+_DEBUG_SYM_ void
+siena_timer_tbl_set(struct efhw_nic *nic,
+ int instance,
+ int enable,
+ int is_interrupting,
+ int mode,
+ int countdown)
+{
+ volatile char __iomem *efhw_kva = EFHW_KVA(nic);
+ FALCON_LOCK_DECL;
+ unsigned offset;
+ uint64_t val;
+
+ EFHW_ASSERT(instance < (int)nic->num_evqs);
+ __RANGECHCK(mode, FRF_CZ_TIMER_MODE_WIDTH);
+ __RANGECHCK(countdown, FRF_CZ_TIMER_VAL_WIDTH);
+
+ offset = FR_AZ_TIMER_TBL_OFST;
+ offset += instance * FALCON_REGISTER128;
+
+ val = (uint64_t) enable << FRF_CZ_TIMER_Q_EN_LBN;
+ val |= (uint64_t) 0 << FRF_CZ_INT_ARMD_LBN;
+ val |= (uint64_t) !is_interrupting << FRF_CZ_HOST_NOTIFY_MODE_LBN;
+ val |= (uint64_t) mode << FRF_CZ_TIMER_MODE_LBN;
+ val |= (uint64_t) countdown << FRF_CZ_TIMER_VAL_LBN;
+
+ /* Falcon requires 128 bit atomic access for this register when
+ * accessed from the driver. User access to timers is paged mapped
+ */
+ FALCON_LOCK_LOCK(nic);
+ falcon_write_qq(efhw_kva + offset, val, 0);
+ mmiowb();
+ FALCON_LOCK_UNLOCK(nic);
+ return;
+}
+
/*--------------------------------------------------------------------
*
* Rate pacing - Low level interface
*--------------------------------------------------------------------*/
void falcon_nic_pace(struct efhw_nic *nic, uint dmaq, uint pace)
{
- /* Pace specified in 2^(units of microseconds). This is the minimum
- additional delay imposed over and above the IPG.
+ /* The pace delay imposed is (2^pace)*100ns unless the pace
+ value is zero in which case the delay is zero. If the
+ delay is less than the IPG then it will effectively be
+ ignored because the IPG will be the limiting factor.
Pacing only available on the virtual interfaces
*/
if (pace > 20)
pace = 20; /* maxm supported value */
- __DWCHCK(TX_PACE_LBN, TX_PACE_WIDTH);
- __RANGECHCK(pace, TX_PACE_WIDTH);
+ __DWCHCK(FRF_AZ_TX_PACE);
+ __RANGECHCK(pace, FRF_AZ_TX_PACE_WIDTH);
switch (nic->devtype.variant) {
case 'A':
- EFHW_ASSERT(dmaq >= TX_PACE_TBL_FIRST_QUEUE_A1);
- offset = TX_PACE_TBL_A1_OFST;
- offset += (dmaq - TX_PACE_TBL_FIRST_QUEUE_A1) * 16;
+ EFHW_ASSERT(dmaq >= FR_AA_TX_PACE_TBL_FIRST_QUEUE);
+ offset = FR_AA_TX_PACE_TBL_OFST;
+ offset += (dmaq - FR_AA_TX_PACE_TBL_FIRST_QUEUE) * 16;
break;
case 'B':
case 'C':
/* Would be nice to assert this, but as dmaq is unsigned and
- * TX_PACE_TBL_FIRST_QUEUE_B0 is 0, it makes no sense
- * EFHW_ASSERT(dmaq >= TX_PACE_TBL_FIRST_QUEUE_B0);
+ * FRF_BZ_TX_PACE_TBL_FIRST_QUEUE is 0, it makes no sense
+ * EFHW_ASSERT(dmaq >= FRF_BZ_TX_PACE_TBL_FIRST_QUEUE);
*/
- offset = TX_PACE_TBL_B0_OFST;
- offset += (dmaq - TX_PACE_TBL_FIRST_QUEUE_B0) * 16;
+ offset = FR_BZ_TX_PACE_TBL_OFST;
+ offset += (dmaq - FR_BZ_TX_PACE_TBL_FIRST_QUEUE) * 16;
break;
default:
EFHW_ASSERT(0);
__FUNCTION__, dmaq, offset, pace);
}
+
/*--------------------------------------------------------------------
*
- * Interrupt - Low level interface
+ * RSS control
*
*--------------------------------------------------------------------*/
-static void falcon_nic_handle_fatal_int(struct efhw_nic *nic)
+void falcon_nic_wakeup_mask_set(struct efhw_nic *nic, unsigned mask)
{
+ uint64_t q0, q1;
FALCON_LOCK_DECL;
- volatile char __iomem *offset;
- volatile char __iomem *efhw_kva = EFHW_KVA(nic);
- uint64_t val;
-
- offset = (efhw_kva + FATAL_INTR_REG_OFST);
- /* Falcon requires 32 bit atomic access for this register */
FALCON_LOCK_LOCK(nic);
- val = readl(offset);
+ falcon_read_qq(EFHW_KVA(nic) + FR_AZ_EVQ_CTL_REG_OFST, &q0, &q1);
+ switch (nic->devtype.variant) {
+ case 'B':
+ q0 &= ~Q0_MASK(FRF_BB_RX_EVQ_WAKEUP_MASK);
+ q0 |= Q0_VALUE(FRF_BB_RX_EVQ_WAKEUP_MASK, mask);
+ break;
+ default:
+ if (nic->devtype.variant >= 'C') {
+ q0 &= ~Q0_MASK(FRF_CZ_RX_EVQ_WAKEUP_MASK);
+ q0 |= Q0_VALUE(FRF_CZ_RX_EVQ_WAKEUP_MASK, mask);
+ }
+ break;
+ }
+ falcon_write_qq(EFHW_KVA(nic) + FR_AZ_EVQ_CTL_REG_OFST, q0, q1);
FALCON_LOCK_UNLOCK(nic);
-
- /* ?? BUG3249 - need to disable illegal address interrupt */
- /* ?? BUG3114 - need to backport interrupt storm protection code */
- EFHW_ERR("fatal interrupt: %s%s%s%s%s%s%s%s%s%s%s%s[%" PRIx64 "]",
- val & (1 << PCI_BUSERR_INT_CHAR_LBN) ? "PCI-bus-error " : "",
- val & (1 << SRAM_OOB_INT_CHAR_LBN) ? "SRAM-oob " : "",
- val & (1 << BUFID_OOB_INT_CHAR_LBN) ? "bufid-oob " : "",
- val & (1 << MEM_PERR_INT_CHAR_LBN) ? "int-parity " : "",
- val & (1 << RBUF_OWN_INT_CHAR_LBN) ? "rx-bufid-own " : "",
- val & (1 << TBUF_OWN_INT_CHAR_LBN) ? "tx-bufid-own " : "",
- val & (1 << RDESCQ_OWN_INT_CHAR_LBN) ? "rx-desc-own " : "",
- val & (1 << TDESCQ_OWN_INT_CHAR_LBN) ? "tx-desc-own " : "",
- val & (1 << EVQ_OWN_INT_CHAR_LBN) ? "evq-own " : "",
- val & (1 << EVFF_OFLO_INT_CHAR_LBN) ? "evq-fifo " : "",
- val & (1 << ILL_ADR_INT_CHAR_LBN) ? "ill-addr " : "",
- val & (1 << SRM_PERR_INT_CHAR_LBN) ? "sram-parity " : "", val);
}
+
+/*--------------------------------------------------------------------
+ *
+ * Interrupt - Low level interface
+ *
+ *--------------------------------------------------------------------*/
+
static void falcon_nic_interrupt_hw_enable(struct efhw_nic *nic)
{
FALCON_LOCK_DECL;
volatile char __iomem *offset;
volatile char __iomem *efhw_kva = EFHW_KVA(nic);
- EFHW_BUILD_ASSERT(DRV_INT_EN_CHAR_WIDTH == 1);
+ EFHW_BUILD_ASSERT(FRF_AZ_DRV_INT_EN_CHAR_WIDTH == 1);
if (nic->flags & NIC_FLAG_NO_INTERRUPT)
return;
- offset = (efhw_kva + INT_EN_REG_CHAR_OFST);
- val = 1 << DRV_INT_EN_CHAR_LBN;
+ offset = (efhw_kva + FR_AZ_INT_EN_REG_CHAR_OFST);
+ val = 1 << FRF_AZ_DRV_INT_EN_CHAR_LBN;
EFHW_NOTICE("%s: %x -> %x", __FUNCTION__, (int)(offset - efhw_kva),
val);
volatile char __iomem *offset;
volatile char __iomem *efhw_kva = EFHW_KVA(nic);
- EFHW_BUILD_ASSERT(SRAM_PERR_INT_KER_WIDTH == 1);
- EFHW_BUILD_ASSERT(DRV_INT_EN_KER_LBN == 0);
- EFHW_BUILD_ASSERT(SRAM_PERR_INT_CHAR_WIDTH == 1);
- EFHW_BUILD_ASSERT(DRV_INT_EN_CHAR_LBN == 0);
- EFHW_BUILD_ASSERT(SRAM_PERR_INT_KER_LBN == SRAM_PERR_INT_CHAR_LBN);
- EFHW_BUILD_ASSERT(DRV_INT_EN_KER_LBN == DRV_INT_EN_CHAR_LBN);
+ EFHW_BUILD_ASSERT(FRF_AZ_SRM_PERR_INT_KER_WIDTH == 1);
+ EFHW_BUILD_ASSERT(FRF_AZ_DRV_INT_EN_KER_LBN == 0);
+ EFHW_BUILD_ASSERT(FRF_AZ_SRM_PERR_INT_CHAR_WIDTH == 1);
+ EFHW_BUILD_ASSERT(FRF_AZ_DRV_INT_EN_CHAR_LBN == 0);
+ EFHW_BUILD_ASSERT(FRF_AZ_SRM_PERR_INT_KER_LBN == FRF_AZ_SRM_PERR_INT_CHAR_LBN);
+ EFHW_BUILD_ASSERT(FRF_AZ_DRV_INT_EN_KER_LBN == FRF_AZ_DRV_INT_EN_CHAR_LBN);
if (nic->flags & NIC_FLAG_NO_INTERRUPT)
return;
- offset = (efhw_kva + INT_EN_REG_CHAR_OFST);
+ offset = (efhw_kva + FR_AZ_INT_EN_REG_CHAR_OFST);
EFHW_NOTICE("%s: %x -> 0", __FUNCTION__, (int)(offset - efhw_kva));
}
-static void falcon_nic_irq_addr_set(struct efhw_nic *nic, dma_addr_t dma_addr)
-{
- FALCON_LOCK_DECL;
- volatile char __iomem *offset;
- volatile char __iomem *efhw_kva = EFHW_KVA(nic);
-
- offset = (efhw_kva + INT_ADR_REG_CHAR_OFST);
-
- EFHW_NOTICE("%s: %x -> " DMA_ADDR_T_FMT, __FUNCTION__,
- (int)(offset - efhw_kva), dma_addr);
-
- /* Falcon requires 128 bit atomic access for this register */
- FALCON_LOCK_LOCK(nic);
- falcon_write_qq(offset, dma_addr, FALCON_ATOMIC_INT_ADR_REG);
- mmiowb();
- FALCON_LOCK_UNLOCK(nic);
-}
-
-
-
/*--------------------------------------------------------------------
*
* RXDP - low level interface
uint64_t val, val2, usr_buf_size = usr_buf_bytes / 32;
int rubs_lbn, rubs_width, roec_lbn;
- EFHW_BUILD_ASSERT(RX_CFG_REG_OFST == RX_CFG_REG_KER_OFST);
+ __DWCHCK(FRF_AA_RX_USR_BUF_SIZE);
+ __DWCHCK(FRF_BZ_RX_USR_BUF_SIZE);
+ __QWCHCK(FRF_AA_RX_OWNERR_CTL);
+ __QWCHCK(FRF_BZ_RX_OWNERR_CTL);
switch (nic->devtype.variant) {
default:
EFHW_ASSERT(0);
/* Fall-through to avoid compiler warnings. */
case 'A':
- rubs_lbn = RX_USR_BUF_SIZE_A1_LBN;
- rubs_width = RX_USR_BUF_SIZE_A1_WIDTH;
- roec_lbn = RX_OWNERR_CTL_A1_LBN;
+ rubs_lbn = FRF_AA_RX_USR_BUF_SIZE_LBN;
+ rubs_width = FRF_AA_RX_USR_BUF_SIZE_WIDTH;
+ roec_lbn = FRF_AA_RX_OWNERR_CTL_LBN;
break;
case 'B':
case 'C':
- rubs_lbn = RX_USR_BUF_SIZE_B0_LBN;
- rubs_width = RX_USR_BUF_SIZE_B0_WIDTH;
- roec_lbn = RX_OWNERR_CTL_B0_LBN;
+ rubs_lbn = FRF_BZ_RX_USR_BUF_SIZE_LBN;
+ rubs_width = FRF_BZ_RX_USR_BUF_SIZE_WIDTH;
+ roec_lbn = FRF_AA_RX_OWNERR_CTL_LBN;
break;
}
- __DWCHCK(rubs_lbn, rubs_width);
- __QWCHCK(roec_lbn, 1);
__RANGECHCK(usr_buf_size, rubs_width);
/* Falcon requires 128 bit atomic access for this register */
FALCON_LOCK_LOCK(nic);
- falcon_read_qq(efhw_kva + RX_CFG_REG_OFST, &val, &val2);
+ falcon_read_qq(efhw_kva + FR_AZ_RX_CFG_REG_OFST, &val, &val2);
val &= ~((__FALCON_MASK64(rubs_width)) << rubs_lbn);
val |= (usr_buf_size << rubs_lbn);
/* shouldn't be needed for a production driver */
val |= ((uint64_t) 1 << roec_lbn);
- falcon_write_qq(efhw_kva + RX_CFG_REG_OFST, val, val2);
+ falcon_write_qq(efhw_kva + FR_AZ_RX_CFG_REG_OFST, val, val2);
mmiowb();
FALCON_LOCK_UNLOCK(nic);
}
EXPORT_SYMBOL(falcon_nic_set_rx_usr_buf_size);
-void
-falcon_nic_rx_filter_ctl_get(struct efhw_nic *nic, uint32_t *tcp_full,
- uint32_t *tcp_wild,
- uint32_t *udp_full, uint32_t *udp_wild)
-{
- volatile char __iomem *efhw_kva = EFHW_KVA(nic);
- FALCON_LOCK_DECL;
- uint64_t val;
-
- FALCON_LOCK_LOCK(nic);
- falcon_read_q(efhw_kva + RX_FILTER_CTL_REG_OFST, &val);
- FALCON_LOCK_UNLOCK(nic);
-
- *tcp_full = (uint32_t)((val >> TCP_FULL_SRCH_LIMIT_LBN) &
- (__FALCON_MASK64(TCP_FULL_SRCH_LIMIT_WIDTH)));
-
- *tcp_wild = (uint32_t)((val >> TCP_WILD_SRCH_LIMIT_LBN) &
- (__FALCON_MASK64(TCP_WILD_SRCH_LIMIT_WIDTH)));
-
- *udp_full = (uint32_t)((val >> UDP_FULL_SRCH_LIMIT_LBN) &
- (__FALCON_MASK64(UDP_FULL_SRCH_LIMIT_WIDTH)));
-
- *udp_wild = (uint32_t)((val >> UDP_WILD_SRCH_LIMIT_LBN) &
- (__FALCON_MASK64(UDP_WILD_SRCH_LIMIT_WIDTH)));
-}
-EXPORT_SYMBOL(falcon_nic_rx_filter_ctl_get);
-
-void
-falcon_nic_rx_filter_ctl_set(struct efhw_nic *nic, uint32_t tcp_full,
- uint32_t tcp_wild,
- uint32_t udp_full, uint32_t udp_wild)
-{
- uint64_t val, val2;
- volatile char __iomem *efhw_kva = EFHW_KVA(nic);
- FALCON_LOCK_DECL;
-
- EFHW_ASSERT(tcp_full < nic->filter_tbl_size);
- EFHW_ASSERT(tcp_wild < nic->filter_tbl_size);
- EFHW_ASSERT(udp_full < nic->filter_tbl_size);
- EFHW_ASSERT(udp_wild < nic->filter_tbl_size);
-
- /* until we implement a dynamic scaling of search limits we wish to
- * maintain the same limits set up by default in the net driver
- * when we initialize the char driver */
- tcp_full_srch_limit = tcp_full;
- tcp_wild_srch_limit = tcp_wild;
- udp_full_srch_limit = udp_full;
- udp_wild_srch_limit = udp_wild;
-
- /* Falcon requires 128 bit atomic access for this register */
- FALCON_LOCK_LOCK(nic);
- falcon_read_qq(efhw_kva + RX_FILTER_CTL_REG_OFST, &val, &val2);
-
- /* Search limits */
- val &= ~((__FALCON_MASK64(TCP_FULL_SRCH_LIMIT_WIDTH))
- << TCP_FULL_SRCH_LIMIT_LBN);
-
- val |= ((uint64_t)tcp_full + RX_FILTER_CTL_SRCH_FUDGE_FULL)
- << TCP_FULL_SRCH_LIMIT_LBN;
-
- val &= ~((__FALCON_MASK64(TCP_WILD_SRCH_LIMIT_WIDTH))
- << TCP_WILD_SRCH_LIMIT_LBN);
-
- val |= ((uint64_t)tcp_wild + RX_FILTER_CTL_SRCH_FUDGE_WILD)
- << TCP_WILD_SRCH_LIMIT_LBN;
-
- val &= ~((__FALCON_MASK64(UDP_FULL_SRCH_LIMIT_WIDTH))
- << UDP_FULL_SRCH_LIMIT_LBN);
-
- val |= ((uint64_t)udp_full + RX_FILTER_CTL_SRCH_FUDGE_FULL)
- << UDP_FULL_SRCH_LIMIT_LBN;
-
- val &= ~((__FALCON_MASK64(UDP_WILD_SRCH_LIMIT_WIDTH))
- << UDP_WILD_SRCH_LIMIT_LBN);
-
- val |= ((uint64_t)udp_wild + RX_FILTER_CTL_SRCH_FUDGE_WILD)
- << UDP_WILD_SRCH_LIMIT_LBN;
-
- falcon_write_qq(efhw_kva + RX_FILTER_CTL_REG_OFST, val, val2);
- mmiowb();
- FALCON_LOCK_UNLOCK(nic);
-}
-EXPORT_SYMBOL(falcon_nic_rx_filter_ctl_set);
/*--------------------------------------------------------------------
*
volatile char __iomem *efhw_kva = EFHW_KVA(nic);
uint64_t val1, val2;
- EFHW_BUILD_ASSERT(TX_CFG_REG_OFST == TX_CFG_REG_KER_OFST);
- __DWCHCK(TX_OWNERR_CTL_LBN, TX_OWNERR_CTL_WIDTH);
- __DWCHCK(TX_NON_IP_DROP_DIS_LBN, TX_NON_IP_DROP_DIS_WIDTH);
+ __DWCHCK(FRF_AZ_TX_OWNERR_CTL);
+ __DWCHCK(FRF_AA_TX_NON_IP_DROP_DIS);
FALCON_LOCK_LOCK(nic);
- falcon_read_qq(efhw_kva + TX_CFG_REG_OFST, &val1, &val2);
+ falcon_read_qq(efhw_kva + FR_AZ_TX_CFG_REG_OFST, &val1, &val2);
/* Will flag fatal interrupts on owner id errors. This should not be
on for production code because there is otherwise a denial of
serivce attack possible */
- val1 |= (1 << TX_OWNERR_CTL_LBN);
+ val1 |= (1 << FRF_AZ_TX_OWNERR_CTL_LBN);
/* Setup user queue TCP/UDP only packet security */
if (unlocked)
- val1 |= (1 << TX_NON_IP_DROP_DIS_LBN);
+ val1 |= (1 << FRF_AA_TX_NON_IP_DROP_DIS_LBN);
else
- val1 &= ~(1 << TX_NON_IP_DROP_DIS_LBN);
+ val1 &= ~(1 << FRF_AA_TX_NON_IP_DROP_DIS_LBN);
- falcon_write_qq(efhw_kva + TX_CFG_REG_OFST, val1, val2);
+ falcon_write_qq(efhw_kva + FR_AZ_TX_CFG_REG_OFST, val1, val2);
mmiowb();
FALCON_LOCK_UNLOCK(nic);
}
*
*--------------------------------------------------------------------*/
-static void falcon_nic_pace_cfg(struct efhw_nic *nic)
+void falcon_nic_pace_cfg(struct efhw_nic *nic, int fb_base, int bin_thresh)
{
FALCON_LOCK_DECL;
volatile char __iomem *efhw_kva = EFHW_KVA(nic);
unsigned offset = 0;
uint64_t val;
- val = 0xa81682; /* !!!! */
+ __DWCHCK(FRF_AZ_TX_PACE_FB_BASE);
+ __DWCHCK(FRF_AZ_TX_PACE_BIN_TH);
- /* Falcon requires 128 bit atomic access for this register */
- FALCON_LOCK_LOCK(nic);
switch (nic->devtype.variant) {
- case 'A': offset = TX_PACE_REG_A1_OFST; break;
- case 'B': offset = TX_PACE_REG_B0_OFST; break;
- case 'C': offset = TX_PACE_REG_B0_OFST; break;
+ case 'A': offset = FR_AA_TX_PACE_REG_OFST; break;
+ case 'B': offset = FR_BZ_TX_PACE_REG_OFST; break;
+ case 'C': offset = FR_BZ_TX_PACE_REG_OFST; break;
default: EFHW_ASSERT(0); break;
}
+
+ val = (0x15 << FRF_AZ_TX_PACE_SB_NOT_AF_LBN);
+ val |= (0xb << FRF_AZ_TX_PACE_SB_AF_LBN);
+
+ val |= ((fb_base & __FALCON_MASK64(FRF_AZ_TX_PACE_FB_BASE_WIDTH)) <<
+ FRF_AZ_TX_PACE_FB_BASE_LBN);
+ val |= ((bin_thresh & __FALCON_MASK64(FRF_AZ_TX_PACE_BIN_TH_WIDTH)) <<
+ FRF_AZ_TX_PACE_BIN_TH_LBN);
+
+ /* Falcon requires 128 bit atomic access for this register */
+ FALCON_LOCK_LOCK(nic);
falcon_write_qq(efhw_kva + offset, val, 0);
mmiowb();
FALCON_LOCK_UNLOCK(nic);
}
+
/**********************************************************************
- * Supporting modules. ************************************************
- **********************************************************************/
-
-/*--------------------------------------------------------------------
- *
- * Filter support
- *
- *--------------------------------------------------------------------*/
-
-/*! \TODO this table should be per nic */
-struct falcon_cached_ipfilter {
-#if FALCON_FULL_FILTER_CACHE
- unsigned dmaq;
- unsigned saddr_le32;
- unsigned daddr_le32;
- unsigned sport_le16;
- unsigned dport_le16;
- unsigned tcp:1;
- unsigned full:1;
- unsigned rss_b0:1;
- unsigned scat_b0:1;
-#endif
- unsigned addr_valid:1;
-
-};
-
-
-/* TODO: Dynamically allocate this and store in struct efhw_nic. */
-static struct falcon_cached_ipfilter
- host_ipfilter_cache[EFHW_MAX_NR_DEVS][FALCON_FILTER_TBL_NUM];
-
-
-static inline void host_ipfilter_cache_init(struct efhw_nic *nic)
-{
- memset(host_ipfilter_cache[nic->index], 0,
- sizeof(host_ipfilter_cache[0][0]) * nic->filter_tbl_size);
-}
-
-static inline int host_ipfilter_cache_active(struct efhw_nic *nic, uint idx)
-{
- EFHW_ASSERT(nic->index < EFHW_MAX_NR_DEVS);
- EFHW_ASSERT(idx < nic->filter_tbl_size);
-
- return (host_ipfilter_cache[nic->index][idx].addr_valid);
-
-}
-
-static inline void host_ipfilter_cache_flush(struct efhw_nic *nic, uint idx)
-{
- EFHW_ASSERT(nic->index < EFHW_MAX_NR_DEVS);
- EFHW_ASSERT(idx < nic->filter_tbl_size);
-
- memset(&host_ipfilter_cache[nic->index][idx], 0,
- sizeof(struct falcon_cached_ipfilter));
- mmiowb();
-}
-
-static inline void
-host_ipfilter_cache_set_addr(struct efhw_nic *nic, uint idx, uint dmaq,
- unsigned tcp, unsigned full,
- unsigned rss_b0, unsigned scat_b0,
- unsigned saddr_le32, unsigned sport_le16,
- unsigned daddr_le32, unsigned dport_le16)
-{
- unsigned nic_i = nic->index;
-
- EFHW_ASSERT(nic_i < EFHW_MAX_NR_DEVS);
- EFHW_ASSERT(idx < nic->filter_tbl_size);
- EFHW_ASSERT(!host_ipfilter_cache[nic_i][idx].addr_valid);
-
- __RANGECHCK(sport_le16, SRC_TCP_DEST_UDP_1_WIDTH);
- __RANGECHCK(dport_le16, SRC_TCP_DEST_UDP_1_WIDTH);
-
-#if FALCON_FULL_FILTER_CACHE
- host_ipfilter_cache[nic_i][idx].dmaq = dmaq;
- host_ipfilter_cache[nic_i][idx].saddr_le32 = saddr_le32;
- host_ipfilter_cache[nic_i][idx].daddr_le32 = daddr_le32;
- host_ipfilter_cache[nic_i][idx].sport_le16 = sport_le16;
- host_ipfilter_cache[nic_i][idx].dport_le16 = dport_le16;
- host_ipfilter_cache[nic_i][idx].tcp = tcp;
- host_ipfilter_cache[nic_i][idx].full = full;
- host_ipfilter_cache[nic_i][idx].rss_b0 = rss_b0;
- host_ipfilter_cache[nic_i][idx].scat_b0 = scat_b0;
-#endif
- host_ipfilter_cache[nic_i][idx].addr_valid = 1;
- mmiowb();
-}
-
-#if FALCON_VERIFY_FILTERS
-/* Check that all active filters still exist by reading from H/W */
-static void _falcon_nic_ipfilter_sanity(struct efhw_nic *nic)
-{
- unsigned i;
- struct falcon_cached_ipfilter *f;
- uint64_t q0_expect, q1_expect, q0_got, q1_got;
-
- for (i = 0; i < nic->filter_tbl_size; i++) {
- f = host_ipfilter_cache[nic->index] + i;
- if (!f->addr_valid)
- continue;
-
- _falcon_nic_ipfilter_build(nic, f->tcp, f->full,
- f->rss_b0, f->scat_b0, i, f->dmaq,
- f->saddr_le32, f->sport_le16,
- f->daddr_le32, f->dport_le16,
- &q0_expect, &q1_expect);
-
- falcon_read_qq(EFHW_KVA(nic) + RX_FILTER_TBL0_OFST +
- i * 2 * FALCON_REGISTER128,
- &q0_got, &q1_got);
-
- if ((q0_got != q0_expect) || (q1_got != q1_expect)) {
- falcon_write_qq(EFHW_KVA(nic) + 0x300,
- q0_got, q1_got);
- EFHW_ERR("ERROR: RX-filter[%d][%d] was "
- "%"PRIx64":%" PRIx64" expected "
- "%"PRIx64":%"PRIx64,
- nic->index, i, q0_got, q1_got,
- q0_expect, q1_expect);
- }
- }
-}
-#endif /* FALCON_VERIFY_FILTERS */
-
-#if FALCON_FULL_FILTER_CACHE
-static inline int
-host_ipfilter_cache_check_not(uint nic, uint idx, int tcp, int full,
- unsigned saddr_le32, unsigned sport_le16,
- unsigned daddr_le32, unsigned dport_le16)
-{
- return ((host_ipfilter_cache[nic][idx].saddr_le32 != saddr_le32) ||
- (host_ipfilter_cache[nic][idx].daddr_le32 != daddr_le32) ||
- (host_ipfilter_cache[nic][idx].sport_le16 != sport_le16) ||
- (host_ipfilter_cache[nic][idx].dport_le16 != dport_le16) ||
- (host_ipfilter_cache[nic][idx].tcp != tcp) ||
- (host_ipfilter_cache[nic][idx].full != full));
-}
-#endif
-
-#define host_ipfilter_cache_saddr_le32(nic, idx) \
- host_ipfilter_cache[nic][idx].saddr_le32
-#define host_ipfilter_cache_daddr_le32(nic, idx) \
- host_ipfilter_cache[nic][idx].daddr_le32
-#define host_ipfilter_cache_sport_le16(nic, idx) \
- host_ipfilter_cache[nic][idx].sport_le16
-#define host_ipfilter_cache_dport_le16(nic, idx) \
- host_ipfilter_cache[nic][idx].dport_le16
-#define host_ipfilter_cache_tcp(nic, idx) \
- host_ipfilter_cache[nic][idx].tcp
-#define host_ipfilter_cache_full(nic, idx) \
- host_ipfilter_cache[nic][idx].full
-
-/**********************************************************************
- * Implementation of the HAL. ********************************************
+ * Implementation of the HAL. ********************************************
**********************************************************************/
/*----------------------------------------------------------------------------
*
*---------------------------------------------------------------------------*/
-
-static int falcon_nic_init_irq_channel(struct efhw_nic *nic, int enable)
-{
- /* create a buffer for the irq channel */
- int rc;
-
- if (enable) {
- rc = efhw_iopage_alloc(nic, &nic->irq_iobuff);
- if (rc < 0)
- return rc;
-
- falcon_nic_irq_addr_set(nic,
- efhw_iopage_dma_addr(&nic->irq_iobuff));
- } else {
- if (efhw_iopage_is_valid(&nic->irq_iobuff))
- efhw_iopage_free(nic, &nic->irq_iobuff);
-
- efhw_iopage_mark_invalid(&nic->irq_iobuff);
- falcon_nic_irq_addr_set(nic, 0);
- }
-
- EFHW_TRACE("%s: %lx %sable", __FUNCTION__,
- (unsigned long) efhw_iopage_dma_addr(&nic->irq_iobuff),
- enable ? "en" : "dis");
-
- return 0;
-}
-
-
static void falcon_nic_close_hardware(struct efhw_nic *nic)
{
/* check we are in possession of some hardware */
if (!efhw_nic_have_hw(nic))
return;
-
- falcon_nic_init_irq_channel(nic, 0);
-
- EFHW_NOTICE("%s:", __FUNCTION__);
+ falcon_nic_filter_dtor(nic);
}
+#ifndef __ci_ul_driver__
static
+#endif
int falcon_nic_get_mac_config(struct efhw_nic *nic)
{
- volatile char __iomem *efhw_kva = nic->bar_ioaddr;
- int is_mac_type_1g;
- uint32_t strap, altera;
- uint64_t rx_cfg, r;
-
- altera = readl(efhw_kva + ALTERA_BUILD_REG_OFST);
- strap = readl(efhw_kva + STRAP_REG_KER_OFST) & 0x7;
-
switch (nic->devtype.variant) {
case 'A':
- if ((altera & 0x0fff0000) == 0x1130000) {
- strap = 2; /* FPGA - PCI-X 2G */
- } else if ((altera & 0x00ff0000) == 0x140000) {
- /* should be 114 */
- strap = 4; /* FPGA - PCI-X 4G */
- } else if (strap < 2 || strap > 5) {
- EFHW_ERR("Invalid strap option %d altera_buid_ver=%x",
- strap, altera);
- return -EINVAL;
- }
- is_mac_type_1g = (0 != (strap & 2));
- break;
case 'B':
- /* Runtime check that the hardware and software agree about
- * the size of the RXFIFO. Write binary 11 across the left
- * most bit, and assert we get 1 back.
- */
- r = 1LL << RX_TOEP_TCP_SUPPRESS_B0_LBN;
- r |= (r << 1);
-
- /* Save the original value */
- falcon_read_q(efhw_kva + RX_CFG_REG_OFST, &rx_cfg);
-
- /* Write and ready the dummy value */
- falcon_write_qq(efhw_kva + RX_CFG_REG_OFST, r, 0);
- falcon_read_q(efhw_kva + RX_CFG_REG_OFST, &r);
-
- /* Restore the original value */
- falcon_write_qq(efhw_kva + RX_CFG_REG_OFST, rx_cfg, 0);
-
- if (r != (1LL << RX_TOEP_TCP_SUPPRESS_B0_LBN)) {
- EFHW_ERR("The FPGA build (%x) RXFIFO size does not "
- "match the software", altera);
- return -EINVAL;
- }
- is_mac_type_1g = (0 != (strap & 2));
-#if FALCON_MAC_SET_TYPE_BY_SPEED
- /* Check the selected strap pins against the MAC speed -
- * and adjust if necessary.
- */
- {
- int speed;
- speed = readl(efhw_kva + MAC0_CTRL_REG_OFST) & 0x3;
- is_mac_type_1g = (speed <= 2);
- }
-#endif
- break;
- case 'C':
- /* Treat like B0 for now, but without the RX FIFO size check
- * (don't need it, and RX_CFG_REG will likely change soon
- * anyway).
- */
- is_mac_type_1g = (0 != (strap & 2));
-#if FALCON_MAC_SET_TYPE_BY_SPEED
- /* Check the selected strap pins against the MAC speed -
- * and adjust if necessary.
- */
- {
- int speed;
- speed = readl(efhw_kva + MAC0_CTRL_REG_OFST) & 0x3;
- is_mac_type_1g = (speed <= 2);
- }
-#endif
+ {
+ volatile char __iomem *efhw_kva = nic->bar_ioaddr;
+ uint32_t altera;
+ altera = readl(efhw_kva + FR_AZ_ALTERA_BUILD_REG_OFST);
+ nic->devtype.in_fpga = (altera != 0);
break;
+ }
default:
- EFHW_ASSERT(0);
- is_mac_type_1g = 0;
break;
}
- nic->fpga_version = altera;
-
- /* We can now set the MAC type correctly based on the strap pins. */
- if (is_mac_type_1g) {
- nic->flags &= ~NIC_FLAG_10G;
- } else {
- /* strap & 4 must be set according to checks above */
- nic->flags |= NIC_FLAG_10G;
- }
- EFHW_NOTICE("Board has %s MAC: strap=%d",
- 0 != (nic->flags & NIC_FLAG_10G) ? "10G" : "1G", strap);
+ nic->flags |= NIC_FLAG_10G;
return 0;
}
return rc;
/* Initialise supporting modules */
- falcon_nic_ipfilter_ctor(nic);
+ rc = falcon_nic_filter_ctor(nic);
+ if (rc < 0)
+ return rc;
#if FALCON_USE_SHADOW_BUFFER_TABLE
CI_ZERO_ARRAY(_falcon_buffer_table, FALCON_BUFFER_TBL_NUM);
IFDEF FALCON's can be removed from
nic.c:efhw_nic_allocate_common_hardware_resources()
*/
- nic->irq_unit = INT_EN_REG_CHAR_OFST;
+ nic->irq_unit = FR_AZ_INT_EN_REG_CHAR_OFST;
/*****************************************************************
* The rest of this function deals with initialization of the NICs
/* TXDP tweaks */
/* ?? bug2396 looks ok */
falcon_nic_tx_cfg(nic, /*unlocked(for non-UDP/TCP)= */ 0);
- falcon_nic_pace_cfg(nic);
+ falcon_nic_pace_cfg(nic, 4, 2);
- /* ?? bug2396
- * netdriver must load first or else must RMW this register */
- falcon_nic_rx_filter_ctl_set(nic, RX_FILTER_CTL_SRCH_LIMIT_TCP_FULL,
- RX_FILTER_CTL_SRCH_LIMIT_TCP_WILD,
- RX_FILTER_CTL_SRCH_LIMIT_UDP_FULL,
- RX_FILTER_CTL_SRCH_LIMIT_UDP_WILD);
+ falcon_nic_set_rx_filter_search_limits_needed(nic);
+ falcon_nic_set_tx_filter_search_limits_needed(nic);
if (!(nic->flags & NIC_FLAG_NO_INTERRUPT)) {
- rc = efhw_keventq_ctor(nic, FALCON_EVQ_CHAR,
+ EFHW_ASSERT(nic->devtype.variant == 'A');
+ rc = efhw_keventq_ctor(nic, FALCON_A_EVQ_CHAR,
&nic->interrupting_evq, ev_handlers);
if (rc < 0) {
EFHW_ERR("%s: efhw_keventq_ctor() failed (%d) evq=%d",
- __FUNCTION__, rc, FALCON_EVQ_CHAR);
+ __FUNCTION__, rc, FALCON_A_EVQ_CHAR);
return rc;
}
}
return rc;
}
- /* allocate IRQ channel */
- rc = falcon_nic_init_irq_channel(nic, 1);
/* ignore failure at user-level for eftest */
if ((rc < 0) && !(nic->options & NIC_OPT_EFTEST))
return rc;
/* An interrupting eventq must start of day ack its read pointer */
q = &nic->interrupting_evq;
rdptr = EFHW_EVENT_OFFSET(q, q, 1) / sizeof(efhw_event_t);
- falcon_nic_evq_ack(nic, FALCON_EVQ_CHAR, rdptr, false);
+ falcon_nic_evq_ack(nic, q->instance, rdptr);
EFHW_NOTICE("%s: ACK evq[%d]:%x", __FUNCTION__,
- FALCON_EVQ_CHAR, rdptr);
+ q->instance, rdptr);
}
static void falcon_nic_interrupt_disable(struct efhw_nic *nic)
}
static void
-falcon_nic_set_interrupt_moderation(struct efhw_nic *nic,
+falcon_nic_set_interrupt_moderation(struct efhw_nic *nic, int evq,
uint32_t val)
{
- falcon_timer_cmd(nic, FALCON_EVQ_CHAR, TIMER_MODE_INT_HLDOFF,
- val / 5);
+ if (evq < 0)
+ evq = nic->interrupting_evq.instance;
+
+ if (nic->devtype.variant < 'C')
+ falcon_ab_timer_tbl_set(nic, evq, FFE_AB_TIMER_MODE_INT_HLDOFF, val / 5);
+ else
+ siena_timer_tbl_set(nic, evq, 1/*enable*/, 1/*interrupting*/,
+ FFE_CZ_TIMER_MODE_INT_HLDOFF, val*10/61);
}
static inline void legacy_irq_ack(struct efhw_nic *nic)
EFHW_ASSERT(!(nic->flags & NIC_FLAG_NO_INTERRUPT));
if (!(nic->flags & NIC_FLAG_MSI)) {
- writel(1, EFHW_KVA(nic) + INT_ACK_REG_CHAR_A1_OFST);
+ writel(1, EFHW_KVA(nic) + FR_AA_INT_ACK_CHAR_OFST);
mmiowb();
/* ?? FIXME: We should be doing a read here to ensure IRQ is
* thoroughly acked before we return from ISR. */
static int falcon_nic_interrupt(struct efhw_nic *nic)
{
- uint32_t *syserr_ptr =
- (uint32_t *) efhw_iopage_ptr(&nic->irq_iobuff);
int handled = 0;
int done_ack = 0;
EFHW_ASSERT(!(nic->flags & NIC_FLAG_NO_INTERRUPT));
- EFHW_ASSERT(syserr_ptr);
-
- /* FIFO fill level interrupt - just log it. */
- if (unlikely(*(syserr_ptr + (DW0_OFST / 4)))) {
- EFHW_WARN("%s: *** FIFO *** %x", __FUNCTION__,
- *(syserr_ptr + (DW0_OFST / 4)));
- *(syserr_ptr + (DW0_OFST / 4)) = 0;
- handled++;
- }
-
- /* Fatal interrupts. */
- if (unlikely(*(syserr_ptr + (DW2_OFST / 4)))) {
- *(syserr_ptr + (DW2_OFST / 4)) = 0;
- falcon_nic_handle_fatal_int(nic);
- handled++;
- }
-
- /* Event queue interrupt. For legacy interrupts we have to check
- * that the interrupt is for us, because it could be shared. */
- if (*(syserr_ptr + (DW1_OFST / 4))) {
- *(syserr_ptr + (DW1_OFST / 4)) = 0;
- /* ACK must come before callback to handler fn. */
- legacy_irq_ack(nic);
- done_ack = 1;
- handled++;
- if (nic->irq_handler)
- nic->irq_handler(nic, 0);
- }
if (unlikely(!done_ack)) {
if (!handled)
static void
falcon_nic_event_queue_enable(struct efhw_nic *nic, uint evq, uint evq_size,
- dma_addr_t q_base_addr, /* not used */
- uint buf_base_id)
+ uint buf_base_id, int interrupting, int enable_dos_p)
{
EFHW_ASSERT(nic);
- /*!\ TODO we can be more efficient if we know whether or not there
- * is a timer attached */
- falcon_timer_cmd(nic, evq, 0 /* disable */ , 0);
+ if (nic->devtype.variant < 'C')
+ /* Whether or not queue has an interrupt depends on
+ * instance number and h/w variant, so [interrupting] is
+ * ignored.
+ */
+ falcon_ab_timer_tbl_set(nic, evq, 0/*disable*/, 0);
+ else
+ siena_timer_tbl_set(nic, evq, 1/*enable*/, interrupting,
+ FFE_CZ_TIMER_MODE_DIS, 0);
- falcon_nic_evq_ptr_tbl(nic, evq, 1, buf_base_id, evq_size);
+ falcon_nic_evq_ptr_tbl(nic, evq, 1, buf_base_id, evq_size, enable_dos_p);
EFHW_TRACE("%s: enable evq %u size %u", __FUNCTION__, evq, evq_size);
}
{
EFHW_ASSERT(nic);
- /*!\ TODO we can be more efficient if we know whether or not there
- * is a timer attached */
- falcon_timer_cmd(nic, evq, 0 /* disable */ , 0);
+ if (nic->devtype.variant < 'C')
+ falcon_ab_timer_tbl_set(nic, evq, 0 /* disable */ , 0);
+ else
+ siena_timer_tbl_set(nic, evq, timer_only /* enable */,
+ 0 /* interrupting */,
+ FFE_CZ_TIMER_MODE_DIS, 0);
if (!timer_only)
- falcon_nic_evq_ptr_tbl(nic, evq, 0, 0, 0);
+ falcon_nic_evq_ptr_tbl(nic, evq, 0, 0, 0, 0);
EFHW_TRACE("%s: disenable evq %u", __FUNCTION__, evq);
}
static void
-falcon_nic_wakeup_request(struct efhw_nic *nic, dma_addr_t q_base_addr,
- int next_i, int evq)
+falcon_nic_wakeup_request(struct efhw_nic *nic, int next_i, int evq)
{
- EFHW_ASSERT(evq > FALCON_EVQ_CHAR);
- falcon_nic_evq_ack(nic, evq, next_i, true);
+ EFHW_ASSERT(evq >= 0);
+ falcon_nic_evq_ack(nic, evq, next_i);
EFHW_TRACE("%s: evq %d next_i %d", __FUNCTION__, evq, next_i);
}
EFHW_NOTICE("%s: evq[%d]->%x", __FUNCTION__, evq, data);
}
-/*--------------------------------------------------------------------
- *
- * Filter support - TODO vary the depth of the search
- *
- *--------------------------------------------------------------------*/
-
-void
-falcon_nic_ipfilter_ctor(struct efhw_nic *nic)
-{
- if (nic->devtype.variant >= 'B' && nic->fpga_version)
- nic->filter_tbl_size = 8 * 1024;
- else
- nic->filter_tbl_size = 16 * 1024;
-
- host_ipfilter_cache_init(nic);
-}
-
-
-static int
-falcon_nic_ipfilter_set(struct efhw_nic *nic, int type, int *_filter_idx,
- int dmaq,
- unsigned saddr_be32, unsigned sport_be16,
- unsigned daddr_be32, unsigned dport_be16)
-{
- FALCON_LOCK_DECL;
- int tcp;
- int full;
- int rss_b0;
- int scat_b0;
- int key, hash1, hash2, idx = -1;
- int k;
- int rc = 0;
- unsigned max_srch = -1;
-
- /* oh joy of joys .. maybe one day we'll optimise */
- unsigned int saddr = ntohl(saddr_be32);
- unsigned int daddr = ntohl(daddr_be32);
- unsigned int sport = ntohs(sport_be16);
- unsigned int dport = ntohs(dport_be16);
-
- __RANGECHCK(sport, SRC_TCP_DEST_UDP_1_WIDTH);
- __RANGECHCK(dport, SRC_TCP_DEST_UDP_1_WIDTH);
-
- tcp = ((type & EFHW_IP_FILTER_TYPE_TCP_MASK) != 0) ? 1 : 0;
- full = ((type & EFHW_IP_FILTER_TYPE_FULL_MASK) != 0) ? 1 : 0;
- rss_b0 = ((type & EFHW_IP_FILTER_TYPE_RSS_B0_MASK) != 0) ? 1 : 0;
- scat_b0 = ((type & EFHW_IP_FILTER_TYPE_NOSCAT_B0_MASK) != 0) ? 0 : 1;
- if (tcp && full)
- max_srch = tcp_full_srch_limit;
- else if (tcp && !full)
- max_srch = tcp_wild_srch_limit;
- else if (!tcp && full)
- max_srch = udp_full_srch_limit;
- else if (!tcp && !full)
- max_srch = udp_wild_srch_limit;
-
- EFHW_TRACE("%s: %x tcp %d full %d max_srch=%d",
- __FUNCTION__, type, tcp, full, max_srch);
-
- /* The second hash function is simply
- * h2(key) = 13 LSB of (key * 2 - 1)
- * And the index(k), or the filter table address for kth search is
- * index(k) = 13 LSB of (h1(key) + k * h2(key))
- */
- key = falcon_hash_get_key(saddr, sport, daddr, dport, tcp, full);
- hash1 = falcon_hash_function1(key, nic->filter_tbl_size);
- hash2 = falcon_hash_function2(key, nic->filter_tbl_size);
-
- /* Avoid race to claim a filter entry */
- FALCON_LOCK_LOCK(nic);
-
- for (k = 0; (unsigned)k < max_srch; k++) {
- idx = falcon_hash_iterator(hash1, hash2, k,
- nic->filter_tbl_size);
-
- EFHW_TRACE("ipfilter_set[%d:%d:%d]: src=%x:%d dest=%x:%d %s",
- *_filter_idx, idx, k,
- saddr, sport, daddr, dport,
- host_ipfilter_cache_active(nic, idx) ?
- "Active" : "Clear");
-
- if (!host_ipfilter_cache_active(nic, idx))
- break;
-
-#if FALCON_FULL_FILTER_CACHE
- /* Check that we are not duplicating the filter */
- if (!host_ipfilter_cache_check_not(nic->index, idx, tcp, full,
- saddr, sport, daddr,
- dport)) {
- EFHW_WARN("%s: ERROR: duplicate filter (disabling "
- "interrupts)", __FUNCTION__);
- FALCON_LOCK_UNLOCK(nic);
- falcon_nic_interrupt_hw_disable(nic);
- return -EINVAL;
- }
-#endif
-
- }
- if (k == max_srch) {
- rc = -EADDRINUSE;
- idx = -1;
- goto fail1;
- }
-
- EFHW_ASSERT(idx < (int)nic->filter_tbl_size);
-
- host_ipfilter_cache_set_addr(nic, idx, dmaq, tcp, full, rss_b0,
- scat_b0, saddr, sport, daddr, dport);
-
- _falcon_nic_ipfilter_set(nic, tcp, full, rss_b0,
- scat_b0, idx, dmaq,
- saddr, sport, daddr, dport);
-
- *_filter_idx = idx;
-
- EFHW_TRACE("%s: filter %x rxq %d src " NIPQUAD_FMT
- ":%d dest " NIPQUAD_FMT ":%d set in %d",
- __FUNCTION__, idx, dmaq,
- NIPQUAD(&saddr), sport, NIPQUAD(&daddr), dport, k);
-
-fail1:
- FALCON_LOCK_UNLOCK(nic);
- return rc;
-}
-
-static void
-falcon_nic_ipfilter_attach(struct efhw_nic *nic, int filter_idx, int dmaq_idx)
-{
- /* Intentionally empty - Falcon attaches and sets the filter
- * in filter_set */
- EFHW_TRACE("%s: attach filter %x with rxq %d - ignored",
- __FUNCTION__, filter_idx, dmaq_idx);
-}
-
-static void falcon_nic_ipfilter_detach(struct efhw_nic *nic, int filter_idx)
-{
- /* Intentionally empty - Falcon attaches and sets the filter
- * in filter_clear */
- EFHW_TRACE("%s: detach filter %x from rxq - ignored",
- __FUNCTION__, filter_idx);
-}
-
-static void falcon_nic_ipfilter_clear(struct efhw_nic *nic, int filter_idx)
-{
- FALCON_LOCK_DECL;
-
- EFHW_TRACE("%s: filter %x", __FUNCTION__, filter_idx);
-
- /* In case the filter has already been freed */
- if (filter_idx == -1)
- return;
-
- FALCON_LOCK_LOCK(nic);
-
- /* if we flush a chained hash then all we need to do is zero it out */
- host_ipfilter_cache_flush(nic, filter_idx);
- _falcon_nic_ipfilter_clear(nic, filter_idx);
-
- FALCON_LOCK_UNLOCK(nic);
- return;
-}
/*--------------------------------------------------------------------
*
static inline void falcon_nic_buffer_table_lazy_commit(struct efhw_nic *nic)
{
+#if defined(__ci_ul_driver__)
+ if (!(nic->options & NIC_OPT_EFTEST))
+ return;
+#endif
/* Do nothing if operating in synchronous mode. */
if (!nic->irq_handler)
FALCON_LOCK_DECL;
int count = 0, rc = 0;
+#if defined(__ci_ul_driver__)
+ if (!(nic->options & NIC_OPT_EFTEST))
+ return;
+#endif
/* We can be called here early days */
if (!nic->irq_handler)
if (count++)
udelay(1);
- if (count > 1000) {
- EFHW_WARN("%s: poll Timeout ***** (%d)", __FUNCTION__,
- nic->buf_commit_outstanding);
+ if (count > MAX_BUF_TBL_READS) {
+ EFHW_ERR("%s: poll Timeout ***** (%d)", __FUNCTION__,
+ nic->buf_commit_outstanding);
nic->buf_commit_outstanding = 0;
return;
}
an event or DMA queue */
FALCON_LOCK_DECL;
+#if defined(__ci_ul_driver__)
+ if (!(nic->options & NIC_OPT_EFTEST))
+ return;
+#endif
/* Do nothing if operating in synchronous mode. */
if (!nic->irq_handler)
*
*--------------------------------------------------------------------*/
-#if BUG5302_WORKAROUND
-
-/* Tx queues can get stuck if the software write pointer is set to an index
- * beyond the configured size of the queue, such that they will not flush.
- * This code can be run before attempting a flush; it will detect the bogus
- * value and reset it. This fixes most instances of this problem, although
- * sometimes it does not work, or we may not detect it in the first place,
- * if the out-of-range value was replaced by an in-range value earlier.
- * (In those cases we have to apply a bigger hammer later, if we see that
- * the queue is still not flushing.)
- */
-static void
-falcon_check_for_bogus_tx_dma_wptr(struct efhw_nic *nic, uint dmaq)
-{
- FALCON_LOCK_DECL;
- uint64_t val_low64, val_high64;
- uint64_t size, hwptr, swptr, val;
- volatile char __iomem *efhw_kva = EFHW_KVA(nic);
- ulong offset = falcon_dma_tx_q_offset(nic, dmaq);
-
- /* Falcon requires 128 bit atomic access for this register */
- FALCON_LOCK_LOCK(nic);
- falcon_read_qq(efhw_kva + offset, &val_low64, &val_high64);
- FALCON_LOCK_UNLOCK(nic);
-
- size = (val_low64 >> TX_DESCQ_SIZE_LBN)
- & __FALCON_MASK64(TX_DESCQ_SIZE_WIDTH);
- size = (1 << size) * 512;
- hwptr = (val_high64 >> __DW3(TX_DESCQ_HW_RPTR_LBN))
- & __FALCON_MASK64(TX_DESCQ_HW_RPTR_WIDTH);
- swptr = (val_low64 >> TX_DESCQ_SW_WPTR_LBN)
- & __FALCON_MASK64(__LW2(TX_DESCQ_SW_WPTR_LBN));
- val = (val_high64)
- &
- __FALCON_MASK64(__DW3
- (TX_DESCQ_SW_WPTR_LBN + TX_DESCQ_SW_WPTR_WIDTH));
- val = val << __LW2(TX_DESCQ_SW_WPTR_LBN);
- swptr = swptr | val;
-
- if (swptr >= size) {
- EFHW_WARN("Resetting bad write pointer for TXQ[%d]", dmaq);
- writel((uint32_t) ((hwptr + 0) & (size - 1)),
- efhw_kva + falcon_tx_dma_page_addr(dmaq) + 12);
- mmiowb();
- }
-}
-
-/* Here's that "bigger hammer": we reset all the pointers (hardware read,
- * hardware descriptor cache read, software write) to zero.
- */
-void falcon_clobber_tx_dma_ptrs(struct efhw_nic *nic, uint dmaq)
-{
- FALCON_LOCK_DECL;
- uint64_t val_low64, val_high64;
- volatile char __iomem *efhw_kva = EFHW_KVA(nic);
- ulong offset = falcon_dma_tx_q_offset(nic, dmaq);
-
- EFHW_WARN("Recovering stuck TXQ[%d]", dmaq);
- FALCON_LOCK_LOCK(nic);
- falcon_read_qq(efhw_kva + offset, &val_low64, &val_high64);
- val_high64 &= ~(__FALCON_MASK64(TX_DESCQ_HW_RPTR_WIDTH)
- << __DW3(TX_DESCQ_HW_RPTR_LBN));
- val_high64 &= ~(__FALCON_MASK64(TX_DC_HW_RPTR_WIDTH)
- << __DW3(TX_DC_HW_RPTR_LBN));
- falcon_write_qq(efhw_kva + offset, val_low64, val_high64);
- mmiowb();
- writel(0, efhw_kva + falcon_tx_dma_page_addr(dmaq) + 12);
- mmiowb();
- FALCON_LOCK_UNLOCK(nic);
-}
-
-#endif
-
static inline int
__falcon_really_flush_tx_dma_channel(struct efhw_nic *nic, uint dmaq)
{
volatile char __iomem *efhw_kva = EFHW_KVA(nic);
uint val;
- EFHW_BUILD_ASSERT(TX_FLUSH_DESCQ_REG_KER_OFST ==
- TX_FLUSH_DESCQ_REG_OFST);
+ __DWCHCK(FRF_AZ_TX_FLUSH_DESCQ_CMD);
+ __DWCHCK(FRF_AZ_TX_FLUSH_DESCQ);
+ __RANGECHCK(dmaq, FRF_AZ_TX_FLUSH_DESCQ_WIDTH);
- __DWCHCK(TX_FLUSH_DESCQ_CMD_LBN, TX_FLUSH_DESCQ_CMD_WIDTH);
- __DWCHCK(TX_FLUSH_DESCQ_LBN, TX_FLUSH_DESCQ_WIDTH);
- __RANGECHCK(dmaq, TX_FLUSH_DESCQ_WIDTH);
-
- val = ((1 << TX_FLUSH_DESCQ_CMD_LBN) | (dmaq << TX_FLUSH_DESCQ_LBN));
+ val = ((1 << FRF_AZ_TX_FLUSH_DESCQ_CMD_LBN) | (dmaq << FRF_AZ_TX_FLUSH_DESCQ_LBN));
EFHW_TRACE("TX DMA flush[%d]", dmaq);
-#if BUG5302_WORKAROUND
- falcon_check_for_bogus_tx_dma_wptr(nic, dmaq);
-#endif
-
/* Falcon requires 128 bit atomic access for this register */
FALCON_LOCK_LOCK(nic);
- falcon_write_qq(efhw_kva + TX_FLUSH_DESCQ_REG_OFST,
+ falcon_write_qq(efhw_kva + FR_AZ_TX_FLUSH_DESCQ_REG_OFST,
val, FALCON_ATOMIC_TX_FLUSH_DESCQ);
mmiowb();
* 3, queue disabled (no flush pending)
* - flush complete
*/
- __DWCHCK(TX_DESCQ_FLUSH_LBN, TX_DESCQ_FLUSH_WIDTH);
- __DW3CHCK(TX_DESCQ_EN_LBN, TX_DESCQ_EN_WIDTH);
- enable = val_high64 & (1 << __DW3(TX_DESCQ_EN_LBN));
- flush_pending = val_low64 & (1 << TX_DESCQ_FLUSH_LBN);
+ __DWCHCK(FRF_AZ_TX_DESCQ_FLUSH);
+ __DW3CHCK(FRF_AZ_TX_DESCQ_EN);
+ enable = val_high64 & (1 << __DW3(FRF_AZ_TX_DESCQ_EN_LBN));
+ flush_pending = val_low64 & (1 << FRF_AZ_TX_DESCQ_FLUSH_LBN);
if (enable && !flush_pending)
return 0;
volatile char __iomem *efhw_kva = EFHW_KVA(nic);
uint val;
- EFHW_BUILD_ASSERT(RX_FLUSH_DESCQ_REG_KER_OFST ==
- RX_FLUSH_DESCQ_REG_OFST);
- __DWCHCK(RX_FLUSH_DESCQ_CMD_LBN, RX_FLUSH_DESCQ_CMD_WIDTH);
- __DWCHCK(RX_FLUSH_DESCQ_LBN, RX_FLUSH_DESCQ_WIDTH);
- __RANGECHCK(dmaq, RX_FLUSH_DESCQ_WIDTH);
+ __DWCHCK(FRF_AZ_RX_FLUSH_DESCQ_CMD);
+ __DWCHCK(FRF_AZ_RX_FLUSH_DESCQ);
+ __RANGECHCK(dmaq, FRF_AZ_RX_FLUSH_DESCQ_WIDTH);
- val = ((1 << RX_FLUSH_DESCQ_CMD_LBN) | (dmaq << RX_FLUSH_DESCQ_LBN));
+ val = ((1 << FRF_AZ_RX_FLUSH_DESCQ_CMD_LBN) | (dmaq << FRF_AZ_RX_FLUSH_DESCQ_LBN));
EFHW_TRACE("RX DMA flush[%d]", dmaq);
/* Falcon requires 128 bit atomic access for this register */
FALCON_LOCK_LOCK(nic);
- falcon_write_qq(efhw_kva + RX_FLUSH_DESCQ_REG_OFST, val,
+ falcon_write_qq(efhw_kva + FR_AZ_RX_FLUSH_DESCQ_REG_OFST, val,
FALCON_ATOMIC_RX_FLUSH_DESCQ);
mmiowb();
FALCON_LOCK_UNLOCK(nic);
falcon_read_q(efhw_kva + offset, &val);
FALCON_LOCK_UNLOCK(nic);
- __DWCHCK(RX_DESCQ_EN_LBN, RX_DESCQ_EN_WIDTH);
+ __DWCHCK(FRF_AZ_RX_DESCQ_EN);
- /* is it enabled? */
- return (val & (1 << RX_DESCQ_EN_LBN))
- ? 0 : -EAGAIN;
+ /* test if channel is still enabled */
+ return (val & (1 << FRF_AZ_RX_DESCQ_EN_LBN)) ? 0 : -EAGAIN;
}
static int falcon_flush_rx_dma_channel(struct efhw_nic *nic, uint dmaq)
{
- int rc;
- rc = __falcon_is_rx_dma_channel_flushed(nic, dmaq);
- if (rc < 0) {
- EFHW_ERR("%s: failed %d", __FUNCTION__, rc);
- return rc;
- }
return __falcon_really_flush_rx_dma_channel(nic, dmaq);
}
case TX_DESCQ_FLS_DONE_EV_DECODE:
EFHW_TRACE("TX[%d] flushed",
(int)FALCON_EVENT_TX_FLUSH_Q_ID(ev));
+#if !defined(__ci_ul_driver__)
efhw_handle_txdmaq_flushed(nic, h, ev);
+#endif
break;
case RX_DESCQ_FLS_DONE_EV_DECODE:
EFHW_TRACE("RX[%d] flushed",
(int)FALCON_EVENT_TX_FLUSH_Q_ID(ev));
+#if !defined(__ci_ul_driver__)
efhw_handle_rxdmaq_flushed(nic, h, ev);
+#endif
break;
case SRM_UPD_DONE_EV_DECODE:
return 0;
}
+
/*--------------------------------------------------------------------
*
- * Abstraction Layer Hooks
+ * Filter search depth control
*
*--------------------------------------------------------------------*/
-struct efhw_func_ops falcon_char_functional_units = {
- falcon_nic_close_hardware,
- falcon_nic_init_hardware,
- falcon_nic_interrupt,
- falcon_nic_interrupt_enable,
- falcon_nic_interrupt_disable,
- falcon_nic_set_interrupt_moderation,
- falcon_nic_event_queue_enable,
- falcon_nic_event_queue_disable,
- falcon_nic_wakeup_request,
- falcon_nic_sw_event,
- falcon_nic_ipfilter_set,
- falcon_nic_ipfilter_attach,
- falcon_nic_ipfilter_detach,
- falcon_nic_ipfilter_clear,
- falcon_dmaq_tx_q_init,
- falcon_dmaq_rx_q_init,
- falcon_dmaq_tx_q_disable,
- falcon_dmaq_rx_q_disable,
+void
+falcon_nic_get_rx_filter_search_limits(struct efhw_nic *nic,
+ struct efhw_filter_search_limits *lim,
+ int use_raw_values)
+{
+ volatile char __iomem *efhw_kva = EFHW_KVA(nic);
+ FALCON_LOCK_DECL;
+ uint64_t q0, q1;
+ unsigned ff = (use_raw_values ? 0 : RX_FILTER_CTL_SRCH_FUDGE_FULL);
+ unsigned wf = (use_raw_values ? 0 : RX_FILTER_CTL_SRCH_FUDGE_WILD);
+
+ FALCON_LOCK_LOCK(nic);
+ falcon_read_qq(efhw_kva + FR_AZ_RX_FILTER_CTL_REG_OFST, &q0, &q1);
+ FALCON_LOCK_UNLOCK(nic);
+
+ lim->tcp_full = Q0_READ(q0, FRF_AZ_TCP_FULL_SRCH_LIMIT) - ff;
+ lim->tcp_wild = Q0_READ(q0, FRF_AZ_TCP_WILD_SRCH_LIMIT) - wf;
+ lim->udp_full = Q0_READ(q0, FRF_AZ_UDP_FULL_SRCH_LIMIT) - ff;
+ lim->udp_wild = Q0_READ(q0, FRF_AZ_UDP_WILD_SRCH_LIMIT) - wf;
+ if (nic->devtype.variant >= 'C') {
+ lim->mac_full =
+ Q1_READ(q1, FRF_CZ_ETHERNET_FULL_SEARCH_LIMIT) - ff;
+ lim->mac_wild =
+ Q1_READ(q1, FRF_CZ_ETHERNET_WILDCARD_SEARCH_LIMIT) - wf;
+ } else {
+ lim->mac_full = 0;
+ lim->mac_wild = 0;
+ }
+}
+EXPORT_SYMBOL(falcon_nic_get_rx_filter_search_limits);
+
+
+static void
+__falcon_nic_set_rx_filter_search_limits(struct efhw_nic *nic,
+ struct efhw_filter_search_limits *lim,
+ int use_raw_values)
+{
+ volatile char __iomem *efhw_kva = EFHW_KVA(nic);
+ uint64_t q0, q1;
+ unsigned ff = (use_raw_values ? 0 : RX_FILTER_CTL_SRCH_FUDGE_FULL);
+ unsigned wf = (use_raw_values ? 0 : RX_FILTER_CTL_SRCH_FUDGE_WILD);
+
+ falcon_read_qq(efhw_kva + FR_AZ_RX_FILTER_CTL_REG_OFST, &q0, &q1);
+
+ q0 &= ~Q0_MASK(FRF_AZ_TCP_FULL_SRCH_LIMIT);
+ q0 &= ~Q0_MASK(FRF_AZ_TCP_WILD_SRCH_LIMIT);
+ q0 &= ~Q0_MASK(FRF_AZ_UDP_FULL_SRCH_LIMIT);
+ q0 &= ~Q0_MASK(FRF_AZ_UDP_WILD_SRCH_LIMIT);
+ q0 |= Q0_VALUE(FRF_AZ_TCP_FULL_SRCH_LIMIT, lim->tcp_full + ff);
+ q0 |= Q0_VALUE(FRF_AZ_TCP_WILD_SRCH_LIMIT, lim->tcp_wild + wf);
+ q0 |= Q0_VALUE(FRF_AZ_UDP_FULL_SRCH_LIMIT, lim->udp_full + ff);
+ q0 |= Q0_VALUE(FRF_AZ_UDP_WILD_SRCH_LIMIT, lim->udp_wild + wf);
+ nic->tcp_full_srch.max = lim->tcp_full + ff
+ - RX_FILTER_CTL_SRCH_FUDGE_FULL;
+ nic->tcp_wild_srch.max = lim->tcp_wild + wf
+ - RX_FILTER_CTL_SRCH_FUDGE_WILD;
+ nic->udp_full_srch.max = lim->udp_full + ff
+ - RX_FILTER_CTL_SRCH_FUDGE_FULL;
+ nic->udp_wild_srch.max = lim->udp_wild + wf
+ - RX_FILTER_CTL_SRCH_FUDGE_WILD;
+
+ if (nic->devtype.variant >= 'C') {
+ q1 &= ~Q1_MASK(FRF_CZ_ETHERNET_FULL_SEARCH_LIMIT);
+ q1 &= ~Q1_MASK(FRF_CZ_ETHERNET_WILDCARD_SEARCH_LIMIT);
+ q1 |= Q1_VALUE(FRF_CZ_ETHERNET_FULL_SEARCH_LIMIT,
+ lim->mac_full + ff);
+ q1 |= Q1_VALUE(FRF_CZ_ETHERNET_WILDCARD_SEARCH_LIMIT,
+ lim->mac_wild + wf);
+ nic->mac_full_srch.max = lim->mac_full + ff
+ - RX_FILTER_CTL_SRCH_FUDGE_FULL;
+ nic->mac_wild_srch.max = lim->mac_wild + wf
+ - RX_FILTER_CTL_SRCH_FUDGE_WILD;
+ }
+
+ falcon_write_qq(efhw_kva + FR_AZ_RX_FILTER_CTL_REG_OFST, q0, q1);
+ mmiowb();
+}
+
+
+void
+falcon_nic_set_rx_filter_search_limits(struct efhw_nic *nic,
+ struct efhw_filter_search_limits *lim,
+ int use_raw_values)
+{
+ FALCON_LOCK_DECL;
+ FALCON_LOCK_LOCK(nic);
+ __falcon_nic_set_rx_filter_search_limits(nic, lim, use_raw_values);
+ FALCON_LOCK_UNLOCK(nic);
+}
+EXPORT_SYMBOL(falcon_nic_set_rx_filter_search_limits);
+
+
+void
+falcon_nic_get_tx_filter_search_limits(struct efhw_nic *nic,
+ struct efhw_filter_search_limits *lim,
+ int use_raw_values)
+{
+ volatile char __iomem *efhw_kva = EFHW_KVA(nic);
+ FALCON_LOCK_DECL;
+ uint64_t q0, q1;
+ unsigned ff = (use_raw_values ? 0 : TX_FILTER_CTL_SRCH_FUDGE_FULL);
+ unsigned wf = (use_raw_values ? 0 : TX_FILTER_CTL_SRCH_FUDGE_WILD);
+
+ if (nic->devtype.variant < 'C') {
+ memset(lim, 0, sizeof(*lim));
+ return;
+ }
+
+ FALCON_LOCK_LOCK(nic);
+ falcon_read_qq(efhw_kva + FR_AZ_TX_CFG_REG_OFST, &q0, &q1);
+ FALCON_LOCK_UNLOCK(nic);
+
+ lim->tcp_full = Q1_READ(q1, FRF_CZ_TX_TCPIP_FILTER_FULL_SEARCH_RANGE) - ff;
+ lim->tcp_wild = Q1_READ(q1, FRF_CZ_TX_TCPIP_FILTER_WILD_SEARCH_RANGE) - wf;
+ lim->udp_full = Q1_READ(q1, FRF_CZ_TX_UDPIP_FILTER_FULL_SEARCH_RANGE) - ff;
+ lim->udp_wild = Q1_READ(q1, FRF_CZ_TX_UDPIP_FILTER_WILD_SEARCH_RANGE) - wf;
+ lim->mac_full = Q1_READ(q1, FRF_CZ_TX_ETH_FILTER_FULL_SEARCH_RANGE) - ff;
+ lim->mac_wild = Q1_READ(q1, FRF_CZ_TX_ETH_FILTER_WILD_SEARCH_RANGE) - wf;
+}
+EXPORT_SYMBOL(falcon_nic_get_tx_filter_search_limits);
+
+
+static void
+__falcon_nic_set_tx_filter_search_limits(struct efhw_nic *nic,
+ struct efhw_filter_search_limits *lim,
+ int use_raw_values)
+{
+ volatile char __iomem *efhw_kva = EFHW_KVA(nic);
+ uint64_t q0, q1;
+ unsigned ff = (use_raw_values ? 0 : TX_FILTER_CTL_SRCH_FUDGE_FULL);
+ unsigned wf = (use_raw_values ? 0 : TX_FILTER_CTL_SRCH_FUDGE_WILD);
+
+ if (nic->devtype.variant < 'C')
+ return;
+
+ falcon_read_qq(efhw_kva + FR_AZ_TX_CFG_REG_OFST, &q0, &q1);
+
+ q1 &= ~Q1_MASK(FRF_CZ_TX_TCPIP_FILTER_FULL_SEARCH_RANGE);
+ q1 &= ~Q1_MASK(FRF_CZ_TX_TCPIP_FILTER_WILD_SEARCH_RANGE);
+ q1 &= ~Q1_MASK(FRF_CZ_TX_UDPIP_FILTER_FULL_SEARCH_RANGE);
+ q1 &= ~Q1_MASK(FRF_CZ_TX_UDPIP_FILTER_WILD_SEARCH_RANGE);
+ q1 &= ~Q1_MASK(FRF_CZ_TX_ETH_FILTER_FULL_SEARCH_RANGE);
+ q1 &= ~Q1_MASK(FRF_CZ_TX_ETH_FILTER_WILD_SEARCH_RANGE);
+ q1 |= Q1_VALUE(FRF_CZ_TX_TCPIP_FILTER_FULL_SEARCH_RANGE, lim->tcp_full + ff);
+ q1 |= Q1_VALUE(FRF_CZ_TX_TCPIP_FILTER_WILD_SEARCH_RANGE,
+ lim->tcp_wild + wf);
+ q1 |= Q1_VALUE(FRF_CZ_TX_UDPIP_FILTER_FULL_SEARCH_RANGE, lim->udp_full + ff);
+ q1 |= Q1_VALUE(FRF_CZ_TX_UDPIP_FILTER_WILD_SEARCH_RANGE,
+ lim->udp_wild + wf);
+ q1 |= Q1_VALUE(FRF_CZ_TX_ETH_FILTER_FULL_SEARCH_RANGE, lim->mac_full + ff);
+ q1 |= Q1_VALUE(FRF_CZ_TX_ETH_FILTER_WILD_SEARCH_RANGE, lim->mac_wild + wf);
+
+ nic->tx_tcp_full_srch.max = lim->tcp_full + ff
+ - TX_FILTER_CTL_SRCH_FUDGE_FULL;
+ nic->tx_tcp_wild_srch.max = lim->tcp_wild + wf
+ - TX_FILTER_CTL_SRCH_FUDGE_WILD;
+ nic->tx_udp_full_srch.max = lim->udp_full + ff
+ - TX_FILTER_CTL_SRCH_FUDGE_FULL;
+ nic->tx_udp_wild_srch.max = lim->udp_wild + wf
+ - TX_FILTER_CTL_SRCH_FUDGE_WILD;
+ nic->tx_mac_full_srch.max = lim->mac_full + ff
+ - TX_FILTER_CTL_SRCH_FUDGE_FULL;
+ nic->tx_mac_wild_srch.max = lim->mac_wild + wf
+ - TX_FILTER_CTL_SRCH_FUDGE_WILD;
+
+ falcon_write_qq(efhw_kva + FR_AZ_TX_CFG_REG_OFST, q0, q1);
+ mmiowb();
+}
+
+
+void
+falcon_nic_set_tx_filter_search_limits(struct efhw_nic *nic,
+ struct efhw_filter_search_limits *lim,
+ int use_raw_values)
+{
+ FALCON_LOCK_DECL;
+ FALCON_LOCK_LOCK(nic);
+ __falcon_nic_set_tx_filter_search_limits(nic, lim, use_raw_values);
+ FALCON_LOCK_UNLOCK(nic);
+}
+EXPORT_SYMBOL(falcon_nic_set_tx_filter_search_limits);
+
+
+#undef READ_Q0
+#undef Q0_MASK
+#undef Q0_VALUE
+#undef READ_Q1
+#undef Q1_MASK
+#undef Q1_VALUE
+
+
+static void
+__falcon_nic_set_rx_filter_search_limits_needed(struct efhw_nic *nic)
+{
+ struct efhw_filter_search_limits lim;
+ lim.tcp_full = nic->tcp_full_srch.needed;
+ lim.tcp_wild = nic->tcp_wild_srch.needed;
+ lim.udp_full = nic->udp_full_srch.needed;
+ lim.udp_wild = nic->udp_wild_srch.needed;
+ lim.mac_full = nic->mac_full_srch.needed;
+ lim.mac_wild = nic->mac_wild_srch.needed;
+ __falcon_nic_set_rx_filter_search_limits(nic, &lim, 0);
+}
+
+
+static void falcon_nic_set_rx_filter_search_limits_needed(struct efhw_nic *nic)
+{
+ FALCON_LOCK_DECL;
+ FALCON_LOCK_LOCK(nic);
+ __falcon_nic_set_rx_filter_search_limits_needed(nic);
+ FALCON_LOCK_UNLOCK(nic);
+}
+
+
+static void
+__falcon_nic_set_tx_filter_search_limits_needed(struct efhw_nic *nic)
+{
+ struct efhw_filter_search_limits lim;
+ lim.tcp_full = nic->tx_tcp_full_srch.needed;
+ lim.tcp_wild = nic->tx_tcp_wild_srch.needed;
+ lim.udp_full = nic->tx_udp_full_srch.needed;
+ lim.udp_wild = nic->tx_udp_wild_srch.needed;
+ lim.mac_full = nic->tx_mac_full_srch.needed;
+ lim.mac_wild = nic->tx_mac_wild_srch.needed;
+ __falcon_nic_set_tx_filter_search_limits(nic, &lim, 0);
+}
+
+
+static void falcon_nic_set_tx_filter_search_limits_needed(struct efhw_nic *nic)
+{
+ FALCON_LOCK_DECL;
+ FALCON_LOCK_LOCK(nic);
+ __falcon_nic_set_tx_filter_search_limits_needed(nic);
+ FALCON_LOCK_UNLOCK(nic);
+}
+
+
+/*--------------------------------------------------------------------
+ *
+ * New unified filter API
+ *
+ *--------------------------------------------------------------------*/
+
+
+#if FALCON_FULL_FILTER_CACHE
+static inline struct efhw_filter_spec *
+filter_spec_cache_entry(struct efhw_nic *nic, enum efhw_filter_type type,
+ int filter_idx)
+{
+ EFHW_ASSERT(nic->filter_spec_cache);
+ return &nic->filter_spec_cache[type * FALCON_FILTER_TBL_NUM
+ + filter_idx];
+}
+#endif
+
+
+static int filter_is_active(struct efhw_nic *nic, enum efhw_filter_type type,
+ int filter_idx)
+{
+ return (nic->filter_in_use[filter_idx] & (1 << type)) ? 1 : 0;
+}
+
+
+static void set_filter_cache_entry(struct efhw_nic *nic,
+ struct efhw_filter_spec *spec,
+ int filter_idx)
+{
+ nic->filter_in_use[filter_idx] |= (1 << spec->type);
+#if FALCON_FULL_FILTER_CACHE
+ memcpy(filter_spec_cache_entry(nic, spec->type, filter_idx), spec,
+ sizeof(struct efhw_filter_spec));
+#endif
+}
+
+
+static void clear_filter_cache_entry(struct efhw_nic *nic,
+ enum efhw_filter_type type,
+ int filter_idx)
+{
+ nic->filter_in_use[filter_idx] &= ~(1 << type);
+#if FALCON_FULL_FILTER_CACHE
+ memset(filter_spec_cache_entry(nic, type, filter_idx), 0,
+ sizeof(struct efhw_filter_spec));
+#endif
+}
+
+
+#if FALCON_FULL_FILTER_CACHE
+static int filter_is_duplicate(struct efhw_nic *nic,
+ struct efhw_filter_spec *spec, int filter_idx)
+{
+ struct efhw_filter_spec *cmp;
+
+ cmp = filter_spec_cache_entry(nic, spec->type, filter_idx);
+
+ EFHW_ASSERT(filter_is_active(nic, spec->type, filter_idx));
+ EFHW_ASSERT(spec->type == cmp->type);
+
+ switch (spec->type) {
+
+ case EFHW_FILTER_TYPE_IP:
+ return (spec->u.ip.saddr_le32 == cmp->u.ip.saddr_le32) &&
+ (spec->u.ip.daddr_le32 == cmp->u.ip.daddr_le32) &&
+ (spec->u.ip.sport_le16 == cmp->u.ip.sport_le16) &&
+ (spec->u.ip.dport_le16 == cmp->u.ip.dport_le16) &&
+ (spec->u.ip.tcp == cmp->u.ip.tcp) &&
+ (spec->u.ip.full == cmp->u.ip.full);
+
+ case EFHW_FILTER_TYPE_MAC:
+ return (!memcmp(spec->u.mac.mac, cmp->u.mac.mac, 6)) &&
+ (spec->u.mac.vlan_tag == cmp->u.mac.vlan_tag) &&
+ (spec->u.mac.full == cmp->u.mac.full);
+
+ case EFHW_FILTER_TYPE_TX_IP:
+ return (spec->u.tx_ip.saddr_le32 == cmp->u.tx_ip.saddr_le32) &&
+ (spec->u.tx_ip.daddr_le32 == cmp->u.tx_ip.daddr_le32) &&
+ (spec->u.tx_ip.sport_le16 == cmp->u.tx_ip.sport_le16) &&
+ (spec->u.tx_ip.dport_le16 == cmp->u.tx_ip.dport_le16) &&
+ (spec->u.tx_ip.tcp == cmp->u.tx_ip.tcp) &&
+ (spec->u.tx_ip.full == cmp->u.tx_ip.full);
+
+ case EFHW_FILTER_TYPE_TX_MAC:
+ return (!memcmp(spec->u.tx_mac.mac, cmp->u.tx_mac.mac, 6)) &&
+ (spec->u.tx_mac.vlan_tag == cmp->u.tx_mac.vlan_tag) &&
+ (spec->u.tx_mac.full == cmp->u.tx_mac.full);
+
+ default:
+ EFHW_ASSERT(0);
+ return 0;
+ }
+}
+#endif
+
+
+static void common_build_ip_filter(struct efhw_nic *nic, int tcp, int full,
+ int rss, int scatter, int tx, uint dmaq_id,
+ unsigned saddr_le32, unsigned sport_le16,
+ unsigned daddr_le32, unsigned dport_le16,
+ uint64_t *q0, uint64_t *q1)
+{
+ uint64_t v1, v2, v3, v4;
+ unsigned tmp_port_le16;
+
+ if (!full) {
+ if (tx) {
+ daddr_le32 = 0;
+ dport_le16 = 0;
+ } else {
+ saddr_le32 = 0;
+ sport_le16 = 0;
+ }
+ if (!tcp) {
+ tmp_port_le16 = sport_le16;
+ sport_le16 = dport_le16;
+ dport_le16 = tmp_port_le16;
+ }
+ }
+
+ v4 = (((!tcp) << __DW4(FRF_AZ_TCP_UDP_LBN)) |
+ (dmaq_id << __DW4(FRF_AZ_RXQ_ID_LBN)));
+
+ switch (nic->devtype.variant) {
+ case 'A':
+ EFHW_ASSERT(!rss);
+ break;
+ case 'B':
+ case 'C':
+ v4 |= scatter << __DW4(FRF_BZ_SCATTER_EN_LBN);
+ v4 |= rss << __DW4(FRF_BZ_RSS_EN_LBN);
+ break;
+ default:
+ EFHW_ASSERT(0);
+ break;
+ }
+
+ v3 = daddr_le32;
+ v2 = ((dport_le16 << __DW2(FRF_AZ_DEST_PORT_TCP_LBN)) |
+ (__HIGH(saddr_le32, FRF_AZ_SRC_IP)));
+ v1 = ((__LOW(saddr_le32, FRF_AZ_SRC_IP)) |
+ (sport_le16 << FRF_AZ_SRC_TCP_DEST_UDP_LBN));
+
+ *q0 = (v2 << 32) | v1;
+ *q1 = (v4 << 32) | v3;
+}
+
+
+static void common_build_mac_filter(struct efhw_nic *nic, int ip_override,
+ int full, int rss, int scatter,
+ uint dmaq_id, unsigned char *mac,
+ unsigned vlan, uint64_t *q0, uint64_t *q1)
+{
+ uint64_t v1, v2, v3, v4;
+
+ EFHW_ASSERT(nic->devtype.variant == 'C');
+
+ /* MJS TBD: bit numbers from header, etc. */
+#ifdef HEADER_REVIEW
+#warning ok this needs some fixing
+#endif
+ v4 = 0;
+ v3 = (rss << __DW3(FRF_CZ_RMFT_RSS_EN_LBN)) |
+ (scatter << __DW3(FRF_CZ_RMFT_SCATTER_EN_LBN)) |
+ (ip_override << __DW3(FRF_CZ_RMFT_IP_OVERRIDE_LBN)) |
+ (__HIGH2(dmaq_id, FRF_CZ_RMFT_RXQ_ID));
+
+ v2 = (__LOW2(dmaq_id, FRF_CZ_RMFT_RXQ_ID)) |
+ ((!full) << __DW2(FRF_CZ_RMFT_WILDCARD_MATCH_LBN)) |
+ (mac[0] << 20) | (mac[1] << 12) | (mac[2] << 4) |
+ ((mac[3] & 0xf0) >> 4);
+ v1 = ((mac[3] & 0x0f) << 28) | (mac[4] << 20) | (mac[5] << 12) |
+ vlan;
+
+ *q0 = (v2 << 32) | v1;
+ *q1 = (v4 << 32) | v3;
+}
+
+
+static void build_filter(struct efhw_nic *nic, struct efhw_filter_spec *spec,
+ unsigned *key, unsigned *tbl_size,
+ struct efhw_filter_depth **depth,
+ uint64_t *q0, uint64_t *q1)
+{
+ switch (spec->type) {
+
+ case EFHW_FILTER_TYPE_IP:
+ *key = falcon_hash_get_ip_key(spec->u.ip.saddr_le32,
+ spec->u.ip.sport_le16,
+ spec->u.ip.daddr_le32,
+ spec->u.ip.dport_le16,
+ spec->u.ip.tcp,
+ spec->u.ip.full);
+ *tbl_size = nic->ip_filter_tbl_size;
+ if (spec->u.ip.tcp && spec->u.ip.full)
+ *depth = &nic->tcp_full_srch;
+ else if (spec->u.ip.tcp && !spec->u.ip.full)
+ *depth = &nic->tcp_wild_srch;
+ else if (!spec->u.ip.tcp && spec->u.ip.full)
+ *depth = &nic->udp_full_srch;
+ else
+ *depth = &nic->udp_wild_srch;
+ common_build_ip_filter(nic, spec->u.ip.tcp, spec->u.ip.full,
+ spec->u.ip.rss, spec->u.ip.scatter, 0,
+ spec->dmaq_id,
+ spec->u.ip.saddr_le32,
+ spec->u.ip.sport_le16,
+ spec->u.ip.daddr_le32,
+ spec->u.ip.dport_le16,
+ q0, q1);
+ break;
+
+ case EFHW_FILTER_TYPE_MAC:
+ *key = falcon_hash_get_mac_key(spec->u.mac.mac,
+ spec->u.mac.vlan_tag,
+ spec->u.mac.full);
+ *tbl_size = nic->mac_filter_tbl_size;
+ if (spec->u.mac.full)
+ *depth = &nic->mac_full_srch;
+ else
+ *depth = &nic->mac_wild_srch;
+ common_build_mac_filter(nic, spec->u.mac.ip_override,
+ spec->u.mac.full,
+ spec->u.mac.rss, spec->u.mac.scatter,
+ spec->dmaq_id,
+ spec->u.mac.mac, spec->u.mac.vlan_tag,
+ q0, q1);
+ break;
+
+ case EFHW_FILTER_TYPE_TX_IP:
+ *key = falcon_hash_get_tx_ip_key(spec->u.tx_ip.saddr_le32,
+ spec->u.tx_ip.sport_le16,
+ spec->u.tx_ip.daddr_le32,
+ spec->u.tx_ip.dport_le16,
+ spec->u.tx_ip.tcp,
+ spec->u.tx_ip.full,
+ spec->dmaq_id);
+ *tbl_size = nic->tx_ip_filter_tbl_size;
+ if (spec->u.tx_ip.tcp && spec->u.tx_ip.full)
+ *depth = &nic->tx_tcp_full_srch;
+ else if (spec->u.tx_ip.tcp && !spec->u.tx_ip.full)
+ *depth = &nic->tx_tcp_wild_srch;
+ else if (!spec->u.tx_ip.tcp && spec->u.tx_ip.full)
+ *depth = &nic->tx_udp_full_srch;
+ else
+ *depth = &nic->tx_udp_wild_srch;
+ common_build_ip_filter(nic, spec->u.tx_ip.tcp,
+ spec->u.tx_ip.full, 0, 0, 1,
+ spec->dmaq_id,
+ spec->u.tx_ip.saddr_le32,
+ spec->u.tx_ip.sport_le16,
+ spec->u.tx_ip.daddr_le32,
+ spec->u.tx_ip.dport_le16,
+ q0, q1);
+ break;
+
+ case EFHW_FILTER_TYPE_TX_MAC:
+ *key = falcon_hash_get_tx_mac_key(spec->u.tx_mac.mac,
+ spec->u.tx_mac.vlan_tag,
+ spec->u.tx_mac.full,
+ spec->dmaq_id);
+ *tbl_size = nic->tx_mac_filter_tbl_size;
+ if (spec->u.tx_mac.full)
+ *depth = &nic->tx_mac_full_srch;
+ else
+ *depth = &nic->tx_mac_wild_srch;
+ common_build_mac_filter(nic, 0, spec->u.tx_mac.full, 0, 0,
+ spec->dmaq_id,
+ spec->u.tx_mac.mac,
+ spec->u.tx_mac.vlan_tag,
+ q0, q1);
+ break;
+
+ default:
+ EFHW_ASSERT(0);
+ }
+}
+
+
+#if FALCON_VERIFY_FILTERS
+static void verify_filters(struct efhw_nic *nic, enum efhw_filter_type type)
+{
+ unsigned table_offset, table_stride;
+ unsigned i, dummy_key, dummy_tbl_size;
+ struct efhw_filter_depth *dummy_depth;
+ unsigned filter_tbl_size;
+ struct efhw_filter_spec *spec;
+ uint64_t q0_expect, q1_expect, q0_got, q1_got;
+
+ switch (type) {
+
+ case EFHW_FILTER_TYPE_IP:
+ filter_tbl_size = nic->ip_filter_tbl_size;
+ table_offset = RX_FILTER_TBL0_OFST;
+ table_stride = 2 * FALCON_REGISTER128;
+ break;
+
+ case EFHW_FILTER_TYPE_MAC:
+ filter_tbl_size = nic->mac_filter_tbl_size;
+ table_offset = RX_FILTER_TBL1_OFST;
+ table_stride = 2 * FALCON_REGISTER128;
+ break;
+
+ case EFHW_FILTER_TYPE_TX_IP:
+ filter_tbl_size = nic->tx_ip_filter_tbl_size;
+ table_offset = 0xFC0000; /* MJS TBD #define */
+ table_stride = FALCON_REGISTER128;
+ break;
+
+ case EFHW_FILTER_TYPE_TX_MAC:
+ filter_tbl_size = nic->tx_mac_filter_tbl_size;
+ table_offset = 0xFE0000; /* MJS TBD #define */
+ table_stride = FALCON_REGISTER128;
+ break;
+
+ default:
+ EFHW_ASSERT(0);
+ return;
+ }
+
+ for (i = 0; i < filter_tbl_size; i++) {
+ if (!filter_is_active(nic, type, i))
+ continue;
+
+ spec = filter_spec_cache_entry(nic, type, i);
+
+ build_filter(nic, spec, &dummy_key, &dummy_tbl_size,
+ &dummy_depth, &q0_expect, &q1_expect);
+
+ falcon_read_qq(EFHW_KVA(nic) + table_offset + i * table_stride,
+ &q0_got, &q1_got);
+
+ if ((q0_got != q0_expect) || (q1_got != q1_expect)) {
+ falcon_write_qq(EFHW_KVA(nic) + 0x300,
+ q0_got, q1_got);
+ EFHW_ERR("ERROR: RX-filter[%d][%d] was "
+ "%"PRIx64":%" PRIx64" expected "
+ "%"PRIx64":%"PRIx64,
+ nic->index, i, q0_got, q1_got,
+ q0_expect, q1_expect);
+ }
+ }
+}
+#endif
+
+
+static void write_filter_table_entry(struct efhw_nic *nic,
+ enum efhw_filter_type type,
+ unsigned filter_idx,
+ uint64_t q0, uint64_t q1)
+{
+ unsigned table_offset, table_stride, offset;
+
+ switch (type) {
+
+ case EFHW_FILTER_TYPE_IP:
+ EFHW_ASSERT(filter_idx < nic->ip_filter_tbl_size);
+ table_offset = FR_AZ_RX_FILTER_TBL0_OFST;
+ table_stride = FR_AZ_RX_FILTER_TBL0_STEP;
+ break;
+
+ case EFHW_FILTER_TYPE_MAC:
+ EFHW_ASSERT(nic->devtype.variant == 'C');
+ EFHW_ASSERT(filter_idx < nic->mac_filter_tbl_size);
+ table_offset = FR_CZ_RX_MAC_FILTER_TBL0_OFST;
+ table_stride = FR_CZ_RX_MAC_FILTER_TBL0_STEP;
+ break;
+
+ case EFHW_FILTER_TYPE_TX_IP:
+ EFHW_ASSERT(filter_idx < nic->tx_ip_filter_tbl_size);
+ table_offset = FR_CZ_TX_FILTER_TBL0_OFST;
+ table_stride = FR_CZ_TX_FILTER_TBL0_STEP;
+ break;
+
+ case EFHW_FILTER_TYPE_TX_MAC:
+ EFHW_ASSERT(filter_idx < nic->tx_mac_filter_tbl_size);
+ table_offset = FR_CZ_TX_MAC_FILTER_TBL0_OFST;
+ table_stride = FR_CZ_TX_MAC_FILTER_TBL0_STEP;
+ break;
+
+ default:
+ EFHW_ASSERT(0);
+ return;
+ }
+
+ offset = table_offset + filter_idx * table_stride;
+ falcon_write_qq(EFHW_KVA(nic) + offset, q0, q1);
+ mmiowb();
+
+#if FALCON_VERIFY_FILTERS
+ {
+ uint64_t q0read, q1read;
+
+ /* Read a different entry first - ensure BIU flushed shadow */
+ falcon_read_qq(EFHW_KVA(nic) + offset + 0x10, &q0read, &q1read);
+ falcon_read_qq(EFHW_KVA(nic) + offset, &q0read, &q1read);
+ EFHW_ASSERT(q0read == q0);
+ EFHW_ASSERT(q1read == q1);
+
+ verify_filters(nic, type);
+ }
+#endif
+}
+
+
+static int falcon_nic_filter_set(struct efhw_nic *nic,
+ struct efhw_filter_spec *spec,
+ int *filter_idx_out)
+{
+ FALCON_LOCK_DECL;
+ unsigned key = 0, tbl_size = 0, hash1, hash2;
+ struct efhw_filter_depth *depth = NULL;
+ int probes, filter_idx = -1;
+ int rc = 0;
+ uint64_t q0, q1;
+
+ build_filter(nic, spec, &key, &tbl_size, &depth, &q0, &q1);
+
+ if (tbl_size == 0)
+ return -EINVAL;
+
+ EFHW_TRACE("%s: type %d depth->max=%d", __FUNCTION__, spec->type,
+ depth->max);
+
+ hash1 = falcon_hash_function1(key, tbl_size);
+ hash2 = falcon_hash_function2(key, tbl_size);
+
+ FALCON_LOCK_LOCK(nic);
+
+ for (probes=1, filter_idx = hash1 & (tbl_size - 1);
+ filter_is_active(nic, spec->type, filter_idx); ++probes) {
+ if (filter_is_duplicate(nic, spec, filter_idx)) {
+ rc = -EEXIST;
+ goto fail1;
+ }
+ filter_idx = (filter_idx + hash2) & (tbl_size - 1);
+ }
+
+ if (depth->needed < probes) {
+ depth->needed = probes;
+ switch (spec->type) {
+ case EFHW_FILTER_TYPE_IP:
+ case EFHW_FILTER_TYPE_MAC:
+ __falcon_nic_set_rx_filter_search_limits_needed(nic);
+ break;
+ case EFHW_FILTER_TYPE_TX_IP:
+ case EFHW_FILTER_TYPE_TX_MAC:
+ __falcon_nic_set_tx_filter_search_limits_needed(nic);
+ break;
+ default:
+ EFHW_ASSERT(0);
+ }
+ }
+
+ EFHW_ASSERT(filter_idx < (int) tbl_size);
+ EFHW_ASSERT(filter_idx >= 0);
+ set_filter_cache_entry(nic, spec, filter_idx);
+ write_filter_table_entry(nic, spec->type, filter_idx, q0, q1);
+
+ switch (spec->type) {
+ case EFHW_FILTER_TYPE_IP:
+ ++nic->ip_filter_tbl_used;
+ break;
+ case EFHW_FILTER_TYPE_MAC:
+ ++nic->mac_filter_tbl_used;
+ break;
+ case EFHW_FILTER_TYPE_TX_IP:
+ ++nic->tx_ip_filter_tbl_used;
+ break;
+ case EFHW_FILTER_TYPE_TX_MAC:
+ ++nic->tx_mac_filter_tbl_used;
+ break;
+ default:
+ EFHW_ASSERT(0);
+ }
+
+ *filter_idx_out = filter_idx;
+
+ EFHW_TRACE("%s: filter type %d index %d rxq %u set in %u",
+ __FUNCTION__, spec->type, filter_idx, spec->dmaq_id, k);
+
+fail1:
+ FALCON_LOCK_UNLOCK(nic);
+ return rc;
+}
+
+
+static void falcon_nic_filter_clear(struct efhw_nic *nic,
+ enum efhw_filter_type type,
+ int filter_idx)
+{
+ FALCON_LOCK_DECL;
+
+ if (filter_idx < 0)
+ return;
+
+ FALCON_LOCK_LOCK(nic);
+ if (filter_is_active(nic, type, filter_idx)) {
+ switch (type) {
+ case EFHW_FILTER_TYPE_IP:
+ if (--nic->ip_filter_tbl_used == 0) {
+ nic->tcp_full_srch.needed = 0;
+ nic->tcp_wild_srch.needed = 0;
+ nic->udp_full_srch.needed = 0;
+ nic->udp_wild_srch.needed = 0;
+ }
+ break;
+ case EFHW_FILTER_TYPE_MAC:
+ if (--nic->mac_filter_tbl_used == 0) {
+ nic->mac_full_srch.needed = 0;
+ nic->mac_wild_srch.needed = 0;
+ }
+ break;
+ case EFHW_FILTER_TYPE_TX_IP:
+ if (--nic->tx_ip_filter_tbl_used == 0) {
+ nic->tx_tcp_full_srch.needed = 0;
+ nic->tx_tcp_wild_srch.needed = 0;
+ nic->tx_udp_full_srch.needed = 0;
+ nic->tx_udp_wild_srch.needed = 0;
+ }
+ break;
+ case EFHW_FILTER_TYPE_TX_MAC:
+ if (--nic->tx_mac_filter_tbl_used == 0) {
+ nic->tx_mac_full_srch.needed = 0;
+ nic->tx_mac_wild_srch.needed = 0;
+ }
+ break;
+ default:
+ EFHW_ASSERT(0);
+ }
+ }
+ clear_filter_cache_entry(nic, type, filter_idx);
+ write_filter_table_entry(nic, type, filter_idx, 0, 0);
+ FALCON_LOCK_UNLOCK(nic);
+}
+
+
+static void filter_nic_filter_redirect(struct efhw_nic *nic, int type,
+ int filter_i, int rxq_i)
+{
+ unsigned key = 0, tbl_size = 0;
+ struct efhw_filter_depth *depth = NULL;
+ struct efhw_filter_spec *spec;
+ uint64_t q0, q1;
+
+ spec = filter_spec_cache_entry(nic, type, filter_i);
+ spec->dmaq_id = rxq_i;
+ build_filter(nic, spec, &key, &tbl_size, &depth, &q0, &q1);
+ write_filter_table_entry(nic, spec->type, filter_i, q0, q1);
+}
+
+
+int
+falcon_nic_filter_ctor(struct efhw_nic *nic)
+{
+ if (nic->devtype.variant < 'C') {
+ nic->ip_filter_tbl_size = efhw_in_fpga(nic) ? 4096 : 8192;
+ nic->mac_filter_tbl_size = 0;
+ nic->tx_ip_filter_tbl_size = 0;
+ nic->tx_mac_filter_tbl_size = 0;
+ } else {
+ nic->ip_filter_tbl_size = 8192;
+ nic->mac_filter_tbl_size = 512;
+ nic->tx_ip_filter_tbl_size = efhw_in_fpga(nic) ? 4096 : 8192;
+ nic->tx_mac_filter_tbl_size = 512;
+ }
+
+ nic->ip_filter_tbl_used = 0;
+ nic->mac_filter_tbl_used = 0;
+ nic->tx_ip_filter_tbl_used = 0;
+ nic->tx_mac_filter_tbl_used = 0;
+
+ nic->tcp_full_srch.needed = 0;
+ nic->tcp_wild_srch.needed = 0;
+ nic->udp_full_srch.needed = 0;
+ nic->udp_wild_srch.needed = 0;
+ nic->mac_full_srch.needed = 0;
+ nic->mac_wild_srch.needed = 0;
+
+ nic->tx_tcp_full_srch.needed = 0;
+ nic->tx_tcp_wild_srch.needed = 0;
+ nic->tx_udp_full_srch.needed = 0;
+ nic->tx_udp_wild_srch.needed = 0;
+ nic->tx_mac_full_srch.needed = 0;
+ nic->tx_mac_wild_srch.needed = 0;
+
+ nic->filter_in_use = vmalloc(FALCON_FILTER_TBL_NUM);
+ if (nic->filter_in_use == NULL)
+ return -ENOMEM;
+ memset(nic->filter_in_use, 0, FALCON_FILTER_TBL_NUM);
+#if FALCON_FULL_FILTER_CACHE
+ nic->filter_spec_cache = vmalloc(FALCON_FILTER_TBL_NUM
+ * EFHW_FILTER_TYPES_NUM
+ * sizeof(struct efhw_filter_spec));
+ if (nic->filter_spec_cache == NULL)
+ return -ENOMEM;
+ memset(nic->filter_spec_cache, 0, FALCON_FILTER_TBL_NUM
+ * EFHW_FILTER_TYPES_NUM
+ * sizeof(struct efhw_filter_spec));
+#endif
+
+ return 0;
+}
+
+
+static void
+falcon_nic_filter_dtor(struct efhw_nic *nic)
+{
+#if FALCON_FULL_FILTER_CACHE
+ vfree(nic->filter_spec_cache);
+ nic->filter_spec_cache = NULL;
+#endif
+ vfree(nic->filter_in_use);
+ nic->filter_in_use = NULL;
+}
+
+
+/*--------------------------------------------------------------------
+ *
+ * Compatibility with old filter API
+ *
+ *--------------------------------------------------------------------*/
+
+void
+falcon_nic_rx_filter_ctl_get(struct efhw_nic *nic, uint32_t *tcp_full,
+ uint32_t *tcp_wild,
+ uint32_t *udp_full, uint32_t *udp_wild)
+{
+ struct efhw_filter_search_limits lim;
+
+ falcon_nic_get_rx_filter_search_limits(nic, &lim, 0);
+ *tcp_full = (uint32_t)lim.tcp_full;
+ *tcp_wild = (uint32_t)lim.tcp_wild;
+ *udp_full = (uint32_t)lim.udp_full;
+ *udp_wild = (uint32_t)lim.udp_wild;
+}
+EXPORT_SYMBOL(falcon_nic_rx_filter_ctl_get);
+
+
+void
+falcon_nic_rx_filter_ctl_set(struct efhw_nic *nic, uint32_t tcp_full,
+ uint32_t tcp_wild,
+ uint32_t udp_full, uint32_t udp_wild)
+{
+ struct efhw_filter_search_limits lim;
+
+ if (nic->devtype.variant >= 'C') {
+ /* Preserve the MAC filter settings on Siena */
+ falcon_nic_get_rx_filter_search_limits(nic, &lim, 0);
+ } else {
+ lim.mac_full = 0;
+ lim.mac_wild = 0;
+ }
+ lim.tcp_full = (unsigned)tcp_full;
+ lim.tcp_wild = (unsigned)tcp_wild;
+ lim.udp_full = (unsigned)udp_full;
+ lim.udp_wild = (unsigned)udp_wild;
+ falcon_nic_set_rx_filter_search_limits(nic, &lim, 0);
+}
+EXPORT_SYMBOL(falcon_nic_rx_filter_ctl_set);
+
+
+static int
+falcon_nic_ipfilter_set(struct efhw_nic *nic, int type, int *_filter_idx,
+ int dmaq,
+ unsigned saddr_be32, unsigned sport_be16,
+ unsigned daddr_be32, unsigned dport_be16)
+{
+ struct efhw_filter_spec spec;
+
+ spec.type = EFHW_FILTER_TYPE_IP;
+ spec.dmaq_id = dmaq;
+ spec.u.ip.saddr_le32 = ntohl(saddr_be32);
+ spec.u.ip.daddr_le32 = ntohl(daddr_be32);
+ spec.u.ip.sport_le16 = ntohs((unsigned short) sport_be16);
+ spec.u.ip.dport_le16 = ntohs((unsigned short) dport_be16);
+ spec.u.ip.tcp = ((type & EFHW_IP_FILTER_TYPE_TCP_MASK) != 0);
+ spec.u.ip.full = ((type & EFHW_IP_FILTER_TYPE_FULL_MASK) != 0);
+ spec.u.ip.rss = ((type & EFHW_IP_FILTER_TYPE_RSS_B0_MASK) != 0);
+ spec.u.ip.scatter = ((type & EFHW_IP_FILTER_TYPE_NOSCAT_B0_MASK) == 0);
+ return falcon_nic_filter_set(nic, &spec, _filter_idx);
+}
+
+static void falcon_nic_ipfilter_clear(struct efhw_nic *nic, int filter_idx)
+{
+ falcon_nic_filter_clear(nic, EFHW_FILTER_TYPE_IP, filter_idx);
+}
+
+
+static void
+falcon_nic_ipfilter_redirect(struct efhw_nic *nic, int filter_i, int rxq_i)
+{
+ filter_nic_filter_redirect(nic, EFHW_FILTER_TYPE_IP, filter_i, rxq_i);
+}
+
+
+/*--------------------------------------------------------------------
+ *
+ * Abstraction Layer Hooks
+ *
+ *--------------------------------------------------------------------*/
+
+struct efhw_func_ops falcon_char_functional_units = {
+ falcon_nic_close_hardware,
+ falcon_nic_init_hardware,
+ falcon_nic_interrupt,
+ falcon_nic_interrupt_enable,
+ falcon_nic_interrupt_disable,
+ falcon_nic_set_interrupt_moderation,
+ falcon_nic_event_queue_enable,
+ falcon_nic_event_queue_disable,
+ falcon_nic_wakeup_request,
+ falcon_nic_sw_event,
+ falcon_nic_ipfilter_set,
+ falcon_nic_ipfilter_clear,
+ falcon_nic_ipfilter_redirect,
+ falcon_dmaq_tx_q_init,
+ falcon_dmaq_rx_q_init,
+ falcon_dmaq_tx_q_disable,
+ falcon_dmaq_rx_q_disable,
falcon_flush_tx_dma_channel,
falcon_flush_rx_dma_channel,
falcon_nic_buffer_table_set,
falcon_nic_buffer_table_set_n,
falcon_nic_buffer_table_clear,
falcon_nic_buffer_table_commit,
+ falcon_nic_filter_set,
+ falcon_nic_filter_clear,
};
+
+
*
* This file contains EtherFabric NIC hash algorithms implementation.
*
- * Copyright 2005-2007: Solarflare Communications Inc,
+ * Copyright 2005-2010: Solarflare Communications Inc,
* 9501 Jeronimo Road, Suite 250,
* Irvine, CA 92618, USA
*
#include <ci/driver/efab/hardware.h>
-/* this mask is per filter bank hence /2 */
-#define FILTER_MASK(n) ((n) / 2u - 1u)
-
-/*
- * Main Functions related to the Hash Table Generation
- * Author: Srinivasaih, Nataraj
- * Created: Thu May 13:32:41 PDT 2004
- * $Id: falcon_hash.c,v 1.20 2008/01/29 08:28:56 ok_sasha Exp $
- */
-/***************************************************************************
-Class Maximum number of Valid address ranges
- hosts per network
-A 16777214 1.0.0.1 through 9.255.255.254
- 11.0.0.1 through 126.255.255.254
-B 65534 128.0.0.1 through 172.15.255.254
- 172.32.0.1 through 191.255.255.254
-C 254 192.0.0.1 through 192.167.255.254
- 192.169.0.1 through 223.255.255.254
-P 16777214 10.0.0.1 through 10.255.255.254 (10/8)
- 1048574 172.16.0.1 through 172.31.255.254 (172.16/12)
- 65534 192.168.0.1 through 192.168.255.254 (192.168/16)
-
-R - 0.0.0.0 through 0.255.255.255
- (used if host will be assigned a
- valid address dynamically)
- 127.0.0.0 through 127.255.255.255
- (loopback addresses)
-
-P : Private internets only
-R : Reserved
-****************************************************************************/
-
-/* All LE parameters */
-unsigned int
-falcon_hash_get_key(unsigned int src_ip, unsigned int src_port,
- unsigned int dest_ip, unsigned int dest_port,
- int tcp, int full)
+static unsigned int
+common_get_ip_key(unsigned int src_ip, unsigned int src_port,
+ unsigned int dest_ip, unsigned int dest_port,
+ int tcp, int full, int tx, unsigned int masked_q_id)
{
- unsigned int result = 0;
- int net_type;
+ unsigned int tmp_port, result;
EFHW_ASSERT(tcp == 0 || tcp == 1);
EFHW_ASSERT(full == 0 || full == 1);
+ EFHW_ASSERT(masked_q_id < (1 << 10)); /* non-0 valid for Siena only */
+
+ /* m=masked_q_id(TX)/0(RX) u=UDP S,D=src/dest addr s,d=src/dest port
+ *
+ * Wildcard filters have src(TX)/dest(RX) addr and port = 0;
+ * and UDP wildcard filters have the src and dest port fields swapped.
+ *
+ * Addr/port fields are little-endian.
+ *
+ * 3322222222221111111111
+ * 10987654321098765432109876543210
+ *
+ * 000000000000000000000mmmmmmmmmmu ^
+ * DDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDD ^
+ * ddddddddddddddddSSSSSSSSSSSSSSSS ^
+ * SSSSSSSSSSSSSSSSssssssssssssssss
+ */
+
+ if (!tx)
+ masked_q_id = 0;
+
+ if (!full) {
+ if (tx) {
+ dest_ip = 0;
+ dest_port = 0;
+ } else {
+ src_ip = 0;
+ src_port = 0;
+ }
+ if (!tcp) {
+ tmp_port = src_port;
+ src_port = dest_port;
+ dest_port = tmp_port;
+ }
+ }
- net_type = tcp << 4 | full;
-
- /* Note that src_ip and src_port ignored if a wildcard filter */
- switch (net_type) {
- case 0x01: /* UDP Full */
- result = ((dest_ip & 0xfffffffe) | (!(dest_ip & 1))) ^
- (((dest_port << 16) & 0xFFFF0000) |
- ((src_ip >> 16) & 0x0000FFFF)) ^
- (((src_ip << 16) & 0xFFFF0000) |
- ((src_port & 0x0000FFFF)));
- EFHW_TRACE("falcon_hash_get_key: UDP Full %x", result);
- break;
- case 0x00: /* UDP Wild Card */
- result = ((dest_ip & 0xfffffffe) | (!(dest_ip & 1))) ^
- (((dest_port << 16) & 0x00000000) |
- ((src_ip >> 16) & 0x00000000)) ^
- (((src_ip << 16) & 0x00000000) |
- ((dest_port & 0x0000FFFF)));
- EFHW_TRACE("falcon_hash_get_key: UDP Wildcard %x", result);
- break;
- case 0x10: /* TCP Wild Card */
- result = (dest_ip) ^
- (((dest_port << 16) & 0xFFFF0000) |
- ((src_ip >> 16) & 0x00000000)) ^
- (((src_ip << 16) & 0x00000000) |
- ((src_port & 0x00000000)));
- EFHW_TRACE("falcon_hash_get_key: TCP Wildcard %x", result);
- break;
- case 0x11: /* TCP Full */
- result = (dest_ip) ^
- (((dest_port << 16) & 0xFFFF0000) |
- ((src_ip >> 16) & 0x0000FFFF)) ^
- (((src_ip << 16) & 0xFFFF0000) |
- ((src_port & 0x0000FFFF)));
- EFHW_TRACE("falcon_hash_get_key: TCP Full %x", result);
- break;
- default:
- EFHW_ASSERT(0);
+ result = ((masked_q_id << 1) | (!tcp)) ^
+ (dest_ip) ^
+ (((dest_port & 0xffff) << 16) | ((src_ip >> 16) & 0xffff)) ^
+ (((src_ip & 0xffff) << 16) | (src_port & 0xffff));
- }
- return (result);
+ EFHW_TRACE("%s: IP %s %s %x", __FUNCTION__, tcp ? "TCP" : "UDP",
+ full ? "Full" : "Wildcard", result);
+
+ return result;
+}
+
+
+static unsigned int
+common_get_mac_key(unsigned char *mac, unsigned int vlan, int full, int tx,
+ unsigned int masked_q_id)
+{
+ unsigned int result;
+
+ EFHW_ASSERT(mac);
+ EFHW_ASSERT(vlan <= 0xfff);
+ EFHW_ASSERT(full == 0 || full == 1);
+ EFHW_ASSERT(masked_q_id < (1 << 10)); /* non-0 valid for Siena only */
+
+ /* m=masked_q_id(TX)/0(RX) w=wildcard aa:bb:cc:dd:ee:ff=MAC v=VLAN
+ *
+ * 3322222222221111111111
+ * 10987654321098765432109876543210
+ *
+ * 000000000000000000000mmmmmmmmmmw ^
+ * 0000000000000000aaaaaaaabbbbbbbb ^
+ * ccccccccddddddddeeeeeeeeffffffff ^
+ * 00000000000000000000vvvvvvvvvvvv
+ */
+
+ if (!tx)
+ masked_q_id = 0;
+
+ if (!full)
+ vlan = 0;
+
+ result = ((masked_q_id << 1) | (!full)) ^
+ ((mac[0] << 8) | mac[1]) ^
+ ((mac[2] << 24) | (mac[3] << 16) | (mac[4] << 8) | mac[5]) ^
+ (vlan & 0xfff);
+
+ EFHW_TRACE("%s: MAC %s %x", __FUNCTION__, full ? "Full" : "Wildcard",
+ result);
+
+ return result;
}
+
+/* For Falcon and Siena: IP filter table key */
+unsigned int
+falcon_hash_get_ip_key(unsigned int src_ip, unsigned int src_port,
+ unsigned int dest_ip, unsigned int dest_port,
+ int tcp, int full)
+{
+ return common_get_ip_key(src_ip, src_port, dest_ip, dest_port, tcp,
+ full, 0, 0);
+}
+
+/* For Siena only: MAC filter table key */
+unsigned int
+falcon_hash_get_mac_key(unsigned char *mac, unsigned int vlan, int full)
+{
+ return common_get_mac_key(mac, vlan, full, 0, 0);
+}
+
+/* For Siena only: TX IP filter table key */
+unsigned int
+falcon_hash_get_tx_ip_key(unsigned int src_ip, unsigned int src_port,
+ unsigned int dest_ip, unsigned int dest_port,
+ int tcp, int full, unsigned int masked_q_id)
+{
+ return common_get_ip_key(src_ip, src_port, dest_ip, dest_port, tcp,
+ full, 1, masked_q_id);
+}
+
+/* For Siena only: TX MAC filter table key */
+unsigned int
+falcon_hash_get_tx_mac_key(unsigned char *mac, unsigned int vlan, int full,
+ unsigned int masked_q_id)
+{
+ return common_get_mac_key(mac, vlan, full, 1, masked_q_id);
+}
+
+
/* This function generates the First Hash key */
unsigned int falcon_hash_function1(unsigned int key, unsigned int nfilters)
{
}
- lfsr_reg = lfsr_reg & FILTER_MASK(nfilters);
+ lfsr_reg = lfsr_reg & (nfilters - 1);
return lfsr_reg;
}
falcon_hash_function2(unsigned int key, unsigned int nfilters)
{
return (unsigned int)(((unsigned long long)key * 2 - 1) &
- FILTER_MASK(nfilters));
+ (nfilters - 1));
}
/* This function iterates through the hash table */
falcon_hash_iterator(unsigned int hash1, unsigned int hash2,
unsigned int n_search, unsigned int nfilters)
{
- return ((hash1 + (n_search * hash2)) & FILTER_MASK(nfilters));
+ return (hash1 + (n_search * hash2)) & (nfilters - 1);
}
+
+++ /dev/null
-/****************************************************************************
- * Driver for Solarflare network controllers -
- * resource management for Xen backend, OpenOnload, etc
- * (including support for SFE4001 10GBT NIC)
- *
- * This file contains MACs (Mentor MAC & GDACT1 ) support for Falcon.
- *
- * Copyright 2005-2007: Solarflare Communications Inc,
- * 9501 Jeronimo Road, Suite 250,
- * Irvine, CA 92618, USA
- *
- * Developed and maintained by Solarflare Communications:
- * <linux-xen-drivers@solarflare.com>
- * <onload-dev@solarflare.com>
- *
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published
- * by the Free Software Foundation, incorporated herein by reference.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- ****************************************************************************
- */
-
-#include <ci/efhw/falcon.h>
-#include <ci/driver/efab/hardware.h>
-
-/********************************************************************
- * Mentor MAC
- */
-
-#define _PRE(x) GM##x
-
-/*--------------------------------------------------------------------
- *
- * Debug Support
- *
- *--------------------------------------------------------------------*/
-
-#define MENTOR_MAC_ASSERT_VALID() \
- EFHW_ASSERT(nic); \
- EFHW_ASSERT(EFHW_KVA(nic)); \
- EFHW_ASSERT(_PRE(_CFG1_REG_OFST) == _PRE(_CFG1_REG_KER_OFST)); \
- EFHW_ASSERT(_PRE(_CFG2_REG_OFST) == _PRE(_CFG2_REG_KER_OFST)); \
- EFHW_ASSERT(_PRE(_IPG_REG_OFST) == _PRE(_IPG_REG_KER_OFST)); \
- EFHW_ASSERT(_PRE(_HD_REG_OFST) == _PRE(_HD_REG_KER_OFST)); \
- EFHW_ASSERT(_PRE(_MAX_FLEN_REG_OFST) == _PRE(_MAX_FLEN_REG_KER_OFST)); \
- EFHW_ASSERT(_PRE(_TEST_REG_OFST) == _PRE(_TEST_REG_KER_OFST)); \
- EFHW_ASSERT(_PRE(_ADR1_REG_OFST) == _PRE(_ADR1_REG_KER_OFST)); \
- EFHW_ASSERT(_PRE(_ADR2_REG_OFST) == _PRE(_ADR2_REG_KER_OFST)); \
- EFHW_ASSERT(_PRE(F_CFG0_REG_OFST) == _PRE(F_CFG0_REG_KER_OFST)); \
- EFHW_ASSERT(_PRE(F_CFG1_REG_OFST) == _PRE(F_CFG1_REG_KER_OFST)); \
- EFHW_ASSERT(_PRE(F_CFG2_REG_OFST) == _PRE(F_CFG2_REG_KER_OFST)); \
- EFHW_ASSERT(_PRE(F_CFG3_REG_OFST) == _PRE(F_CFG3_REG_KER_OFST)); \
- EFHW_ASSERT(_PRE(F_CFG4_REG_OFST) == _PRE(F_CFG4_REG_KER_OFST)); \
- EFHW_ASSERT(_PRE(F_CFG5_REG_OFST) == _PRE(F_CFG5_REG_KER_OFST));
-
-/*! Get MAC current address - i.e not necessarily the one in the EEPROM */
-static inline void mentormac_get_mac_addr(struct efhw_nic *nic)
-{
- volatile char __iomem *mac_kva;
- uint val1, val2;
-
- MENTOR_MAC_ASSERT_VALID();
-
- mac_kva = GM_P0_BASE + EFHW_KVA(nic);
-
- val1 = readl(mac_kva + _PRE(_ADR1_REG_OFST));
- val2 = readl(mac_kva + _PRE(_ADR2_REG_OFST));
-
-#if 0
- nic->mac_addr[0] = (val1 & 0xff000000) >> 24;
- nic->mac_addr[1] = (val1 & 0x00ff0000) >> 16;
- nic->mac_addr[2] = (val1 & 0x0000ff00) >> 8;
- nic->mac_addr[3] = (val1 & 0x000000ff) >> 0;
- nic->mac_addr[4] = (val2 & 0xff000000) >> 24;
- nic->mac_addr[5] = (val2 & 0x00ff0000) >> 16;
-#else
- nic->mac_addr[5] = (val1 & 0xff000000) >> 24;
- nic->mac_addr[4] = (val1 & 0x00ff0000) >> 16;
- nic->mac_addr[3] = (val1 & 0x0000ff00) >> 8;
- nic->mac_addr[2] = (val1 & 0x000000ff) >> 0;
- nic->mac_addr[1] = (val2 & 0xff000000) >> 24;
- nic->mac_addr[0] = (val2 & 0x00ff0000) >> 16;
-#endif
-}
-
-
-/********************************************************************
- * GDACT10 MAC
- */
-
-/*--------------------------------------------------------------------
- *
- * Debug Support
- *
- *--------------------------------------------------------------------*/
-
-#define GDACT10_MAC_ASSERT_VALID() \
- EFHW_ASSERT(nic); \
- EFHW_ASSERT(EFHW_KVA(nic)); \
- EFHW_ASSERT(XM_GLB_CFG_REG_P0_OFST == XM_GLB_CFG_REG_KER_P0_OFST); \
- EFHW_ASSERT(XM_TX_CFG_REG_P0_OFST == XM_TX_CFG_REG_KER_P0_OFST); \
- EFHW_ASSERT(XM_RX_CFG_REG_P0_OFST == XM_RX_CFG_REG_KER_P0_OFST); \
- EFHW_ASSERT(MAC0_SPEED_LBN == MAC1_SPEED_LBN); \
- EFHW_ASSERT(MAC0_SPEED_WIDTH == MAC1_SPEED_WIDTH); \
- EFHW_ASSERT(MAC0_LINK_STATUS_LBN == MAC1_LINK_STATUS_LBN); \
- EFHW_ASSERT(MAC0_LINK_STATUS_WIDTH == MAC1_LINK_STATUS_WIDTH); \
- EFHW_ASSERT(MAC1_BCAD_ACPT_LBN == MAC0_BCAD_ACPT_LBN); \
- EFHW_ASSERT(MAC1_UC_PROM_LBN == MAC0_UC_PROM_LBN); \
- EFHW_ASSERT(MAC0_CTRL_REG_KER_OFST == MAC0_CTRL_REG_OFST); \
- EFHW_ASSERT(MAC1_CTRL_REG_KER_OFST == MAC1_CTRL_REG_OFST); \
- EFHW_ASSERT(XM_ADR_LO_REG_KER_P0_OFST == XM_ADR_LO_REG_P0_OFST); \
- EFHW_ASSERT(XM_ADR_HI_REG_KER_P0_OFST == XM_ADR_HI_REG_P0_OFST); \
- EFHW_ASSERT(XM_RX_PARAM_REG_KER_P0_OFST == XM_RX_PARAM_REG_P0_OFST);
-
-/*--------------------------------------------------------------------
- *
- * Information gathering
- *
- *--------------------------------------------------------------------*/
-
-/*! Get MAC current address - i.e not necessarily the one in the EEPROM */
-static inline void GDACT10mac_get_mac_addr(struct efhw_nic *nic)
-{
- uint val1, val2;
- volatile char __iomem *efhw_kva = EFHW_KVA(nic);
- FALCON_LOCK_DECL;
-
- GDACT10_MAC_ASSERT_VALID();
-
- EFHW_ASSERT(XM_ADR_LO_LBN == 0);
- EFHW_ASSERT(XM_ADR_LO_WIDTH == 32);
- EFHW_ASSERT(XM_ADR_HI_LBN == 0);
- EFHW_ASSERT(XM_ADR_HI_WIDTH == 16);
-
- FALCON_LOCK_LOCK(nic);
-
- val1 = readl(efhw_kva + XM_ADR_LO_REG_P0_OFST);
- val2 = readl(efhw_kva + XM_ADR_HI_REG_P0_OFST);
-
- FALCON_LOCK_UNLOCK(nic);
-
- /* The HW scores no points for consistency */
- nic->mac_addr[5] = (val2 & 0x0000ff00) >> 8;
- nic->mac_addr[4] = (val2 & 0x000000ff) >> 0;
- nic->mac_addr[3] = (val1 & 0xff000000) >> 24;
- nic->mac_addr[2] = (val1 & 0x00ff0000) >> 16;
- nic->mac_addr[1] = (val1 & 0x0000ff00) >> 8;
- nic->mac_addr[0] = (val1 & 0x000000ff) >> 0;
-}
-
-
-/********************************************************************
- * Call one or another function
- */
-
-void falcon_get_mac_addr(struct efhw_nic *nic)
-{
- if (nic->flags & NIC_FLAG_10G)
- GDACT10mac_get_mac_addr(nic);
- else
- mentormac_get_mac_addr(nic);
-}
*
* This file contains filters support.
*
- * Copyright 2005-2007: Solarflare Communications Inc,
+ * Copyright 2005-2010: Solarflare Communications Inc,
* 9501 Jeronimo Road, Suite 250,
* Irvine, CA 92618, USA
*
#include <ci/efrm/private.h>
#include <ci/efrm/filter.h>
#include <ci/efrm/buffer_table.h>
+#include <ci/efrm/efrm_client.h>
+#include "efrm_internal.h"
+
struct filter_resource_manager {
struct efrm_resource_manager rm;
static struct filter_resource_manager *efrm_filter_manager;
+
void efrm_filter_resource_free(struct filter_resource *frs)
{
- struct efhw_nic *nic;
- int nic_i;
+ struct efhw_nic *nic = frs->rs.rs_client->nic;
int id;
EFRM_RESOURCE_ASSERT_VALID(&frs->rs, 1);
EFRM_TRACE("%s: " EFRM_RESOURCE_FMT, __FUNCTION__,
EFRM_RESOURCE_PRI_ARG(frs->rs.rs_handle));
- /* if we have a PT endpoint */
- if (NULL != frs->pt) {
- /* Detach the filter */
- EFRM_FOR_EACH_NIC_IN_SET(&frs->nic_set, nic_i, nic)
- efhw_nic_ipfilter_detach(nic, frs->filter_idx);
-
- /* Release our ref to the PT resource. */
- EFRM_TRACE("%s: releasing PT resource reference",
- __FUNCTION__);
- efrm_vi_resource_release(frs->pt);
- }
-
- /* Disable the filter. */
- EFRM_FOR_EACH_NIC_IN_SET(&frs->nic_set, nic_i, nic)
- efhw_nic_ipfilter_clear(nic, frs->filter_idx);
+ efhw_nic_ipfilter_clear(nic, frs->filter_idx);
+ frs->filter_idx = -1;
+ efrm_vi_resource_release(frs->pt);
/* Free this filter. */
id = EFRM_RESOURCE_INSTANCE(frs->rs.rs_handle);
(unsigned char *)&id, sizeof(id)),
sizeof(id));
+ efrm_client_put(frs->rs.rs_client);
EFRM_DO_DEBUG(memset(frs, 0, sizeof(*frs)));
kfree(frs);
}
EXPORT_SYMBOL(efrm_filter_resource_free);
+
+void efrm_filter_resource_release(struct filter_resource *frs)
+{
+ if (__efrm_resource_release(&frs->rs))
+ efrm_filter_resource_free(frs);
+}
+EXPORT_SYMBOL(efrm_filter_resource_release);
+
+
static void filter_rm_dtor(struct efrm_resource_manager *rm)
{
- EFRM_TRACE("filter_rm_dtor");
+ EFRM_TRACE("%s:", __FUNCTION__);
EFRM_RESOURCE_MANAGER_ASSERT_VALID(&efrm_filter_manager->rm);
EFRM_ASSERT(&efrm_filter_manager->rm == rm);
kfifo_vfree(efrm_filter_manager->free_ids);
- EFRM_TRACE("filter_rm_dtor: done");
+ EFRM_TRACE("%s: done", __FUNCTION__);
}
/**********************************************************************/
rc = efrm_resource_manager_ctor(&efrm_filter_manager->rm,
filter_rm_dtor, "FILTER",
- EFRM_RESOURCE_FILTER, 0);
+ EFRM_RESOURCE_FILTER);
if (rc < 0)
goto fail1;
}
-/*--------------------------------------------------------------------
- *!
- * Called to set/change the PT endpoint of a filter
- *
- * Example of use is TCP helper when it finds a wildcard IP filter
- * needs to change which application it delivers traffic to
- *
- * \param frs filter resource
- * \param pt_handle handle of new PT endpoint
- *
- * \return standard error codes
- *
- *--------------------------------------------------------------------*/
-int
-efrm_filter_resource_set_ptresource(struct filter_resource *frs,
- struct vi_resource *ptrs)
-{
- int rc, pti, nic_i;
- struct efhw_nic *nic;
-
- EFRM_ASSERT(frs);
- /* if filter is attached to a valid PT endpoint */
- if (NULL != frs->pt) {
+int efrm_filter_resource_clear(struct filter_resource *frs)
+{
+ struct efhw_nic *nic = frs->rs.rs_client->nic;
- EFRM_TRACE("%s: detaching PT resource " EFRM_RESOURCE_FMT
- " from filter ",
- __FUNCTION__,
- EFRM_RESOURCE_PRI_ARG(frs->rs.rs_handle));
- /* Detach the filter */
- EFRM_FOR_EACH_NIC_IN_SET(&frs->nic_set, nic_i, nic)
- efhw_nic_ipfilter_detach(nic, frs->filter_idx);
+ efhw_nic_ipfilter_clear(nic, frs->filter_idx);
+ frs->filter_idx = -1;
+ return 0;
+}
+EXPORT_SYMBOL(efrm_filter_resource_clear);
- /* release reference */
- efrm_vi_resource_release(frs->pt);
- frs->pt = NULL;
- }
- if (ptrs != NULL) {
- /* get PT endpoint index */
- EFRM_RESOURCE_ASSERT_VALID(&ptrs->rs, 0);
- EFRM_ASSERT(EFRM_RESOURCE_TYPE(ptrs->rs.rs_handle) ==
- EFRM_RESOURCE_VI);
- pti = EFRM_RESOURCE_INSTANCE(ptrs->rs.rs_handle);
- if (pti == 0) {
- EFRM_ERR("%s: cannot filter for channel 0",
- __FUNCTION__);
- rc = -EINVAL;
- goto fail2;
- }
- frs->pt = ptrs;
- EFRM_TRACE("%s: attaching PT resource " EFRM_RESOURCE_FMT
- " to filter",
- __FUNCTION__,
- EFRM_RESOURCE_PRI_ARG(frs->pt->rs.rs_handle));
- EFRM_FOR_EACH_NIC_IN_SET(&frs->nic_set, nic_i, nic)
- efhw_nic_ipfilter_attach(nic, frs->filter_idx, pti);
- efrm_vi_resource_ref(frs->pt);
+int
+efrm_filter_resource_ip_set(struct filter_resource *frs, int protocol,
+ unsigned saddr_be32, int sport_be16,
+ unsigned daddr_be32, int dport_be16)
+{
+ int type;
+
+ switch (protocol) {
+ case IPPROTO_TCP:
+ if (saddr_be32)
+ type = EFHW_IP_FILTER_TYPE_TCP_FULL;
+ else
+ type = EFHW_IP_FILTER_TYPE_TCP_WILDCARD;
+ break;
+ case IPPROTO_UDP:
+ if (saddr_be32)
+ type = EFHW_IP_FILTER_TYPE_UDP_FULL;
+ else
+ type = EFHW_IP_FILTER_TYPE_UDP_WILDCARD;
+ break;
+ default:
+ return -EINVAL;
}
- return 0;
-fail2:
- efrm_vi_resource_release(frs->pt);
- return rc;
+ return efrm_filter_resource_set(frs, type, saddr_be32, sport_be16,
+ daddr_be32, dport_be16);
}
-EXPORT_SYMBOL(efrm_filter_resource_set_ptresource);
+EXPORT_SYMBOL(efrm_filter_resource_ip_set);
-int efrm_filter_resource_clear(struct filter_resource *frs)
+
+int
+efrm_filter_resource_set(struct filter_resource *frs, int type,
+ unsigned saddr, int sport,
+ unsigned daddr, int dport)
{
- struct efhw_nic *nic;
- int nic_i;
+ struct efhw_nic *nic = frs->rs.rs_client->nic;
+ int vi_instance;
EFRM_ASSERT(frs);
- EFRM_FOR_EACH_NIC_IN_SET(&frs->nic_set, nic_i, nic)
- efhw_nic_ipfilter_clear(nic, frs->filter_idx);
- return 0;
-}
-EXPORT_SYMBOL(efrm_filter_resource_clear);
+ if (efrm_nic_tablep->a_nic->devtype.variant >= 'B' &&
+ (frs->pt->flags & EFHW_VI_JUMBO_EN) == 0)
+ type |= EFHW_IP_FILTER_TYPE_NOSCAT_B0_MASK;
+ vi_instance = EFRM_RESOURCE_INSTANCE(frs->pt->rs.rs_handle);
-int
-__efrm_filter_resource_set(struct filter_resource *frs, int type,
- unsigned saddr, uint16_t sport,
- unsigned daddr, uint16_t dport)
-{
- struct efhw_nic *nic;
- int nic_i, rc = 0;
- unsigned instance = EFRM_RESOURCE_INSTANCE(frs->pt->rs.rs_handle);
+ return efhw_nic_ipfilter_set(nic, type, &frs->filter_idx,
+ vi_instance, saddr, sport, daddr, dport);
+}
+EXPORT_SYMBOL(efrm_filter_resource_set);
- EFRM_ASSERT(frs);
- EFRM_ASSERT(frs->pt);
- if (efrm_nic_tablep->a_nic->devtype.variant >= 'B') {
- /* Scatter setting must match the setting for
- * the corresponding RX queue */
- if (!(frs->pt->flags & EFHW_VI_JUMBO_EN))
- type |= EFHW_IP_FILTER_TYPE_NOSCAT_B0_MASK;
- }
+void
+efrm_filter_resource_redirect(struct filter_resource *frs,
+ struct vi_resource *vi)
+{
+ struct efhw_nic *nic = frs->rs.rs_client->nic;
+ int vi_instance;
- EFRM_FOR_EACH_NIC_IN_SET(&frs->nic_set, nic_i, nic)
- if (rc >= 0)
- rc = efhw_nic_ipfilter_set(nic, type, &frs->filter_idx,
- instance,
- saddr, sport, daddr, dport);
+ EFRM_ASSERT(frs != NULL);
+ EFRM_ASSERT(vi != NULL);
- return rc;
+ vi_instance = EFRM_RESOURCE_INSTANCE(vi->rs.rs_handle);
+ if( frs->filter_idx >= 0 )
+ efhw_nic_ipfilter_redirect(nic, frs->filter_idx, vi_instance);
+ efrm_vi_resource_release(frs->pt);
+ frs->pt = vi;
+ efrm_resource_ref(&frs->pt->rs);
}
-EXPORT_SYMBOL(__efrm_filter_resource_set);;
+EXPORT_SYMBOL(efrm_filter_resource_redirect);
+
int
efrm_filter_resource_alloc(struct vi_resource *vi_parent,
struct filter_resource **frs_out)
{
- struct efhw_nic *nic;
- int nic_i, rc, instance;
struct filter_resource *frs;
+ int rc, instance;
EFRM_ASSERT(frs_out);
EFRM_ASSERT(efrm_filter_manager);
EFRM_RESOURCE_MANAGER_ASSERT_VALID(&efrm_filter_manager->rm);
- EFRM_ASSERT(vi_parent == NULL ||
- EFRM_RESOURCE_TYPE(vi_parent->rs.rs_handle) ==
+ EFRM_ASSERT(vi_parent != NULL);
+ EFRM_ASSERT(EFRM_RESOURCE_TYPE(vi_parent->rs.rs_handle) ==
EFRM_RESOURCE_VI);
- /* Allocate resource data structure. */
- frs = kmalloc(sizeof(struct filter_resource), GFP_KERNEL);
+ /* Allocate resource data structure. This is called in atomic
+ * context by the onload driver.
+ */
+ frs = kmalloc(sizeof(struct filter_resource), GFP_ATOMIC);
if (!frs)
return -ENOMEM;
- efrm_nic_set_clear(&frs->nic_set);
/* Allocate an instance. */
rc = kfifo_get(efrm_filter_manager->free_ids,
/* Initialise the resource DS. */
efrm_resource_init(&frs->rs, EFRM_RESOURCE_FILTER, instance);
frs->pt = vi_parent;
- if (frs->pt)
- efrm_vi_resource_ref(frs->pt);
+ efrm_resource_ref(&frs->pt->rs);
frs->filter_idx = -1;
- EFRM_FOR_EACH_NIC(nic_i, nic)
- efrm_nic_set_write(&frs->nic_set, nic_i, true);
- EFRM_TRACE("%s: " EFRM_RESOURCE_FMT " Q %d idx %x",
- __FUNCTION__,
+ EFRM_TRACE("%s: " EFRM_RESOURCE_FMT " VI %d", __FUNCTION__,
EFRM_RESOURCE_PRI_ARG(frs->rs.rs_handle),
- vi_parent == NULL ? -1 :
- EFRM_RESOURCE_INSTANCE(vi_parent->rs.rs_handle),
- frs->filter_idx);
-
- /* Put it into the resource manager's table. */
- rc = efrm_resource_manager_insert(&frs->rs);
- if (rc != 0) {
- if (atomic_dec_and_test(&frs->rs.rs_ref_count))
- efrm_filter_resource_free(frs);
- return rc;
- }
+ EFRM_RESOURCE_INSTANCE(vi_parent->rs.rs_handle));
+ efrm_client_add_resource(vi_parent->rs.rs_client, &frs->rs);
*frs_out = frs;
return 0;
return rc;
}
EXPORT_SYMBOL(efrm_filter_resource_alloc);
+
+
+int efrm_filter_resource_instance(struct filter_resource *frs)
+{
+ return EFRM_RESOURCE_INSTANCE(frs->rs.rs_handle);
+}
+EXPORT_SYMBOL(efrm_filter_resource_instance);
+
+
+struct efrm_resource *
+efrm_filter_resource_to_resource(struct filter_resource *frs)
+{
+ return &frs->rs;
+}
+EXPORT_SYMBOL(efrm_filter_resource_to_resource);
+
+
+struct filter_resource *
+efrm_filter_resource_from_resource(struct efrm_resource *rs)
+{
+ return filter_resource(rs);
+}
+EXPORT_SYMBOL(efrm_filter_resource_from_resource);
*
* This file contains non-contiguous I/O buffers support.
*
- * Copyright 2005-2007: Solarflare Communications Inc,
+ * Copyright 2005-2010: Solarflare Communications Inc,
* 9501 Jeronimo Road, Suite 250,
* Irvine, CA 92618, USA
*
#include <ci/efrm/iobufset.h>
#include <ci/efrm/vi_resource_manager.h>
#include <ci/efrm/buffer_table.h>
+#include <ci/efrm/efrm_client.h>
+#include "efrm_internal.h"
+
#define EFRM_IOBUFSET_MAX_NUM_INSTANCES 0x00010000
#define iobsrs(rs1) iobufset_resource(rs1)
/* Returns size of iobufset resource data structure. */
-static inline size_t iobsrs_size(int no_pages)
+static inline size_t iobsrs_size(int n_pages)
{
return offsetof(struct iobufset_resource, bufs) +
- no_pages * sizeof(struct efhw_iopage);
+ n_pages * sizeof(struct efhw_iopage);
}
void efrm_iobufset_resource_free(struct iobufset_resource *rs)
{
- unsigned int no_pages;
unsigned int i;
int id;
EFRM_RESOURCE_ASSERT_VALID(&rs->rs, 1);
- no_pages = rs->n_bufs;
- if (rs->buf_tbl_alloc.base != (unsigned)-1)
+ if (!rs->linked && rs->buf_tbl_alloc.base != (unsigned) -1)
efrm_buffer_table_free(&rs->buf_tbl_alloc);
/* see comment on call to efhw_iopage_alloc in the alloc routine above
for discussion on use of efrm_nic_tablep->a_nic here */
EFRM_ASSERT(efrm_nic_tablep->a_nic);
- if (rs->order == 0) {
+ if (rs->linked) {
+ /* Nothing to do. */
+ } else if (rs->chunk_order == 0) {
for (i = 0; i < rs->n_bufs; ++i)
efhw_iopage_free(efrm_nic_tablep->a_nic, &rs->bufs[i]);
} else {
i += rs->pages_per_contiguous_chunk) {
struct efhw_iopages iopages;
efhw_iopages_init_from_iopage(&iopages, &rs->bufs[i],
- rs->order);
+ rs->chunk_order);
efhw_iopages_free(efrm_nic_tablep->a_nic, &iopages);
}
}
(unsigned char *)&id, sizeof(id)), sizeof(id));
efrm_vi_resource_release(rs->evq);
+ if (rs->linked)
+ efrm_iobufset_resource_release(rs->linked);
- EFRM_DO_DEBUG(memset(rs, 0, sizeof(*rs)));
- if (iobsrs_size(no_pages) < PAGE_SIZE) {
+ efrm_client_put(rs->rs.rs_client);
+ if (iobsrs_size(rs->n_bufs) < PAGE_SIZE) {
+ EFRM_DO_DEBUG(memset(rs, 0, sizeof(*rs)));
kfree(rs);
} else {
+ EFRM_DO_DEBUG(memset(rs, 0, sizeof(*rs)));
vfree(rs);
}
}
EXPORT_SYMBOL(efrm_iobufset_resource_free);
+
+void efrm_iobufset_resource_release(struct iobufset_resource *iobrs)
+{
+ if (__efrm_resource_release(&iobrs->rs))
+ efrm_iobufset_resource_free(iobrs);
+}
+EXPORT_SYMBOL(efrm_iobufset_resource_release);
+
+
+
int
efrm_iobufset_resource_alloc(int32_t n_pages,
int32_t pages_per_contiguous_chunk,
struct vi_resource *vi_evq,
+ struct iobufset_resource *linked,
bool phys_addr_mode,
- uint32_t faultonaccess,
struct iobufset_resource **iobrs_out)
{
struct iobufset_resource *iobrs;
EFRM_RESOURCE_VI);
EFRM_ASSERT(efrm_nic_tablep->a_nic);
+ if (linked) {
+ /* This resource will share properties and memory with
+ * another. Only difference is that we'll program it into
+ * the buffer table of another nic.
+ */
+ n_pages = linked->n_bufs;
+ pages_per_contiguous_chunk = linked->pages_per_contiguous_chunk;
+ phys_addr_mode = linked->buf_tbl_alloc.base == (unsigned) -1;
+ }
+
/* allocate the resource data structure. */
object_size = iobsrs_size(n_pages);
if (object_size < PAGE_SIZE) {
#endif
iobrs = (struct iobufset_resource *) vmalloc(object_size);
}
- if (iobrs == 0) {
+ if (iobrs == NULL) {
+ EFRM_WARN("%s: failed to allocate container", __FUNCTION__);
rc = -ENOMEM;
goto fail1;
}
rc = kfifo_get(efrm_iobufset_manager->free_ids,
(unsigned char *)&instance, sizeof(instance));
if (rc != sizeof(instance)) {
- EFRM_TRACE("%s: out of instances", __FUNCTION__);
+ EFRM_WARN("%s: out of instances", __FUNCTION__);
EFRM_ASSERT(rc == 0);
rc = -EBUSY;
goto fail3;
efrm_resource_init(&iobrs->rs, EFRM_RESOURCE_IOBUFSET, instance);
iobrs->evq = vi_evq;
- efrm_vi_resource_ref(iobrs->evq);
-
+ iobrs->linked = linked;
iobrs->n_bufs = n_pages;
iobrs->pages_per_contiguous_chunk = pages_per_contiguous_chunk;
- iobrs->order = fls(iobrs->pages_per_contiguous_chunk - 1);
- iobrs->faultonaccess = faultonaccess;
+ iobrs->chunk_order = fls(iobrs->pages_per_contiguous_chunk - 1);
+ iobrs->buf_tbl_alloc.base = (unsigned) -1;
EFRM_TRACE("%s: " EFRM_RESOURCE_FMT " %u pages", __FUNCTION__,
EFRM_RESOURCE_PRI_ARG(iobrs->rs.rs_handle), iobrs->n_bufs);
/* Allocate the iobuffers. */
- if (iobrs->order == 0) {
- /* make sure iobufs are in a known state in case we don't
- * finish our allocation */
- for (i = 0; i < iobrs->n_bufs; ++i)
- memset(&iobrs->bufs[i], 0, sizeof(iobrs->bufs[i]));
-
+ if (linked) {
+ memcpy(iobrs->bufs, linked->bufs,
+ iobrs->n_bufs * sizeof(iobrs->bufs[0]));
+ } else if (iobrs->chunk_order == 0) {
+ memset(iobrs->bufs, 0, iobrs->n_bufs * sizeof(iobrs->bufs[0]));
for (i = 0; i < iobrs->n_bufs; ++i) {
/* due to bug2426 we have to specifiy a NIC when
* allocating a DMAable page, which is a bit messy.
rc = efhw_iopage_alloc(efrm_nic_tablep->a_nic,
&iobrs->bufs[i]);
if (rc < 0) {
- EFRM_ERR("%s: failed (rc %d) to allocate "
- "page (i=%u)", __FUNCTION__, rc, i);
+ EFRM_WARN("%s: failed (rc %d) to allocate "
+ "page (i=%u)", __FUNCTION__, rc, i);
goto fail4;
}
}
struct efhw_iopages iopages;
unsigned j;
- /* make sure iobufs are in a known state in case we don't
- * finish our allocation */
- for (i = 0; i < iobrs->n_bufs; ++i)
- memset(&iobrs->bufs[i], 0, sizeof(iobrs->bufs[i]));
-
+ memset(iobrs->bufs, 0, iobrs->n_bufs * sizeof(iobrs->bufs[0]));
for (i = 0; i < iobrs->n_bufs;
i += iobrs->pages_per_contiguous_chunk) {
rc = efhw_iopages_alloc(efrm_nic_tablep->a_nic,
- &iopages, iobrs->order);
+ &iopages, iobrs->chunk_order);
if (rc < 0) {
- EFRM_ERR("%s: failed (rc %d) to allocate "
- "pages (i=%u order %d)",
- __FUNCTION__, rc, i, iobrs->order);
+ EFRM_WARN("%s: failed (rc %d) to allocate "
+ "pages (i=%u order %d)",
+ __FUNCTION__, rc, i,
+ iobrs->chunk_order);
goto fail4;
}
for (j = 0; j < iobrs->pages_per_contiguous_chunk;
}
}
- iobrs->buf_tbl_alloc.base = (unsigned)-1;
-
if (!phys_addr_mode) {
- unsigned instance = EFAB_VI_RESOURCE_INSTANCE(iobrs->evq);
- /* Allocate space in the NIC's buffer table. */
- rc = efrm_buffer_table_alloc(fls(iobrs->n_bufs - 1),
- &iobrs->buf_tbl_alloc);
- if (rc < 0) {
- EFRM_ERR("%s: failed (%d) to alloc %d buffer table "
- "entries", __FUNCTION__, rc, iobrs->n_bufs);
- goto fail5;
+ unsigned owner_id = EFAB_VI_RESOURCE_INSTANCE(iobrs->evq);
+
+ if (!linked) {
+ /* Allocate space in the NIC's buffer table. */
+ rc = efrm_buffer_table_alloc(fls(iobrs->n_bufs - 1),
+ &iobrs->buf_tbl_alloc);
+ if (rc < 0) {
+ EFRM_WARN("%s: failed (%d) to alloc %d buffer "
+ "table entries", __FUNCTION__, rc,
+ iobrs->n_bufs);
+ goto fail5;
+ }
+ EFRM_ASSERT(((unsigned)1 << iobrs->buf_tbl_alloc.order)
+ >= (unsigned) iobrs->n_bufs);
+ } else {
+ iobrs->buf_tbl_alloc = linked->buf_tbl_alloc;
}
- EFRM_ASSERT(((unsigned)1 << iobrs->buf_tbl_alloc.order) >=
- (unsigned)iobrs->n_bufs);
/* Initialise the buffer table entries. */
for (i = 0; i < iobrs->n_bufs; ++i) {
/*\ ?? \TODO burst them! */
- efrm_buffer_table_set(&iobrs->buf_tbl_alloc, i,
+ efrm_buffer_table_set(&iobrs->buf_tbl_alloc,
+ vi_evq->rs.rs_client->nic,
+ i,
efhw_iopage_dma_addr(&iobrs->
- bufs[i]),
- instance);
+ bufs[i]),
+ owner_id);
}
efrm_buffer_table_commit();
}
EFRM_RESOURCE_PRI_ARG(iobrs->rs.rs_handle),
iobrs->n_bufs, EFHW_BUFFER_ADDR(iobrs->buf_tbl_alloc.base,
0));
-
- /* Put it into the resource manager's table. */
- rc = efrm_resource_manager_insert(&iobrs->rs);
- if (rc != 0) {
- if (atomic_dec_and_test(&iobrs->rs.rs_ref_count))
- efrm_iobufset_resource_free(iobrs);
- return rc;
- }
-
+ efrm_resource_ref(&iobrs->evq->rs);
+ if (linked != NULL)
+ efrm_resource_ref(&linked->rs);
+ efrm_client_add_resource(vi_evq->rs.rs_client, &iobrs->rs);
*iobrs_out = iobrs;
return 0;
fail4:
/* see comment on call to efhw_iopage_alloc above for a discussion
* on use of efrm_nic_tablep->a_nic here */
- if (iobrs->order == 0) {
+ if (linked) {
+ /* Nothing to do. */
+ } else if (iobrs->chunk_order == 0) {
while (i--) {
struct efhw_iopage *page = &iobrs->bufs[i];
efhw_iopage_free(efrm_nic_tablep->a_nic, page);
* efhw_iopages_init_from_iopage() assume this */
efhw_iopages_init_from_iopage(&iopages,
&iobrs->bufs[j],
- iobrs->order);
+ iobrs->chunk_order);
efhw_iopages_free(efrm_nic_tablep->a_nic, &iopages);
}
}
- efrm_vi_resource_release(iobrs->evq);
fail3:
- if (object_size < PAGE_SIZE) {
+ if (object_size < PAGE_SIZE)
kfree(iobrs);
- } else {
+ else
vfree(iobrs);
- }
fail1:
return rc;
}
max = efrm_buffer_table_size() / MIN_PAGES_PER_IOBUFSET;
max = min_t(int, max, EFRM_IOBUFSET_MAX_NUM_INSTANCES);
+ /* HACK: There currently exists an option to allocate buffers that
+ * are not programmed into the buffer table, so the max number is
+ * not limited by the buffer table size. I'm hoping this usage
+ * will go away eventually.
+ */
+ max = 32768;
+
rc = efrm_kfifo_id_ctor(&efrm_iobufset_manager->free_ids,
0, max, &efrm_iobufset_manager->rm.rm_lock);
if (rc != 0)
rc = efrm_resource_manager_ctor(&efrm_iobufset_manager->rm,
iobufset_rm_dtor, "IOBUFSET",
- EFRM_RESOURCE_IOBUFSET, max);
+ EFRM_RESOURCE_IOBUFSET);
if (rc < 0)
goto fail2;
* This file provides Linux-specific implementation for iopage API used
* from efhw library.
*
- * Copyright 2005-2007: Solarflare Communications Inc,
+ * Copyright 2005-2010: Solarflare Communications Inc,
* 9501 Jeronimo Road, Suite 250,
* Irvine, CA 92618, USA
*
int efhw_iopage_alloc(struct efhw_nic *nic, struct efhw_iopage *p)
{
struct linux_efhw_nic *lnic = linux_efhw_nic(nic);
- dma_addr_t handle;
void *kva;
- kva = efrm_pci_alloc_consistent(lnic->pci_dev, PAGE_SIZE,
- &handle);
+ kva = efrm_dma_alloc_coherent(&lnic->pci_dev->dev, PAGE_SIZE,
+ &p->dma_addr, GFP_ATOMIC);
if (kva == 0)
return -ENOMEM;
- EFHW_ASSERT((handle & ~PAGE_MASK) == 0);
+ EFHW_ASSERT((p->dma_addr & ~PAGE_MASK) == 0);
memset((void *)kva, 0, PAGE_SIZE);
efhw_page_init_from_va(&p->p, kva);
-
- p->dma_addr = handle;
-
return 0;
}
struct linux_efhw_nic *lnic = linux_efhw_nic(nic);
EFHW_ASSERT(efhw_page_is_valid(&p->p));
- efrm_pci_free_consistent(lnic->pci_dev, PAGE_SIZE,
- efhw_iopage_ptr(p), p->dma_addr);
+ efrm_dma_free_coherent(&lnic->pci_dev->dev, PAGE_SIZE,
+ efhw_iopage_ptr(p), p->dma_addr);
}
int
* This file provides compatibility layer for various Linux kernel versions
* (starting from 2.6.9 RHEL kernel).
*
- * Copyright 2005-2007: Solarflare Communications Inc,
+ * Copyright 2005-2010: Solarflare Communications Inc,
* 9501 Jeronimo Road, Suite 250,
* Irvine, CA 92618, USA
*
* Reference counting should then work on the whole allocation but
* is broken by bug/feature D (above) on old kernels.
*
- * EFRM_MMAP_USE_SPLIT
+ * EFRM_MMAP_USE_SPLIT
* On old kernels, we convert the multi-page allocation to many
* single page allocations. This involves incrementing the
/* Should we split each multi-page allocation into single page
* allocations? */
#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,16)
-#define EFRM_MMAP_USE_SPLIT 1
+# define EFRM_MMAP_USE_SPLIT 1
#else
-#define EFRM_MMAP_USE_SPLIT 0
+# define EFRM_MMAP_USE_SPLIT 0
#endif
+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,26)
/* NB. 2.6.17 has renamed SetPageCompound to __SetPageCompound and
* ClearPageCompound to __ClearPageCompound. */
-#if ( ( !defined(PageCompound) ) || \
- ( !defined(PG_compound) ) || \
- ( !defined(SetPageCompound) && !defined(__SetPageCompound) ) || \
- ( !defined(ClearPageCompound) && !defined(__ClearPageCompound) ) )
-#error Mismatch of defined page-flags.
+# if ((!defined(PageCompound)) || \
+ (!defined(PG_compound)) || \
+ (!defined(SetPageCompound) && !defined(__SetPageCompound)) || \
+ (!defined(ClearPageCompound) && !defined(__ClearPageCompound)))
+# error Mismatch of defined page-flags.
+# endif
#endif
/****************************************************************************
/* Check the page count and PG_compound bit. */
#ifndef NDEBUG
- EFRM_ASSERT(PageCompound(start_pg) == 1);
+ EFRM_ASSERT(PageCompound(start_pg));
EFRM_ASSERT(page_count(start_pg) == 1);
#endif
* This file provides compatibility layer for various Linux kernel versions
* (starting from 2.6.9 RHEL kernel).
*
- * Copyright 2005-2007: Solarflare Communications Inc,
+ * Copyright 2005-2010: Solarflare Communications Inc,
* 9501 Jeronimo Road, Suite 250,
* Irvine, CA 92618, USA
*
#include <linux/version.h>
#include <linux/moduleparam.h>
#include <linux/sched.h>
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,16)
+#include <linux/io.h>
+#else
#include <asm/io.h>
+#endif
#include <linux/pci.h>
/********* wait_for_completion_timeout() ********************/
extern void efrm_dma_free_coherent(struct device *dev, size_t size,
void *ptr, dma_addr_t dma_addr);
-static inline void *efrm_pci_alloc_consistent(struct pci_dev *hwdev,
- size_t size,
- dma_addr_t *dma_addr)
-{
- return efrm_dma_alloc_coherent(&hwdev->dev, size, dma_addr,
- GFP_ATOMIC);
-}
-
-static inline void efrm_pci_free_consistent(struct pci_dev *hwdev, size_t size,
- void *ptr, dma_addr_t dma_addr)
-{
- efrm_dma_free_coherent(&hwdev->dev, size, ptr, dma_addr);
-}
-
#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,8))
static inline void efrm_pci_disable_msi(struct pci_dev *dev) {}
#define pci_disable_msi efrm_pci_disable_msi
#endif
+#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,19))
+enum {
+ false = 0,
+ true = 1
+};
+
+typedef _Bool bool;
+#endif /* LINUX_VERSION_CODE < 2.6.19 */
+
#endif /* DRIVER_LINUX_RESOURCE_KERNEL_COMPAT_H */
+
*
* This file contains /proc/driver/sfc_resource/ implementation.
*
- * Copyright 2005-2007: Solarflare Communications Inc,
+ * Copyright 2005-2010: Solarflare Communications Inc,
* 9501 Jeronimo Road, Suite 250,
* Irvine, CA 92618, USA
*
*/
#include <ci/efrm/debug.h>
-#include <ci/efrm/nic_table.h>
#include <ci/efrm/driver_private.h>
#include <linux/proc_fs.h>
int efrm_install_proc_entries(void)
{
/* create the top-level directory for etherfabric specific stuff */
- efrm_proc_root = proc_mkdir("sfc_resource", proc_root_driver);
+ efrm_proc_root = proc_mkdir("driver/sfc_resource", NULL);
if (!efrm_proc_root)
return -ENOMEM;
- EFRM_ASSERT(efrm_proc_root);
if (create_proc_read_entry("resources", 0, efrm_proc_root,
efrm_resource_read_proc, 0) == NULL) {
EFRM_WARN("%s: Unable to create /proc/drivers/sfc_resource/"
- "resources", __FUNCTION__);
+ "resources", __func__);
}
return 0;
}
{
EFRM_ASSERT(efrm_proc_root);
remove_proc_entry("resources", efrm_proc_root);
- remove_proc_entry("sfc_resource", proc_root_driver);
+ remove_proc_entry(efrm_proc_root->name, efrm_proc_root->parent);
efrm_proc_root = NULL;
}
* Most part of linux/kfifo.h is incorporated into
* ci/efrm/sysdep_linux.h.
*/
-#include <ci/efrm/sysdep_linux.h>
-#ifdef HAS_NO_KFIFO
+#include <ci/efrm/sysdep.h>
+#ifdef EFX_NEED_KFIFO
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/slab.h>
#include <linux/err.h>
-/*#include <linux/kfifo.h>*/
+
/**
* kfifo_init - allocates a new FIFO using a preallocated buffer
* &struct kfifo with kfree().
*/
struct kfifo *kfifo_init(unsigned char *buffer, unsigned int size,
- gfp_t gfp_mask, spinlock_t * lock)
+ gfp_t gfp_mask, spinlock_t *lock)
{
struct kfifo *fifo;
return fifo;
}
-
EXPORT_SYMBOL(kfifo_init);
/**
*
* The size will be rounded-up to a power of 2.
*/
-struct kfifo *kfifo_alloc(unsigned int size, gfp_t gfp_mask, spinlock_t * lock)
+struct kfifo *kfifo_alloc(unsigned int size, gfp_t gfp_mask, spinlock_t *lock)
{
unsigned char *buffer;
struct kfifo *ret;
return ret;
}
-
EXPORT_SYMBOL(kfifo_alloc);
/**
kfree(fifo->buffer);
kfree(fifo);
}
-
EXPORT_SYMBOL(kfifo_free);
/**
return len;
}
-
EXPORT_SYMBOL(__kfifo_put);
/**
return len;
}
-
EXPORT_SYMBOL(__kfifo_get);
+
#endif
*
* This file contains Linux-specific API internal for the resource driver.
*
- * Copyright 2005-2007: Solarflare Communications Inc,
+ * Copyright 2005-2010: Solarflare Communications Inc,
* 9501 Jeronimo Road, Suite 250,
* Irvine, CA 92618, USA
*
#include <ci/efrm/driver_private.h>
#include <ci/driver/efab/hardware.h>
-
-/*! Linux specific EtherFabric initialisation */
-extern int
-linux_efrm_nic_ctor(struct linux_efhw_nic *, struct pci_dev *,
- spinlock_t *reg_lock,
- unsigned nic_flags, unsigned nic_options);
-
-/*! Linux specific EtherFabric initialisation */
-extern void linux_efrm_nic_dtor(struct linux_efhw_nic *);
-
/*! Linux specific EtherFabric initialisation -- interrupt registration */
extern int linux_efrm_irq_ctor(struct linux_efhw_nic *);
efrm_nic_add(struct pci_dev *dev, unsigned int opts, const uint8_t *mac_addr,
struct linux_efhw_nic **lnic_out, spinlock_t *reg_lock,
int bt_min, int bt_max, int non_irq_evq,
- const struct vi_resource_dimensions *);
+ const struct vi_resource_dimensions *, int ifindex);
extern void efrm_nic_del(struct linux_efhw_nic *);
* This file contains EtherFabric Generic NIC instance (init, interrupts,
* etc)
*
- * Copyright 2005-2007: Solarflare Communications Inc,
+ * Copyright 2005-2010: Solarflare Communications Inc,
* 9501 Jeronimo Road, Suite 250,
* Irvine, CA 92618, USA
*
#include <ci/efhw/nic.h>
#include <ci/efhw/eventq.h>
-
+/* Return 0 if not a known type */
int efhw_device_type_init(struct efhw_device_type *dt,
int vendor_id, int device_id,
int class_revision)
if (vendor_id != 0x1924)
return 0;
+ memset(dt, 0, sizeof(*dt));
+
switch (device_id) {
case 0x0703:
case 0x6703:
return 0;
}
break;
+ /* Development */
+ case 0x0770:
+ dt->arch = EFHW_ARCH_FALCON;
+ dt->variant = 'C';
+ dt->in_fpga = 1;
+ break;
case 0x7777:
dt->arch = EFHW_ARCH_FALCON;
dt->variant = 'C';
+ dt->in_fpga = 1;
switch (class_revision) {
case 0:
dt->revision = 0;
return 0;
}
break;
+ /* cosim */
+ case 0x7778:
+ dt->arch = EFHW_ARCH_FALCON;
+ dt->variant = 'C';
+ dt->in_cosim = 1;
+ dt->revision = 0;
+ if (class_revision > 0xf)
+ return 0;
+ break;
+ case 0x0803:
+ dt->arch = EFHW_ARCH_FALCON;
+ dt->variant = 'C';
+ switch (class_revision) {
+ case 0: /* ASIC */
+ dt->revision = 0;
+ dt->in_fpga = 0;
+ break;
+
+ case 1:
+ case 2: /* 20/Oct/08 indicates DBI has been alt initialized */
+ case 3: /* 30/Sep/08 indicates DBI has been initialized */
+ dt->revision = 0;
+ dt->in_fpga = 1;
+ break;
+
+ default:
+ return 0;
+ }
+ break;
default:
return 0;
}
switch (nic->devtype.variant) {
case 'A':
nic->ctr_ap_bar = FALCON_S_CTR_AP_BAR;
+ nic->num_evqs = 4096;
+ nic->num_dmaqs = 4096;
+ nic->num_timers = 4096;
break;
case 'B':
+ nic->flags |= NIC_FLAG_NO_INTERRUPT;
+ nic->ctr_ap_bar = FALCON_P_CTR_AP_BAR;
+ nic->num_evqs = 4096;
+ nic->num_dmaqs = 4096;
+ nic->num_timers = 4096;
+ break;
case 'C':
nic->flags |= NIC_FLAG_NO_INTERRUPT;
nic->ctr_ap_bar = FALCON_P_CTR_AP_BAR;
+ nic->num_evqs = 1024;
+ nic->num_dmaqs = 1024;
+ nic->num_timers = 1024;
+ nic->ctr_ap_bytes = EFHW_16M;
break;
default:
EFHW_ASSERT(0);
/* Check that we have functional units because the software only
* driver doesn't initialise anything hardware related any more */
+#ifndef __ci_ul_driver__
/* close interrupts is called first because the act of deregistering
the driver could cause this driver to change from master to slave
and hence the implicit interrupt mappings would be wrong */
efhw_nic_close_hardware(nic);
}
EFHW_TRACE("%s: functional units ... done", __FUNCTION__);
+#endif
/* destroy event queues */
EFHW_TRACE("%s: event queues ... ", __FUNCTION__);
+#ifndef __ci_ul_driver__
if (nic->interrupting_evq.evq_mask)
efhw_keventq_dtor(nic, &nic->interrupting_evq);
if (nic->non_interrupting_evq.evq_mask)
efhw_keventq_dtor(nic, &nic->non_interrupting_evq);
+#endif
EFHW_TRACE("%s: event queues ... done", __FUNCTION__);
*
* This file contains main driver entry points.
*
- * Copyright 2005-2007: Solarflare Communications Inc,
+ * Copyright 2005-2010: Solarflare Communications Inc,
* 9501 Jeronimo Road, Suite 250,
* Irvine, CA 92618, USA
*
#include <ci/driver/resource/efx_vi.h>
#include <ci/efhw/eventq.h>
#include <ci/efhw/nic.h>
+#include <ci/efhw/falcon.h>
#include <ci/efrm/buffer_table.h>
#include <ci/efrm/vi_resource_private.h>
#include <ci/efrm/driver_private.h>
* Module load time variables
*
*--------------------------------------------------------------------*/
-/* See docs/notes/pci_alloc_consistent */
-static int do_irq = 1; /* enable interrupts */
#if defined(CONFIG_X86_XEN)
static int irq_moderation = 60; /* interrupt moderation (60 usec) */
#else
static int irq_moderation = 20; /* interrupt moderation (20 usec) */
#endif
-static int nic_options = NIC_OPT_DEFAULT;
int efx_vi_eventq_size = EFX_VI_EVENTQ_SIZE_DEFAULT;
-module_param(do_irq, int, S_IRUGO);
-MODULE_PARM_DESC(do_irq, "Enable interrupts. "
- "Do not turn it off unless you know what are you doing.");
module_param(irq_moderation, int, S_IRUGO);
MODULE_PARM_DESC(irq_moderation, "IRQ moderation in usec");
-module_param(nic_options, int, S_IRUGO);
-MODULE_PARM_DESC(nic_options, "Nic options -- see efhw_types.h");
module_param(efx_vi_eventq_size, int, S_IRUGO);
MODULE_PARM_DESC(efx_vi_eventq_size,
"Size of event queue allocated by efx_vi library");
int linux_efrm_irq_ctor(struct linux_efhw_nic *lnic)
{
- struct efhw_nic *nic = &lnic->nic;
+ struct efhw_nic *nic = &lnic->efrm_nic.efhw_nic;
nic->flags &= ~NIC_FLAG_MSI;
if (nic->flags & NIC_FLAG_TRY_MSI) {
int rc = pci_enable_msi(lnic->pci_dev);
if (rc < 0) {
EFRM_WARN("%s: Could not enable MSI (%d)",
- __FUNCTION__, rc);
+ __func__, rc);
EFRM_WARN("%s: Continuing with legacy interrupt mode",
- __FUNCTION__);
+ __func__);
} else {
- EFRM_NOTICE("%s: MSI enabled", __FUNCTION__);
+ EFRM_NOTICE("%s: MSI enabled", __func__);
nic->flags |= NIC_FLAG_MSI;
}
}
void linux_efrm_irq_dtor(struct linux_efhw_nic *lnic)
{
- EFRM_TRACE("linux_efrm_irq_dtor: start");
+ EFRM_TRACE("%s: start", __func__);
- if (lnic->nic.flags & NIC_FLAG_OS_IRQ_EN) {
- free_irq(lnic->pci_dev->irq, &lnic->nic);
- lnic->nic.flags &= ~NIC_FLAG_OS_IRQ_EN;
+ if (lnic->efrm_nic.efhw_nic.flags & NIC_FLAG_OS_IRQ_EN) {
+ free_irq(lnic->pci_dev->irq, &lnic->efrm_nic.efhw_nic);
+ lnic->efrm_nic.efhw_nic.flags &= ~NIC_FLAG_OS_IRQ_EN;
}
- if (lnic->nic.flags & NIC_FLAG_MSI) {
+ if (lnic->efrm_nic.efhw_nic.flags & NIC_FLAG_MSI) {
pci_disable_msi(lnic->pci_dev);
- lnic->nic.flags &= ~NIC_FLAG_MSI;
+ lnic->efrm_nic.efhw_nic.flags &= ~NIC_FLAG_MSI;
}
- EFRM_TRACE("linux_efrm_irq_dtor: done");
+ EFRM_TRACE("%s: done", __func__);
}
/* Allocate buffer table entries for a particular NIC.
if (capacity > nic->evq_sizes) {
EFRM_ERR
("%s: Unable to choose EVQ size (supported=%x)",
- __FUNCTION__, nic->evq_sizes);
+ __func__, nic->evq_sizes);
return -E2BIG;
} else if (capacity & nic->evq_sizes)
break;
if (rc < 0) {
EFRM_WARN
("%s: failed (%d) to alloc %d buffer table entries",
- __FUNCTION__, rc, page_order);
+ __func__, rc, page_order);
return rc;
}
}
if (rc < 0) {
EFRM_WARN
("%s: failed (%d) to alloc %d buffer table entries",
- __FUNCTION__, rc, page_order);
+ __func__, rc, page_order);
return rc;
}
if (ioaddr == 0)
return -ENOMEM;
- lnic->nic.bar_ioaddr = ioaddr;
+ lnic->efrm_nic.efhw_nic.bar_ioaddr = ioaddr;
return 0;
}
static int linux_efhw_nic_map_ctr_ap(struct linux_efhw_nic *lnic)
{
- struct efhw_nic *nic = &lnic->nic;
+ struct efhw_nic *nic = &lnic->efrm_nic.efhw_nic;
int rc;
rc = iomap_bar(lnic, nic->ctr_ap_bytes);
-#if defined(__CI_HARDWARE_CONFIG_FALCON__)
/* Bug 5195: workaround for now. */
if (rc != 0 && nic->ctr_ap_bytes > 16 * 1024 * 1024) {
/* Try half the size for now. */
nic->ctr_ap_bytes);
rc = iomap_bar(lnic, nic->ctr_ap_bytes);
}
-#endif
-
if (rc < 0) {
EFRM_ERR("Failed (%d) to map bar (%d bytes)",
rc, nic->ctr_ap_bytes);
return rc;
}
-int
+static int
linux_efrm_nic_ctor(struct linux_efhw_nic *lnic, struct pci_dev *dev,
spinlock_t *reg_lock,
- unsigned nic_flags, unsigned nic_options)
+ unsigned nic_flags)
{
struct efhw_device_type dev_type;
- struct efhw_nic *nic = &lnic->nic;
+ struct efhw_nic *nic = &lnic->efrm_nic.efhw_nic;
u8 class_revision;
int rc;
rc = pci_read_config_byte(dev, PCI_CLASS_REVISION, &class_revision);
if (rc != 0) {
EFRM_ERR("%s: pci_read_config_byte failed (%d)",
- __FUNCTION__, rc);
+ __func__, rc);
return rc;
}
if (!efhw_device_type_init(&dev_type, dev->vendor, dev->device,
class_revision)) {
EFRM_ERR("%s: efhw_device_type_init failed %04x:%04x(%d)",
- __FUNCTION__, (unsigned) dev->vendor,
+ __func__, (unsigned) dev->vendor,
(unsigned) dev->device, (int) class_revision);
return -ENODEV;
}
dev_type.arch, dev_type.variant, dev_type.revision);
/* Initialise the adapter-structure. */
- efhw_nic_init(nic, nic_flags, nic_options, dev_type);
+ efhw_nic_init(nic, nic_flags, NIC_OPT_DEFAULT, dev_type);
lnic->pci_dev = dev;
rc = pci_enable_device(dev);
if (rc < 0) {
EFRM_ERR("%s: pci_enable_device failed (%d)",
- __FUNCTION__, rc);
+ __func__, rc);
return rc;
}
lnic->ctr_ap_pci_addr = pci_resource_start(dev, nic->ctr_ap_bar);
if (!pci_dma_supported(dev, (dma_addr_t)EFHW_DMA_ADDRMASK)) {
- EFRM_ERR("%s: pci_dma_supported(%lx) failed", __FUNCTION__,
+ EFRM_ERR("%s: pci_dma_supported(%lx) failed", __func__,
(unsigned long)EFHW_DMA_ADDRMASK);
return -ENODEV;
}
if (pci_set_dma_mask(dev, (dma_addr_t)EFHW_DMA_ADDRMASK)) {
- EFRM_ERR("%s: pci_set_dma_mask(%lx) failed", __FUNCTION__,
+ EFRM_ERR("%s: pci_set_dma_mask(%lx) failed", __func__,
(unsigned long)EFHW_DMA_ADDRMASK);
return -ENODEV;
}
if (pci_set_consistent_dma_mask(dev, (dma_addr_t)EFHW_DMA_ADDRMASK)) {
EFRM_ERR("%s: pci_set_consistent_dma_mask(%lx) failed",
- __FUNCTION__, (unsigned long)EFHW_DMA_ADDRMASK);
+ __func__, (unsigned long)EFHW_DMA_ADDRMASK);
return -ENODEV;
}
return 0;
}
-void linux_efrm_nic_dtor(struct linux_efhw_nic *lnic)
+static void linux_efrm_nic_dtor(struct linux_efhw_nic *lnic)
{
- struct efhw_nic *nic = &lnic->nic;
+ struct efhw_nic *nic = &lnic->efrm_nic.efhw_nic;
volatile char __iomem *bar_ioaddr = nic->bar_ioaddr;
efhw_nic_dtor(nic);
EFRM_ASSERT(!(nic->flags & NIC_FLAG_NO_INTERRUPT));
efhw_keventq_poll(nic, &nic->interrupting_evq);
- EFRM_TRACE("tasklet complete");
+ EFRM_TRACE("%s: complete", __func__);
}
/****************************************************************************
{
/* NB. The interrupt must have already been acked (for legacy mode). */
- EFRM_TRACE("%s: starting tasklet", __FUNCTION__);
+ EFRM_TRACE("%s: starting tasklet", __func__);
EFRM_ASSERT(!(nic->flags & NIC_FLAG_NO_INTERRUPT));
tasklet_schedule(&linux_efhw_nic(nic)->tasklet);
efrm_nic_add(struct pci_dev *dev, unsigned flags, const uint8_t *mac_addr,
struct linux_efhw_nic **lnic_out, spinlock_t *reg_lock,
int bt_min, int bt_lim, int non_irq_evq,
- const struct vi_resource_dimensions *res_dim)
+ const struct vi_resource_dimensions *res_dim, int ifindex)
{
struct linux_efhw_nic *lnic = NULL;
struct efhw_nic *nic = NULL;
int buffers_allocated = 0;
static unsigned nic_index; /* = 0; */
- EFRM_TRACE("%s: device detected (Slot '%s', IRQ %d)", __FUNCTION__,
- pci_name(dev) ? pci_name(dev) : "?", dev->irq);
+ EFRM_NOTICE("%s: device detected (Slot '%s', IRQ %d)", __func__,
+ pci_name(dev) ? pci_name(dev) : "?", dev->irq);
/* Ensure that we have room for the new adapter-structure. */
if (efrm_nic_tablep->nic_count == EFHW_MAX_NR_DEVS) {
- EFRM_WARN("%s: WARNING: too many devices", __FUNCTION__);
+ EFRM_ERR("%s: ERROR: too many devices", __func__);
rc = -ENOMEM;
goto failed;
}
/* Allocate memory for the new adapter-structure. */
lnic = kmalloc(sizeof(*lnic), GFP_KERNEL);
if (lnic == NULL) {
- EFRM_ERR("%s: ERROR: failed to allocate memory", __FUNCTION__);
+ EFRM_ERR("%s: ERROR: failed to allocate memory", __func__);
rc = -ENOMEM;
goto failed;
}
memset(lnic, 0, sizeof(*lnic));
- nic = &lnic->nic;
+ nic = &lnic->efrm_nic.efhw_nic;
lnic->ev_handlers = &ev_handler;
/* OS specific hardware mappings */
- rc = linux_efrm_nic_ctor(lnic, dev, reg_lock, flags, nic_options);
+ rc = linux_efrm_nic_ctor(lnic, dev, reg_lock, flags);
if (rc < 0) {
- EFRM_ERR("%s: ERROR: initialisation failed", __FUNCTION__);
+ EFRM_ERR("%s: ERROR: linux_efrm_nic_ctor failed (%d)",
+ __func__, rc);
goto failed;
}
unreliable hardware initialisation. However, there's quite a lot
of code to review if we wanted to hardware init before bringing
up the resource managers. */
- rc = efrm_driver_register_nic(nic, nic_index++);
+ rc = efrm_driver_register_nic(&lnic->efrm_nic, nic_index, ifindex);
if (rc < 0) {
- EFRM_ERR("%s: cannot register nic %d with nic error code %d",
- __FUNCTION__, efrm_nic_tablep->nic_count, rc);
+ EFRM_ERR("%s: ERROR: efrm_driver_register_nic failed (%d)",
+ __func__, rc);
goto failed;
}
+ ++nic_index;
registered_nic = 1;
rc = efrm_nic_buffer_table_alloc(nic);
if (rc < 0)
goto failed;
+ /* Tell NIC to spread wakeup events. */
+ if (nic->devtype.arch == EFHW_ARCH_FALCON &&
+ res_dim->evq_int_min > 1)
+ falcon_nic_wakeup_mask_set(nic, 1);
+
tasklet_init(&lnic->tasklet, efrm_tasklet, (ulong)nic);
/* set up interrupt handlers (hard-irq) */
nic->irq_handler = &efrm_handle_eventq_irq;
/* this device can now take management interrupts */
- if (do_irq && !(nic->flags & NIC_FLAG_NO_INTERRUPT)) {
+ if (!(nic->flags & NIC_FLAG_NO_INTERRUPT)) {
rc = linux_efrm_irq_ctor(lnic);
if (rc < 0) {
EFRM_ERR("Interrupt initialisation failed (%d)", rc);
goto failed;
}
- efhw_nic_set_interrupt_moderation(nic, irq_moderation);
+ efhw_nic_set_interrupt_moderation(nic, -1, irq_moderation);
efhw_nic_interrupt_enable(nic);
}
- EFRM_TRACE("interrupts are %sregistered", do_irq ? "" : "not ");
*lnic_out = lnic;
EFRM_ASSERT(rc == 0);
if (buffers_allocated)
efrm_nic_buffer_table_free(nic);
if (registered_nic)
- efrm_driver_unregister_nic(nic);
+ efrm_driver_unregister_nic(&lnic->efrm_nic);
if (constructed)
linux_efrm_nic_dtor(lnic);
kfree(lnic); /* safe in any case */
****************************************************************************/
void efrm_nic_del(struct linux_efhw_nic *lnic)
{
- struct efhw_nic *nic = &lnic->nic;
+ struct efhw_nic *nic = &lnic->efrm_nic.efhw_nic;
- EFRM_TRACE("%s:", __FUNCTION__);
+ EFRM_TRACE("%s:", __func__);
EFRM_ASSERT(nic);
efrm_nic_buffer_table_free(nic);
- efrm_driver_unregister_nic(nic);
+ efrm_driver_unregister_nic(&lnic->efrm_nic);
/*
* Synchronise here with any running ISR.
}
/* Close down hardware and free resources. */
- linux_efrm_nic_dtor(lnic);
- kfree(lnic);
-
if (--n_nics_probed == 0)
efrm_resources_fini();
- EFRM_TRACE("NIC teardown: Done");
+ linux_efrm_nic_dtor(lnic);
+ kfree(lnic);
+
+ EFRM_TRACE("%s: done", __func__);
}
/****************************************************************************
{
int rc = 0;
- EFRM_TRACE("%s: RESOURCE driver starting", __FUNCTION__);
+ EFRM_TRACE("%s: RESOURCE driver starting", __func__);
- rc = efrm_driver_ctor();
- if (rc < 0) {
- EFRM_ERR("%s: efrm_driver_ctor: error %d", __FUNCTION__, rc);
- goto fail_driver_ctor;
- }
+ efrm_driver_ctor();
/* Register the driver so that our 'probe' function is called for
* each EtherFabric device in the system.
*/
rc = efrm_driverlink_register();
if (rc == -ENODEV)
- EFRM_ERR("%s: no devices found", __FUNCTION__);
+ EFRM_ERR("%s: no devices found", __func__);
if (rc < 0)
goto failed_driverlink;
if (efrm_install_proc_entries() != 0) {
/* Do not fail, but print a warning */
EFRM_WARN("%s: WARNING: failed to install /proc entries",
- __FUNCTION__);
+ __func__);
}
return 0;
failed_driverlink:
- /* No need to release resource managers here since they register
- * destructors with the driver. */
efrm_driver_dtor();
-fail_driver_ctor:
- EFRM_ASSERT(rc != 0);
return rc;
}
- driver dtor can use both work queue and buffer table entries */
efrm_driver_dtor();
- EFRM_TRACE("unloaded");
+ EFRM_TRACE("%s: unloaded", __func__);
}
module_init(init_sfc_resource);
*
* This file contains generic code for resources and resource managers.
*
- * Copyright 2005-2007: Solarflare Communications Inc,
+ * Copyright 2005-2010: Solarflare Communications Inc,
* 9501 Jeronimo Road, Suite 250,
* Irvine, CA 92618, USA
*
#include <ci/efrm/nic_table.h>
#include <ci/efhw/iopage.h>
#include <ci/efrm/driver_private.h>
-
-/**********************************************************************
- * Internal stuff.
- */
-
-#define EFRM_RM_TABLE_SIZE_INIT 256
-
-static int grow_table(struct efrm_resource_manager *rm, unsigned min_size)
-{
- irq_flags_t lock_flags;
- struct efrm_resource **table, **old_table;
- unsigned new_size;
-
- EFRM_RESOURCE_MANAGER_ASSERT_VALID(rm);
-
- spin_lock_irqsave(&rm->rm_lock, lock_flags);
-
- /* Check whether the size of the table increased whilst the lock was
- * dropped. */
- if (min_size <= rm->rm_table_size) {
- spin_unlock_irqrestore(&rm->rm_lock, lock_flags);
- return 0;
- }
-
- new_size = rm->rm_table_size << 1;
- if (new_size < min_size)
- new_size = min_size;
-
- spin_unlock_irqrestore(&rm->rm_lock, lock_flags);
- if (in_atomic()) {
- EFRM_WARN("%s: in_atomic in grow_table()", __FUNCTION__);
- EFRM_WARN("%s: allocating %u bytes", __FUNCTION__,
- (unsigned)(new_size *
- sizeof(struct efrm_resource *)));
- return -ENOMEM;
- }
-
- table =
- (struct efrm_resource **)vmalloc(new_size *
- sizeof(struct efrm_resource *));
- spin_lock_irqsave(&rm->rm_lock, lock_flags);
-
- if (table == 0) {
- EFRM_ERR("%s: out of memory in grow_table()", __FUNCTION__);
- EFRM_ERR("%s: allocating %u bytes", __FUNCTION__,
- (unsigned)(new_size *
- sizeof(struct efrm_resource *)));
- spin_unlock_irqrestore(&rm->rm_lock, lock_flags);
- return -ENOMEM;
- }
-
- /* Could have got bigger while we dropped the lock... */
- if (new_size <= rm->rm_table_size) {
- spin_unlock_irqrestore(&rm->rm_lock, lock_flags);
- vfree(table);
- return 0;
- }
-
- memcpy(table, rm->rm_table, rm->rm_table_size * sizeof(*table));
- memset(table + rm->rm_table_size, 0,
- sizeof(*table) * (new_size - rm->rm_table_size));
- /* remember old table so we can free the
- memory after we drop the lock (bug 1040) */
- old_table = rm->rm_table;
- rm->rm_table = table;
- rm->rm_table_size = new_size;
- spin_unlock_irqrestore(&rm->rm_lock, lock_flags);
- vfree(old_table);
-
- return 0;
-}
+#include <ci/efrm/private.h>
+#include "efrm_internal.h"
/**********************************************************************
* struct efrm_resource_manager
EFRM_ERR("%s: %s leaked %d resources",
__FUNCTION__, rm->rm_name, rm->rm_resources));
EFRM_ASSERT(rm->rm_resources == 0);
+ EFRM_ASSERT(list_empty(&rm->rm_resources_list));
rm->rm_dtor(rm);
/* clear out things built by efrm_resource_manager_ctor */
spin_lock_destroy(&rm->rm_lock);
- vfree(rm->rm_table);
/* and the free the memory */
EFRM_DO_DEBUG(memset(rm, 0, sizeof(*rm)));
int
efrm_resource_manager_ctor(struct efrm_resource_manager *rm,
void (*dtor)(struct efrm_resource_manager *),
- const char *name, unsigned type,
- int initial_table_size)
+ const char *name, unsigned type)
{
EFRM_ASSERT(rm);
EFRM_ASSERT(dtor);
spin_lock_init(&rm->rm_lock);
rm->rm_resources = 0;
rm->rm_resources_hiwat = 0;
-
- /* if not set then pick a number */
- rm->rm_table_size = (initial_table_size) ?
- initial_table_size : EFRM_RM_TABLE_SIZE_INIT;
-
- rm->rm_table = vmalloc(rm->rm_table_size *
- sizeof(struct efrm_resource *));
-
- if (rm->rm_table == 0) {
- spin_lock_destroy(&rm->rm_lock);
- return -ENOMEM;
- }
- memset(rm->rm_table, 0, sizeof(*rm->rm_table) * rm->rm_table_size);
-
+ INIT_LIST_HEAD(&rm->rm_resources_list);
EFRM_RESOURCE_MANAGER_ASSERT_VALID(rm);
return 0;
}
-int efrm_resource_manager_insert(struct efrm_resource *rs)
+
+void efrm_client_add_resource(struct efrm_client *client,
+ struct efrm_resource *rs)
{
- irq_flags_t lock_flags;
struct efrm_resource_manager *rm;
- int instance = EFRM_RESOURCE_INSTANCE(rs->rs_handle);
+ irq_flags_t lock_flags;
- EFRM_ASSERT(EFRM_RESOURCE_TYPE(rs->rs_handle) < EFRM_RESOURCE_NUM);
- rm = efrm_rm_table[EFRM_RESOURCE_TYPE(rs->rs_handle)];
- EFRM_ASSERT(EFRM_RESOURCE_TYPE(rs->rs_handle) == rm->rm_type);
- EFRM_RESOURCE_ASSERT_VALID(rs, 0);
+ EFRM_ASSERT(client != NULL);
+ EFRM_ASSERT(rs != NULL);
- /* Put an entry in the resource table. */
- spin_lock_irqsave(&rm->rm_lock, lock_flags);
- if ((unsigned)instance >= rm->rm_table_size) {
- spin_unlock_irqrestore(&rm->rm_lock, lock_flags);
- if (grow_table(rm, instance + 1) < 0)
- return -ENOMEM;
- spin_lock_irqsave(&rm->rm_lock, lock_flags);
- }
- EFRM_ASSERT(rm->rm_table_size > (unsigned)instance);
- EFRM_ASSERT(rm->rm_table[instance] == NULL);
- rm->rm_table[instance] = rs;
- rm->rm_resources++;
+ spin_lock_irqsave(&efrm_nic_tablep->lock, lock_flags);
+ rm = efrm_rm_table[EFRM_RESOURCE_TYPE(rs->rs_handle)];
+ ++rm->rm_resources;
+ list_add(&rs->rs_manager_link, &rm->rm_resources_list);
if (rm->rm_resources > rm->rm_resources_hiwat)
rm->rm_resources_hiwat = rm->rm_resources;
-
- /* Put the resource in the linked list. */
- /* ?? broken list_add(&rm->rm_resources, &rs->rs_link); */
- /* DJR wrote that it causes problem on driver unload, and DR tried
- * it and saw (probably) this cause an assertion failure due to a
- * bad link structure in
- * /runbench/results/2005/09/22/0_DupTester_15-16-46 */
-
- spin_unlock_irqrestore(&rm->rm_lock, lock_flags);
-
- return 0;
+ rs->rs_client = client;
+ ++client->ref_count;
+ list_add(&rs->rs_client_link, &client->resources);
+ spin_unlock_irqrestore(&efrm_nic_tablep->lock, lock_flags);
}
-bool __efrm_resource_ref_count_zero(unsigned type, unsigned instance)
+
+void efrm_resource_ref(struct efrm_resource *rs)
{
- /* This is rather nasty because when a resource's ref count goes to
- * zero there is still a pointer to it in the [rm_table]. Thus
- * arriving here does not guarantee that we have exclusive access
- * to the resource and can free it. In fact the resource may
- * already have been freed by another thread (after we dropped our
- * ref, but before arriving here).
- *
- * At this point the only pointers to this resource should be [rs]
- * and the one in [rm_table]. EXCEPT: Someone could have got in
- * and looked-up the resource in the table before we got the lock.
- * In this case the ref will have been hiked again.
- *
- * Therefore, if ref count is non-zero here, we shouldn't do
- * anything, as someone else holds a ref to the resource, and will
- * eventually release it.
- *
- * Otherwise, we zero-out the table entry. Therefore we have the
- * only pointer to the resource, and can kill it safely.
- */
- struct efrm_resource_manager *rm = efrm_rm_table[type];
irq_flags_t lock_flags;
- struct efrm_resource *rs;
- bool do_free = false;
-
- EFRM_TRACE("efrm_resource_ref_count_zero: type=%d instance=%d",
- rm->rm_type, instance);
-
- EFRM_RESOURCE_MANAGER_ASSERT_VALID(rm);
- EFRM_ASSERT(rm->rm_table_size > instance);
+ spin_lock_irqsave(&efrm_nic_tablep->lock, lock_flags);
+ ++rs->rs_ref_count;
+ spin_unlock_irqrestore(&efrm_nic_tablep->lock, lock_flags);
+}
+EXPORT_SYMBOL(efrm_resource_ref);
- spin_lock_irqsave(&rm->rm_lock, lock_flags);
- rs = rm->rm_table[instance];
- if (rs != NULL) {
- do_free = atomic_read(&rs->rs_ref_count) == 0;
- if (do_free) {
- EFRM_ASSERT(rm->rm_resources > 0);
- --rm->rm_resources;
- rm->rm_table[instance] = 0;
- }
+int __efrm_resource_release(struct efrm_resource *rs)
+{
+ struct efrm_resource_manager *rm;
+ irq_flags_t lock_flags;
+ int free_rs;
+
+ spin_lock_irqsave(&efrm_nic_tablep->lock, lock_flags);
+ free_rs = --rs->rs_ref_count == 0;
+ if (free_rs) {
+ rm = efrm_rm_table[EFRM_RESOURCE_TYPE(rs->rs_handle)];
+ EFRM_ASSERT(rm->rm_resources > 0);
+ --rm->rm_resources;
+ list_del(&rs->rs_manager_link);
+ list_del(&rs->rs_client_link);
}
-
- spin_unlock_irqrestore(&rm->rm_lock, lock_flags);
-
- return do_free;
+ spin_unlock_irqrestore(&efrm_nic_tablep->lock, lock_flags);
+ return free_rs;
}
-EXPORT_SYMBOL(__efrm_resource_ref_count_zero);
+EXPORT_SYMBOL(__efrm_resource_release);
/*
* vi: sw=8:ai:aw
*
* This file contains resource managers initialisation functions.
*
- * Copyright 2005-2007: Solarflare Communications Inc,
+ * Copyright 2005-2010: Solarflare Communications Inc,
* 9501 Jeronimo Road, Suite 250,
* Irvine, CA 92618, USA
*
*
* This file contains allocation of VI resources.
*
- * Copyright 2005-2007: Solarflare Communications Inc,
+ * Copyright 2005-2010: Solarflare Communications Inc,
* 9501 Jeronimo Road, Suite 250,
* Irvine, CA 92618, USA
*
#include <ci/efrm/private.h>
#include <ci/efrm/buffer_table.h>
#include <ci/efrm/vi_resource_private.h>
+#include <ci/efrm/efrm_client.h>
+#include "efrm_internal.h"
+
/*** Data definitions ****************************************************/
/*** Forward references **************************************************/
static int
-efrm_vi_resource_alloc_or_free(int alloc, struct vi_resource *evq_virs,
- uint16_t vi_flags, int32_t evq_capacity,
- int32_t txq_capacity, int32_t rxq_capacity,
- uint8_t tx_q_tag, uint8_t rx_q_tag,
+efrm_vi_resource_alloc_or_free(struct efrm_client *client,
+ int alloc, struct vi_resource *evq_virs,
+ unsigned vi_flags, int evq_capacity,
+ int txq_capacity, int rxq_capacity,
+ int tx_q_tag, int rx_q_tag,
struct vi_resource **virs_in_out);
/*** Reference count handling ********************************************/
{
EFRM_ASSERT(atomic_read(&virs->evq_refs) != 0);
if (atomic_dec_and_test(&virs->evq_refs))
- efrm_vi_resource_alloc_or_free(false, NULL, 0, 0, 0, 0, 0, 0,
- &virs);
+ efrm_vi_resource_alloc_or_free(virs->rs.rs_client, false, NULL,
+ 0, 0, 0, 0, 0, 0, &virs);
}
/*** Instance numbers ****************************************************/
-static inline int efrm_vi_rm_alloc_id(uint16_t vi_flags, int32_t evq_capacity)
+static inline int efrm_vi_rm_alloc_id(unsigned vi_flags, int evq_capacity)
{
irq_flags_t lock_flags;
int instance;
/* NB. This should really take a nic as an argument, but that makes
* the buffer table allocation difficult. */
uint32_t efrm_vi_rm_evq_bytes(struct vi_resource *virs
- /*,struct efhw_nic *nic */ )
+ /*,struct efhw_nic *nic */)
{
return virs->evq_capacity * sizeof(efhw_event_t);
}
/* NB. This should really take a nic as an argument, but that makes
* the buffer table allocation difficult. */
uint32_t efrm_vi_rm_txq_bytes(struct vi_resource *virs
- /*,struct efhw_nic *nic */ )
+ /*,struct efhw_nic *nic */)
{
return virs->dmaq_capacity[EFRM_VI_RM_DMA_QUEUE_TX] *
FALCON_DMA_TX_DESC_BYTES;
/* NB. This should really take a nic as an argument, but that makes
* the buffer table allocation difficult. */
uint32_t efrm_vi_rm_rxq_bytes(struct vi_resource *virs
- /*,struct efhw_nic *nic */ )
+ /*,struct efhw_nic *nic */)
{
uint32_t bytes_per_desc = ((virs->flags & EFHW_VI_RX_PHYS_ADDR_EN)
? FALCON_DMA_RX_PHYS_DESC_BYTES
/* size_rq < 0 means default, but we interpret this as 'minimum'. */
for (size = 256;; size <<= 1)
- if ((sizes & ~((size - 1) | size)) == 0)
- return -1;
- else if ((size & sizes) && size >= size_rq)
+ if ((size & sizes) && size >= size_rq)
return size;
+ else if ((sizes & ~((size - 1) | size)) == 0)
+ return -1;
}
static int
/*** Buffer Table allocations ********************************************/
-#if defined(__CI_HARDWARE_CONFIG_FALCON__)
static int
efrm_vi_rm_alloc_or_free_buffer_table(struct vi_resource *virs, bool is_alloc)
{
return rc;
}
-#endif /* defined(__CI_HARDWARE_CONFIG_FALCON__) */
/*** Per-NIC allocations *************************************************/
static inline int
-efrm_vi_rm_init_evq(struct vi_resource *virs, int nic_index)
+efrm_vi_rm_init_evq(struct vi_resource *virs, struct efhw_nic *nic)
{
- int rc;
- struct efhw_nic *nic = efrm_nic_tablep->nic[nic_index];
int instance = EFRM_RESOURCE_INSTANCE(virs->rs.rs_handle);
- struct eventq_resource_hardware *evq_hw =
- &virs->nic_info[nic_index].evq_pages;
+ struct eventq_resource_hardware *evq_hw = &virs->evq_hw;
uint32_t buf_bytes = efrm_vi_rm_evq_bytes(virs);
+ int rc;
if (virs->evq_capacity == 0)
return 0;
/* Initialise the event queue hardware */
efhw_nic_event_queue_enable(nic, instance, virs->evq_capacity,
- efhw_iopages_dma_addr(&evq_hw->iobuff) +
- evq_hw->iobuff_off,
- evq_hw->buf_tbl_alloc.base);
+ evq_hw->buf_tbl_alloc.base,
+ /* make siena look like falcon for now */
+ instance < 64,
+ /*make dos protection enable by default*/
+ 1);
EFRM_TRACE("%s: " EFRM_RESOURCE_FMT " capacity=%u", __FUNCTION__,
EFRM_RESOURCE_PRI_ARG(virs->rs.rs_handle),
* size of the requested evq up to a round number of
* pages
*/
- buf_bytes = CI_ROUND_UP(buf_bytes, PAGE_SIZE);
+ buf_bytes = CI_ROUNDUP(buf_bytes, PAGE_SIZE);
#endif
EFRM_ASSERT(buf_bytes % PAGE_SIZE == 0);
}
static inline void
-efrm_vi_rm_fini_evq(struct vi_resource *virs, int nic_index)
+efrm_vi_rm_fini_evq(struct vi_resource *virs, struct efhw_nic *nic)
{
- struct efhw_nic *nic = efrm_nic_tablep->nic[nic_index];
int instance = EFRM_RESOURCE_INSTANCE(virs->rs.rs_handle);
- struct vi_resource_nic_info *nic_info = &virs->nic_info[nic_index];
if (virs->evq_capacity == 0)
return;
And Tell NIC to stop using this event queue. */
efhw_nic_event_queue_disable(nic, instance, 0);
- if (nic_info->evq_pages.buf_tbl_alloc.base != (unsigned)-1)
- efrm_buffer_table_free(&nic_info->evq_pages.buf_tbl_alloc);
+ if (virs->evq_hw.buf_tbl_alloc.base != (unsigned)-1)
+ efrm_buffer_table_free(&virs->evq_hw.buf_tbl_alloc);
- efhw_iopages_free(nic, &nic_info->evq_pages.iobuff);
+ efhw_iopages_free(nic, &virs->evq_hw.iobuff);
}
/*! FIXME: we should make sure this number is never zero (=> unprotected) */
struct efhw_nic *nic)
{
int instance;
- struct vi_resource *evq_virs;
int evq_instance;
efhw_buffer_addr_t buf_addr;
instance = EFRM_RESOURCE_INSTANCE(virs->rs.rs_handle);
- evq_virs = virs->evq_virs;
- evq_instance = EFRM_RESOURCE_INSTANCE(evq_virs->rs.rs_handle);
+ evq_instance = EFRM_RESOURCE_INSTANCE(virs->evq_virs->rs.rs_handle);
buf_addr = virs->dmaq_buf_tbl_alloc[queue_type].base;
static int
efrm_vi_rm_init_or_fini_dmaq(struct vi_resource *virs,
- int queue_type, int init, int nic_index)
+ int queue_type, int init,
+ struct efhw_nic *nic)
{
int rc;
- struct efhw_nic *nic = efrm_nic_tablep->nic[nic_index];
int instance = EFRM_RESOURCE_INSTANCE(virs->rs.rs_handle);
uint32_t buf_bytes;
- struct vi_resource *evq_virs;
-
-#if defined(__CI_HARDWARE_CONFIG_FALCON__)
- struct vi_resource_nic_info *nic_info = &virs->nic_info[nic_index];
int page_order;
uint32_t num_pages;
struct efhw_iopages *iobuff;
-#endif
if (!init)
goto destroy;
? efrm_vi_rm_txq_bytes(virs)
: efrm_vi_rm_rxq_bytes(virs));
-#if defined(__CI_HARDWARE_CONFIG_FALCON__)
page_order = get_order(buf_bytes);
- rc = efhw_iopages_alloc(nic, &nic_info->dmaq_pages[queue_type],
+ rc = efhw_iopages_alloc(nic, &virs->dmaq_pages[queue_type],
page_order);
if (rc != 0) {
EFRM_ERR("%s: Failed to allocate %s DMA buffer.", __FUNCTION__,
}
num_pages = 1 << page_order;
- iobuff = &nic_info->dmaq_pages[queue_type];
+ iobuff = &virs->dmaq_pages[queue_type];
efhw_nic_buffer_table_set_n(nic,
virs->dmaq_buf_tbl_alloc[queue_type].base,
efhw_iopages_dma_addr(iobuff),
falcon_nic_buffer_table_confirm(nic);
- virs->mem_mmap_bytes += round_up(buf_bytes, PAGE_SIZE);
-#endif /* __CI_HARDWARE_CONFIG_FALCON__ */
-
- evq_virs = virs->evq_virs;
- EFRM_ASSERT(evq_virs);
+ virs->mem_mmap_bytes += roundup(buf_bytes, PAGE_SIZE);
/* Make sure there is an event queue. */
- if (evq_virs->evq_capacity <= 0) {
+ if (virs->evq_virs->evq_capacity <= 0) {
EFRM_ERR("%s: Cannot use empty event queue for %s DMA",
__FUNCTION__, dmaq_names[queue_type]);
rc = -EINVAL;
/* No need to disable the queue here. Nobody is using it anyway. */
fail_evq:
-#if defined(__CI_HARDWARE_CONFIG_FALCON__)
- efhw_iopages_free(nic, &nic_info->dmaq_pages[queue_type]);
+ efhw_iopages_free(nic, &virs->dmaq_pages[queue_type]);
fail_iopages:
-#endif
-
return rc;
}
+
static int
-efrm_vi_rm_init_or_fini_nic(struct vi_resource *virs, int init, int nic_index)
+efrm_vi_rm_init_or_fini_nic(struct vi_resource *virs, int init,
+ struct efhw_nic *nic)
{
- struct vi_resource *evq_virs;
- int rc;
-#if defined(__CI_HARDWARE_CONFIG_FALCON__)
#ifndef NDEBUG
int instance = EFRM_RESOURCE_INSTANCE(virs->rs.rs_handle);
#endif
-#endif
+ int rc;
if (!init)
goto destroy;
- evq_virs = virs->evq_virs;
- if (evq_virs != virs) {
- if (!efrm_nic_set_read(&evq_virs->nic_set, nic_index)) {
- /* Ignore this NIC. It's not supported by the event
- * queue. */
- return 0;
- }
- }
-
- rc = efrm_vi_rm_init_evq(virs, nic_index);
+ rc = efrm_vi_rm_init_evq(virs, nic);
if (rc != 0)
goto fail_evq;
rc = efrm_vi_rm_init_or_fini_dmaq(virs, EFRM_VI_RM_DMA_QUEUE_TX,
- init, nic_index);
+ init, nic);
if (rc != 0)
goto fail_txq;
rc = efrm_vi_rm_init_or_fini_dmaq(virs, EFRM_VI_RM_DMA_QUEUE_RX,
- init, nic_index);
+ init, nic);
if (rc != 0)
goto fail_rxq;
-#if defined(__CI_HARDWARE_CONFIG_FALCON__)
/* Allocate space for the control page. */
EFRM_ASSERT(falcon_tx_dma_page_offset(instance) < PAGE_SIZE);
EFRM_ASSERT(falcon_rx_dma_page_offset(instance) < PAGE_SIZE);
EFRM_ASSERT(falcon_timer_page_offset(instance) < PAGE_SIZE);
virs->bar_mmap_bytes += PAGE_SIZE;
-#endif
-
- /* Mark the NIC as having been initialised. */
- efrm_nic_set_write(&virs->nic_set, nic_index, true);
-
return 0;
destroy:
rc = 0;
efrm_vi_rm_init_or_fini_dmaq(virs, EFRM_VI_RM_DMA_QUEUE_RX,
- false, nic_index);
+ false, nic);
fail_rxq:
efrm_vi_rm_init_or_fini_dmaq(virs, EFRM_VI_RM_DMA_QUEUE_TX,
- false, nic_index);
+ false, nic);
fail_txq:
- efrm_vi_rm_fini_evq(virs, nic_index);
+ efrm_vi_rm_fini_evq(virs, nic);
fail_evq:
- /* Mark the NIC as having been finalised. */
- efrm_nic_set_write(&virs->nic_set, nic_index, false);
EFRM_ASSERT(rc != 0 || !init);
-
return rc;
}
static int
-efrm_vi_resource_alloc_or_free(int alloc, struct vi_resource *evq_virs,
- uint16_t vi_flags, int32_t evq_capacity,
- int32_t txq_capacity, int32_t rxq_capacity,
- uint8_t tx_q_tag, uint8_t rx_q_tag,
+efrm_vi_resource_alloc_or_free(struct efrm_client *client,
+ int alloc, struct vi_resource *evq_virs,
+ unsigned vi_flags, int evq_capacity,
+ int txq_capacity, int rxq_capacity,
+ int tx_q_tag, int rx_q_tag,
struct vi_resource **virs_in_out)
{
+ struct efhw_nic *nic = client->nic;
struct vi_resource *virs;
int rc;
int instance;
- struct efhw_nic *nic;
- int nic_i;
EFRM_ASSERT(virs_in_out);
EFRM_ASSERT(efrm_vi_manager);
if (!alloc)
goto destroy;
-#if defined(__CI_HARDWARE_CONFIG_FALCON__)
- rx_q_tag &= (1 << TX_DESCQ_LABEL_WIDTH) - 1;
- tx_q_tag &= (1 << RX_DESCQ_LABEL_WIDTH) - 1;
-#endif
+ rx_q_tag &= (1 << FRF_AZ_TX_DESCQ_LABEL_WIDTH) - 1;
+ tx_q_tag &= (1 << FRF_AZ_RX_DESCQ_LABEL_WIDTH) - 1;
virs = kmalloc(sizeof(*virs), GFP_KERNEL);
if (virs == NULL) {
* is freed. */
atomic_set(&virs->evq_refs, 1);
- efrm_nic_set_clear(&virs->nic_set);
-
virs->bar_mmap_bytes = 0;
virs->mem_mmap_bytes = 0;
virs->evq_capacity = evq_capacity;
virs->dmaq_capacity[EFRM_VI_RM_DMA_QUEUE_TX] = txq_capacity;
virs->dmaq_capacity[EFRM_VI_RM_DMA_QUEUE_RX] = rxq_capacity;
- virs->dmaq_tag[EFRM_VI_RM_DMA_QUEUE_TX] = tx_q_tag;
- virs->dmaq_tag[EFRM_VI_RM_DMA_QUEUE_RX] = rx_q_tag;
+ virs->dmaq_tag[EFRM_VI_RM_DMA_QUEUE_TX] = (uint8_t) tx_q_tag;
+ virs->dmaq_tag[EFRM_VI_RM_DMA_QUEUE_RX] = (uint8_t) rx_q_tag;
virs->flags = vi_flags;
-
INIT_LIST_HEAD(&virs->tx_flush_link);
INIT_LIST_HEAD(&virs->rx_flush_link);
- efrm_nic_set_clear(&virs->tx_flush_nic_set);
- efrm_nic_set_clear(&virs->rx_flush_nic_set);
-
- memset(&efrm_vi_manager->evq_infos[instance], 0,
- sizeof(struct vi_resource_evq_info));
- efrm_vi_manager->evq_infos[instance].evq_virs = virs;
+ virs->tx_flushing = 0;
+ virs->rx_flushing = 0;
/* Adjust the queue sizes. */
- rc = 0;
- EFRM_FOR_EACH_NIC(nic_i, nic)
- if (rc == 0)
- rc = efrm_vi_rm_adjust_alloc_request(virs, nic);
+ rc = efrm_vi_rm_adjust_alloc_request(virs, nic);
if (rc != 0)
goto fail_adjust_request;
}
virs->evq_virs = evq_virs;
-#if defined(__CI_HARDWARE_CONFIG_FALCON__)
rc = efrm_vi_rm_alloc_or_free_buffer_table(virs, true);
if (rc != 0)
goto fail_buffer_table;
-#endif
- rc = 0;
- EFRM_FOR_EACH_NIC(nic_i, nic)
- if (rc == 0)
- /* This updates virs->nic_set for the NICs which need
- * finalising. */
- rc = efrm_vi_rm_init_or_fini_nic(virs, true, nic_i);
+ rc = efrm_vi_rm_init_or_fini_nic(virs, true, nic);
if (rc != 0)
goto fail_init_nic;
- /* Put it into the resource manager's table. */
- rc = efrm_resource_manager_insert(&virs->rs);
- if (rc != 0) {
- if (atomic_dec_and_test(&virs->rs.rs_ref_count))
- efrm_vi_resource_free(virs);
- return rc;
- }
-
+ efrm_client_add_resource(client, &virs->rs);
*virs_in_out = virs;
EFRM_TRACE("%s: Allocated " EFRM_RESOURCE_FMT, __FUNCTION__,
EFRM_RESOURCE_PRI_ARG(virs->rs.rs_handle));
rc = 0;
fail_init_nic:
- EFRM_FOR_EACH_NIC_IN_SET(&virs->nic_set, nic_i, nic)
- efrm_vi_rm_init_or_fini_nic(virs, false, nic_i);
+ efrm_vi_rm_init_or_fini_nic(virs, false, nic);
-#if defined(__CI_HARDWARE_CONFIG_FALCON__)
efrm_vi_rm_alloc_or_free_buffer_table(virs, false);
fail_buffer_table:
-#endif
efrm_vi_rm_detach_evq(virs);
fail_adjust_request:
EFRM_ASSERT(virs->evq_callback_fn == NULL);
- memset(&efrm_vi_manager->evq_infos[instance], 0,
- sizeof(struct vi_resource_evq_info));
EFRM_TRACE("%s: delete VI ID %d", __FUNCTION__, instance);
efrm_vi_rm_free_id(instance);
fail_alloc_id:
-
+ if (!alloc)
+ efrm_client_put(virs->rs.rs_client);
EFRM_DO_DEBUG(memset(virs, 0, sizeof(*virs)));
kfree(virs);
fail_alloc:
/*** Resource object ****************************************************/
int
-efrm_vi_resource_alloc(struct vi_resource *evq_virs,
- uint16_t vi_flags, int32_t evq_capacity,
- int32_t txq_capacity, int32_t rxq_capacity,
- uint8_t tx_q_tag, uint8_t rx_q_tag,
+efrm_vi_resource_alloc(struct efrm_client *client,
+ struct vi_resource *evq_virs,
+ unsigned vi_flags, int evq_capacity,
+ int txq_capacity, int rxq_capacity,
+ int tx_q_tag, int rx_q_tag,
struct vi_resource **virs_out,
uint32_t *out_io_mmap_bytes,
uint32_t *out_mem_mmap_bytes,
uint32_t *out_txq_capacity, uint32_t *out_rxq_capacity)
{
int rc;
- rc = efrm_vi_resource_alloc_or_free(true, evq_virs, vi_flags,
+ EFRM_ASSERT(client != NULL);
+ rc = efrm_vi_resource_alloc_or_free(client, true, evq_virs, vi_flags,
evq_capacity, txq_capacity,
rxq_capacity, tx_q_tag, rx_q_tag,
virs_out);
void efrm_vi_rm_free_flushed_resource(struct vi_resource *virs)
{
EFRM_ASSERT(virs != NULL);
- EFRM_ASSERT(atomic_read(&virs->rs.rs_ref_count) == 0);
+ EFRM_ASSERT(virs->rs.rs_ref_count == 0);
EFRM_TRACE("%s: " EFRM_RESOURCE_FMT, __FUNCTION__,
EFRM_RESOURCE_PRI_ARG(virs->rs.rs_handle));
*
* This file contains event handling for VI resource.
*
- * Copyright 2005-2007: Solarflare Communications Inc,
+ * Copyright 2005-2010: Solarflare Communications Inc,
* 9501 Jeronimo Road, Suite 250,
* Irvine, CA 92618, USA
*
#include <ci/efhw/eventq.h>
#include <ci/efrm/private.h>
#include <ci/efrm/vi_resource_private.h>
+#include <ci/efrm/efrm_nic.h>
+#include "efrm_internal.h"
+
+
+static inline int
+efrm_eventq_bytes(struct vi_resource *virs)
+{
+ return efrm_vi_rm_evq_bytes(virs);
+}
+
+
+static inline efhw_event_t *
+efrm_eventq_base(struct vi_resource *virs)
+{
+ return (efhw_event_t *) efhw_iopages_ptr(&virs->evq_hw.iobuff);
+}
+
void
-efrm_eventq_request_wakeup(struct vi_resource *virs, unsigned current_ptr,
- unsigned nic_index)
+efrm_eventq_request_wakeup(struct vi_resource *virs, unsigned current_ptr)
{
- struct efhw_nic *nic;
+ struct efhw_nic *nic = virs->rs.rs_client->nic;
int next_i;
- EFRM_ASSERT(efrm_nic_set_read(&virs->nic_set, nic_index));
- nic = efrm_nic_tablep->nic[nic_index];
- EFRM_ASSERT(nic);
next_i = ((current_ptr / sizeof(efhw_event_t)) &
(virs->evq_capacity - 1));
- efhw_nic_wakeup_request(nic, efrm_eventq_dma_addr(virs, nic_index),
- next_i,
+ efhw_nic_wakeup_request(nic, next_i,
EFRM_RESOURCE_INSTANCE(virs->rs.rs_handle));
}
EXPORT_SYMBOL(efrm_eventq_request_wakeup);
-void efrm_eventq_reset(struct vi_resource *virs, int nic_index)
+void efrm_eventq_reset(struct vi_resource *virs)
{
- struct efhw_nic *nic = efrm_nic_tablep->nic[nic_index];
+ struct efhw_nic *nic = virs->rs.rs_client->nic;
int instance = EFRM_RESOURCE_INSTANCE(virs->rs.rs_handle);
EFRM_ASSERT(virs->evq_capacity != 0);
- EFRM_ASSERT(efrm_nic_set_read(&virs->nic_set, nic_index));
/* FIXME: Protect against concurrent resets. */
efhw_nic_event_queue_disable(nic, instance, 0);
- memset(efrm_eventq_base(virs, nic_index), EFHW_CLEAR_EVENT_VALUE,
- efrm_eventq_bytes(virs, nic_index));
+ memset(efrm_eventq_base(virs), EFHW_CLEAR_EVENT_VALUE,
+ efrm_eventq_bytes(virs));
efhw_nic_event_queue_enable(nic, instance, virs->evq_capacity,
- efrm_eventq_dma_addr(virs, nic_index),
- virs->nic_info[nic_index].evq_pages.
- buf_tbl_alloc.base);
+ virs->evq_hw.buf_tbl_alloc.base,
+ /* make siena look like falcon for now */
+ instance < 64,
+ /* make dos protection enable by default */
+ 1);
EFRM_TRACE("%s: " EFRM_RESOURCE_FMT, __FUNCTION__,
EFRM_RESOURCE_PRI_ARG(virs->rs.rs_handle));
}
struct efhw_nic *nic),
void *arg)
{
+ struct efrm_nic_per_vi *cb_info;
int instance;
int bit;
EFRM_RESOURCE_ASSERT_VALID(&virs->rs, 0);
EFRM_ASSERT(virs->evq_capacity != 0);
+ EFRM_ASSERT(handler != NULL);
+
+ /* ?? TODO: Get rid of this test when client is compulsory. */
+ if (virs->rs.rs_client == NULL) {
+ EFRM_ERR("%s: no client", __FUNCTION__);
+ return -EINVAL;
+ }
+ virs->evq_callback_arg = arg;
+ virs->evq_callback_fn = handler;
instance = EFRM_RESOURCE_INSTANCE(virs->rs.rs_handle);
+ cb_info = &efrm_nic(virs->rs.rs_client->nic)->vis[instance];
/* The handler can be set only once. */
bit = test_and_set_bit(VI_RESOURCE_EVQ_STATE_CALLBACK_REGISTERED,
- &efrm_vi_manager->evq_infos[instance].evq_state);
+ &cb_info->state);
if (bit)
return -EBUSY;
-
- /* Store the details. The order is important here. */
- virs->evq_callback_arg = arg;
- virs->evq_callback_fn = handler;
+ cb_info->vi = virs;
return 0;
}
void efrm_eventq_kill_callback(struct vi_resource *virs)
{
- int nic_i, instance;
- struct efhw_nic *nic;
- struct vi_resource_evq_info *evq_info;
+ struct efrm_nic_per_vi *cb_info;
int32_t evq_state;
+ int instance;
int bit;
EFRM_RESOURCE_ASSERT_VALID(&virs->rs, 0);
EFRM_ASSERT(virs->evq_capacity != 0);
-
- /* Clean out the callback so a new one can be installed. */
- virs->evq_callback_fn = NULL;
+ EFRM_ASSERT(virs->rs.rs_client != NULL);
instance = EFRM_RESOURCE_INSTANCE(virs->rs.rs_handle);
- evq_info = &efrm_vi_manager->evq_infos[instance];
+ cb_info = &efrm_nic(virs->rs.rs_client->nic)->vis[instance];
+ cb_info->vi = NULL;
- /* Disable the event queue. */
- EFRM_FOR_EACH_NIC_IN_SET(&virs->nic_set, nic_i, nic)
- efhw_nic_event_queue_disable(nic, instance, /*timer_only */ 1);
+ /* Disable the timer. */
+ efhw_nic_event_queue_disable(virs->rs.rs_client->nic,
+ instance, /*timer_only */ 1);
/* Disable the callback. */
bit = test_and_clear_bit(VI_RESOURCE_EVQ_STATE_CALLBACK_REGISTERED,
- &evq_info->evq_state);
+ &cb_info->state);
EFRM_ASSERT(bit); /* do not call me twice! */
/* Spin until the callback is complete. */
rmb();
udelay(1);
- evq_state = evq_info->evq_state;
+ evq_state = cb_info->state;
} while ((evq_state & VI_RESOURCE_EVQ_STATE(BUSY)));
+
+ virs->evq_callback_fn = NULL;
}
EXPORT_SYMBOL(efrm_eventq_kill_callback);
efrm_eventq_do_callback(struct efhw_nic *nic, unsigned instance,
bool is_timeout)
{
+ struct efrm_nic *rnic = efrm_nic(nic);
void (*handler) (void *, int is_timeout, struct efhw_nic *nic);
void *arg;
- struct vi_resource_evq_info *evq_info;
+ struct efrm_nic_per_vi *cb_info;
int32_t evq_state;
int32_t new_evq_state;
struct vi_resource *virs;
int bit;
- EFRM_TRACE("%s: q=%d %s", __FUNCTION__, instance,
- is_timeout ? "timeout" : "wakeup");
EFRM_ASSERT(efrm_vi_manager);
- evq_info = &efrm_vi_manager->evq_infos[instance];
+ cb_info = &rnic->vis[instance];
/* Set the BUSY bit and clear WAKEUP_PENDING. Do this
* before waking up the sleeper to avoid races. */
while (1) {
- evq_state = evq_info->evq_state;
+ evq_state = cb_info->state;
new_evq_state = evq_state;
if ((evq_state & VI_RESOURCE_EVQ_STATE(BUSY)) != 0) {
if (evq_state & VI_RESOURCE_EVQ_STATE(CALLBACK_REGISTERED)) {
new_evq_state |= VI_RESOURCE_EVQ_STATE(BUSY);
- if (cmpxchg(&evq_info->evq_state, evq_state,
- new_evq_state) == evq_state) {
- virs = evq_info->evq_virs;
+ virs = cb_info->vi;
+ if (cmpxchg(&cb_info->state, evq_state,
+ new_evq_state) == evq_state)
break;
- }
-
} else {
/* Just update the state if necessary. */
if (new_evq_state == evq_state ||
- cmpxchg(&evq_info->evq_state, evq_state,
+ cmpxchg(&cb_info->state, evq_state,
new_evq_state) == evq_state)
return;
}
-
- udelay(1);
}
- /* Call the callback if any. */
- if (evq_state & VI_RESOURCE_EVQ_STATE(CALLBACK_REGISTERED)) {
- /* Retrieve the callback fn. */
+ if (virs) {
handler = virs->evq_callback_fn;
arg = virs->evq_callback_arg;
- if (handler != NULL) /* avoid races */
- handler(arg, is_timeout, nic);
+ EFRM_ASSERT(handler != NULL);
+ handler(arg, is_timeout, nic);
}
/* Clear the BUSY bit. */
bit =
test_and_clear_bit(VI_RESOURCE_EVQ_STATE_BUSY,
- &evq_info->evq_state);
+ &cb_info->state);
if (!bit) {
EFRM_ERR("%s:%d: evq_state corrupted!",
__FUNCTION__, __LINE__);
*
* This file contains DMA queue flushing of VI resources.
*
- * Copyright 2005-2007: Solarflare Communications Inc,
+ * Copyright 2005-2010: Solarflare Communications Inc,
* 9501 Jeronimo Road, Suite 250,
* Irvine, CA 92618, USA
*
#include <ci/efrm/sysdep.h>
#include <ci/efrm/buffer_table.h>
#include <ci/efrm/vi_resource_private.h>
+#include "efrm_internal.h"
+
#if EFRM_VI_USE_WORKQUEUE
/* can fail as workitem can already be scheuled -- ignore failure */
static const int flush_fifo_hwm = 8 /* TODO should be a HW specific const */ ;
static void
-efrm_vi_resource_rx_flush_done(struct vi_resource *virs, int nic_i,
- bool *completed)
+efrm_vi_resource_rx_flush_done(struct vi_resource *virs, bool *completed)
{
/* We should only get a flush event if there is a flush
* outstanding. */
- EFRM_ASSERT(efrm_nic_set_read
- (&virs->rx_flush_outstanding_nic_set, nic_i));
+ EFRM_ASSERT(virs->rx_flush_outstanding);
- efrm_nic_set_write(&virs->rx_flush_outstanding_nic_set, nic_i, false);
- efrm_nic_set_write(&virs->rx_flush_nic_set, nic_i, false);
+ virs->rx_flush_outstanding = 0;
+ virs->rx_flushing = 0;
- if (efrm_nic_set_is_all_clear(&virs->rx_flush_outstanding_nic_set)) {
- list_del(&virs->rx_flush_link);
- efrm_vi_manager->rx_flush_outstanding_count--;
+ list_del(&virs->rx_flush_link);
+ efrm_vi_manager->rx_flush_outstanding_count--;
- if (efrm_nic_set_is_all_clear(&virs->tx_flush_nic_set)) {
- list_add_tail(&virs->rx_flush_link,
- &efrm_vi_manager->close_pending);
- *completed = 1;
- }
+ if (virs->tx_flushing == 0) {
+ list_add_tail(&virs->rx_flush_link,
+ &efrm_vi_manager->close_pending);
+ *completed = 1;
}
}
static void
-efrm_vi_resource_tx_flush_done(struct vi_resource *virs, int nic_i,
- bool *completed)
+efrm_vi_resource_tx_flush_done(struct vi_resource *virs, bool *completed)
{
/* We should only get a flush event if there is a flush
* outstanding. */
- EFRM_ASSERT(efrm_nic_set_read(&virs->tx_flush_nic_set, nic_i));
+ EFRM_ASSERT(virs->tx_flushing);
- efrm_nic_set_write(&virs->tx_flush_nic_set, nic_i, false);
+ virs->tx_flushing = 0;
- if (efrm_nic_set_is_all_clear(&virs->tx_flush_nic_set)) {
- list_del(&virs->tx_flush_link);
+ list_del(&virs->tx_flush_link);
- if (efrm_nic_set_is_all_clear(&virs->rx_flush_nic_set)) {
- list_add_tail(&virs->rx_flush_link,
- &efrm_vi_manager->close_pending);
- *completed = 1;
- }
+ if (virs->rx_flushing == 0) {
+ list_add_tail(&virs->rx_flush_link,
+ &efrm_vi_manager->close_pending);
+ *completed = 1;
}
}
static void
efrm_vi_resource_issue_rx_flush(struct vi_resource *virs, bool *completed)
{
- struct efhw_nic *nic;
- int nic_i;
+ struct efhw_nic *nic = virs->rs.rs_client->nic;
int instance;
int rc;
list_add_tail(&virs->rx_flush_link,
&efrm_vi_manager->rx_flush_outstanding_list);
- virs->rx_flush_outstanding_nic_set = virs->rx_flush_nic_set;
+ virs->rx_flush_outstanding = virs->rx_flushing;
efrm_vi_manager->rx_flush_outstanding_count++;
- EFRM_FOR_EACH_NIC_IN_SET(&virs->nic_set, nic_i, nic) {
- EFRM_TRACE("%s: rx queue %d flush requested for nic %d",
- __FUNCTION__, instance, nic->index);
- rc = efhw_nic_flush_rx_dma_channel(nic, instance);
- if (rc == -EAGAIN)
- efrm_vi_resource_rx_flush_done(virs, nic_i, completed);
- }
+ EFRM_TRACE("%s: rx queue %d flush requested for nic %d",
+ __FUNCTION__, instance, nic->index);
+ rc = efhw_nic_flush_rx_dma_channel(nic, instance);
}
static void
efrm_vi_resource_issue_tx_flush(struct vi_resource *virs, bool *completed)
{
- struct efhw_nic *nic;
- int nic_i;
+ struct efhw_nic *nic = virs->rs.rs_client->nic;
int instance;
int rc;
list_add_tail(&virs->tx_flush_link,
&efrm_vi_manager->tx_flush_outstanding_list);
- EFRM_FOR_EACH_NIC_IN_SET(&virs->nic_set, nic_i, nic) {
- EFRM_TRACE("%s: tx queue %d flush requested for nic %d",
- __FUNCTION__, instance, nic->index);
- rc = efhw_nic_flush_tx_dma_channel(nic, instance);
- if (rc == -EAGAIN)
- efrm_vi_resource_tx_flush_done(virs, nic_i, completed);
- }
+ EFRM_TRACE("%s: tx queue %d flush requested for nic %d",
+ __FUNCTION__, instance, nic->index);
+ rc = efhw_nic_flush_tx_dma_channel(nic, instance);
+ if (rc == -EAGAIN)
+ efrm_vi_resource_tx_flush_done(virs, completed);
}
-static void efrm_vi_resource_process_waiting_flushes(bool *completed)
+static void efrm_vi_resource_process_flushes(bool *completed)
{
struct vi_resource *virs;
}
}
-#if BUG7916_WORKAROUND || BUG5302_WORKAROUND
-static void
-efrm_vi_resource_flush_retry_vi(struct vi_resource *virs,
- int64_t time_now, bool *completed)
-{
- struct efhw_nic *nic;
- int nic_i;
- int instance;
-
- instance = EFRM_RESOURCE_INSTANCE(virs->rs.rs_handle);
-
- virs->flush_count++;
- virs->flush_time = time_now;
-
-#if BUG7916_WORKAROUND
- if (!efrm_nic_set_is_all_clear(&virs->rx_flush_outstanding_nic_set)) {
- EFRM_TRACE("%s: Retrying RX flush on instance %d",
- __FUNCTION__, instance);
-
- list_del(&virs->rx_flush_link);
- efrm_vi_manager->rx_flush_outstanding_count--;
- efrm_vi_resource_issue_rx_flush(virs, completed);
- efrm_vi_resource_process_waiting_flushes(completed);
- }
-#endif
-
-#if BUG5302_WORKAROUND
- if (!efrm_nic_set_is_all_clear(&virs->tx_flush_nic_set)) {
- if (virs->flush_count > 5) {
- EFRM_TRACE("%s: VI resource stuck flush pending "
- "(instance=%d, count=%d)",
- __FUNCTION__, instance, virs->flush_count);
- EFRM_FOR_EACH_NIC_IN_SET(&virs->tx_flush_nic_set,
- nic_i, nic) {
- falcon_clobber_tx_dma_ptrs(nic, instance);
- }
- } else {
- EFRM_TRACE("%s: Retrying TX flush on instance %d",
- __FUNCTION__, instance);
- }
-
- list_del(&virs->tx_flush_link);
- efrm_vi_resource_issue_tx_flush(virs, completed);
- }
-#endif
-}
-#endif
-
-int efrm_vi_resource_flush_retry(struct vi_resource *virs)
-{
-#if BUG7916_WORKAROUND || BUG5302_WORKAROUND
- irq_flags_t lock_flags;
- bool completed = false;
-
- if (efrm_nic_set_is_all_clear(&virs->rx_flush_nic_set) &&
- efrm_nic_set_is_all_clear(&virs->tx_flush_nic_set))
- return -EALREADY;
-
- spin_lock_irqsave(&efrm_vi_manager->rm.rm_lock, lock_flags);
- efrm_vi_resource_flush_retry_vi(virs, get_jiffies_64(), &completed);
- spin_unlock_irqrestore(&efrm_vi_manager->rm.rm_lock, lock_flags);
-
- if (completed)
- EFRM_VI_RM_DELAYED_FREE(efrm_vi_manager);
-#endif
-
- return 0;
-}
-EXPORT_SYMBOL(efrm_vi_resource_flush_retry);
-
-#if BUG7916_WORKAROUND || BUG5302_WORKAROUND
-/* resource manager lock should be taken before this call */
-static void efrm_vi_handle_flush_loss(bool *completed)
-{
- struct list_head *pos, *temp;
- struct vi_resource *virs;
- int64_t time_now, time_pending;
-
- /* It's possible we miss flushes - the list is sorted in order we
- * generate flushes, see if any are very old. It's also possible
- * that we decide an endpoint is flushed even though we've not
- * received all the flush events. We *should * mark as
- * completed, reclaim and loop again. ??
- * THIS NEEDS BACKPORTING FROM THE FALCON branch
- */
- time_now = get_jiffies_64();
-
-#if BUG7916_WORKAROUND
- list_for_each_safe(pos, temp,
- &efrm_vi_manager->rx_flush_outstanding_list) {
- virs = container_of(pos, struct vi_resource, rx_flush_link);
-
- time_pending = time_now - virs->flush_time;
-
- /* List entries are held in reverse chronological order. Only
- * process the old ones. */
- if (time_pending <= 0x100000000LL)
- break;
-
- efrm_vi_resource_flush_retry_vi(virs, time_now, completed);
- }
-#endif
-
-#if BUG5302_WORKAROUND
- list_for_each_safe(pos, temp,
- &efrm_vi_manager->tx_flush_outstanding_list) {
- virs = container_of(pos, struct vi_resource, tx_flush_link);
-
- time_pending = time_now - virs->flush_time;
-
- /* List entries are held in reverse chronological order.
- * Only process the old ones. */
- if (time_pending <= 0x100000000LL)
- break;
-
- efrm_vi_resource_flush_retry_vi(virs, time_now, completed);
- }
-#endif
-}
-#endif
-
void
efrm_vi_register_flush_callback(struct vi_resource *virs,
void (*handler)(void *), void *arg)
}
EXPORT_SYMBOL(efrm_vi_register_flush_callback);
-int efrm_pt_flush(struct vi_resource *virs)
+void efrm_pt_flush(struct vi_resource *virs)
{
int instance;
irq_flags_t lock_flags;
instance = EFRM_RESOURCE_INSTANCE(virs->rs.rs_handle);
- EFRM_ASSERT(efrm_nic_set_is_all_clear(&virs->rx_flush_nic_set));
- EFRM_ASSERT(efrm_nic_set_is_all_clear
- (&virs->rx_flush_outstanding_nic_set));
- EFRM_ASSERT(efrm_nic_set_is_all_clear(&virs->tx_flush_nic_set));
+ EFRM_ASSERT(virs->rx_flushing == 0);
+ EFRM_ASSERT(virs->rx_flush_outstanding == 0);
+ EFRM_ASSERT(virs->tx_flushing == 0);
EFRM_TRACE("%s: " EFRM_RESOURCE_FMT " EVQ=%d TXQ=%d RXQ=%d",
__FUNCTION__, EFRM_RESOURCE_PRI_ARG(virs->rs.rs_handle),
spin_lock_irqsave(&efrm_vi_manager->rm.rm_lock, lock_flags);
if (virs->dmaq_capacity[EFRM_VI_RM_DMA_QUEUE_RX] != 0)
- virs->rx_flush_nic_set = virs->nic_set;
+ virs->rx_flushing = 1;
if (virs->dmaq_capacity[EFRM_VI_RM_DMA_QUEUE_TX] != 0)
- virs->tx_flush_nic_set = virs->nic_set;
+ virs->tx_flushing = 1;
/* Clean up immediately if there are no flushes. */
- if (efrm_nic_set_is_all_clear(&virs->rx_flush_nic_set) &&
- efrm_nic_set_is_all_clear(&virs->tx_flush_nic_set)) {
+ if (virs->rx_flushing == 0 && virs->tx_flushing == 0) {
list_add_tail(&virs->rx_flush_link,
&efrm_vi_manager->close_pending);
completed = true;
}
/* Issue the RX flush if possible or queue it for later. */
- if (!efrm_nic_set_is_all_clear(&virs->rx_flush_nic_set)) {
-#if BUG7916_WORKAROUND || BUG5302_WORKAROUND
- if (efrm_vi_manager->rx_flush_outstanding_count >=
- flush_fifo_hwm)
- efrm_vi_handle_flush_loss(&completed);
-#endif
+ if (virs->rx_flushing) {
if (efrm_vi_manager->rx_flush_outstanding_count >=
flush_fifo_hwm) {
list_add_tail(&virs->rx_flush_link,
/* Issue the TX flush. There's no limit to the number of
* outstanding TX flushes. */
- if (!efrm_nic_set_is_all_clear(&virs->tx_flush_nic_set))
+ if (virs->tx_flushing)
efrm_vi_resource_issue_tx_flush(virs, &completed);
virs->flush_time = get_jiffies_64();
if (completed)
EFRM_VI_RM_DELAYED_FREE(efrm_vi_manager);
-
- return 0;
}
EXPORT_SYMBOL(efrm_pt_flush);
static void
efrm_handle_rx_dmaq_flushed(struct efhw_nic *flush_nic, int instance,
- bool *completed)
+ bool *completed, int failed)
{
struct list_head *pos, *temp;
struct vi_resource *virs;
virs = container_of(pos, struct vi_resource, rx_flush_link);
if (instance == EFRM_RESOURCE_INSTANCE(virs->rs.rs_handle)) {
- efrm_vi_resource_rx_flush_done(virs,
- flush_nic->index,
- completed);
- efrm_vi_resource_process_waiting_flushes(completed);
+ if (failed) {
+ struct efhw_nic *nic = virs->rs.rs_client->nic;
+ int rc = efhw_nic_flush_rx_dma_channel(nic,
+ instance);
+ EFRM_ASSERT(rc == 0);
+ (void) rc; /* kill compiler warning */
+ *completed = false;
+ } else {
+ efrm_vi_resource_rx_flush_done(virs, completed);
+ efrm_vi_resource_process_flushes(completed);
+ }
return;
}
}
virs = container_of(pos, struct vi_resource, tx_flush_link);
if (instance == EFRM_RESOURCE_INSTANCE(virs->rs.rs_handle)) {
- efrm_vi_resource_tx_flush_done(virs,
- flush_nic->index,
- completed);
+ efrm_vi_resource_tx_flush_done(virs, completed);
return;
}
}
void
efrm_handle_dmaq_flushed(struct efhw_nic *flush_nic, unsigned instance,
- int rx_flush)
+ int rx_flush, int failed)
{
irq_flags_t lock_flags;
bool completed = false;
- EFRM_TRACE("%s: nic_i=%d instance=%d rx_flush=%d", __FUNCTION__,
- flush_nic->index, instance, rx_flush);
+ EFRM_TRACE("%s: nic_i=%d instance=%d rx_flush=%d failed=%d",
+ __FUNCTION__, flush_nic->index, instance, rx_flush,
+ failed);
spin_lock_irqsave(&efrm_vi_manager->rm.rm_lock, lock_flags);
if (rx_flush)
- efrm_handle_rx_dmaq_flushed(flush_nic, instance, &completed);
+ efrm_handle_rx_dmaq_flushed(flush_nic, instance, &completed,
+ failed);
else
efrm_handle_tx_dmaq_flushed(flush_nic, instance, &completed);
-#if BUG7916_WORKAROUND || BUG5302_WORKAROUND
- efrm_vi_handle_flush_loss(&completed);
-#endif
-
spin_unlock_irqrestore(&efrm_vi_manager->rm.rm_lock, lock_flags);
if (completed)
static void
efrm_vi_rm_reinit_dmaqs(struct vi_resource *virs)
{
- struct efhw_nic *nic;
- int nic_i;
-
- EFRM_FOR_EACH_NIC_IN_SET(&virs->nic_set, nic_i, nic) {
- if (virs->dmaq_capacity[EFRM_VI_RM_DMA_QUEUE_TX] != 0)
- efrm_vi_rm_init_dmaq(virs, EFRM_VI_RM_DMA_QUEUE_TX,
- nic);
- if (virs->dmaq_capacity[EFRM_VI_RM_DMA_QUEUE_RX])
- efrm_vi_rm_init_dmaq(virs, EFRM_VI_RM_DMA_QUEUE_RX,
- nic);
- }
+ struct efhw_nic *nic = virs->rs.rs_client->nic;
+
+ if (virs->dmaq_capacity[EFRM_VI_RM_DMA_QUEUE_TX] != 0)
+ efrm_vi_rm_init_dmaq(virs, EFRM_VI_RM_DMA_QUEUE_TX, nic);
+ if (virs->dmaq_capacity[EFRM_VI_RM_DMA_QUEUE_RX])
+ efrm_vi_rm_init_dmaq(virs, EFRM_VI_RM_DMA_QUEUE_RX, nic);
}
/* free any PT endpoints whose flush has now complete */
void efrm_vi_rm_salvage_flushed_vis(void)
{
-#if BUG7916_WORKAROUND || BUG5302_WORKAROUND
- irq_flags_t lock_flags;
- bool completed;
-
- spin_lock_irqsave(&efrm_vi_manager->rm.rm_lock, lock_flags);
- efrm_vi_handle_flush_loss(&completed);
- spin_unlock_irqrestore(&efrm_vi_manager->rm.rm_lock, lock_flags);
-#endif
-
efrm_vi_rm_delayed_free(&efrm_vi_manager->work_item);
}
}
EXPORT_SYMBOL(efrm_vi_resource_free);
+
+void efrm_vi_resource_release(struct vi_resource *virs)
+{
+ if (__efrm_resource_release(&virs->rs))
+ efrm_vi_resource_free(virs);
+}
+EXPORT_SYMBOL(efrm_vi_resource_release);
+
/*
* vi: sw=8:ai:aw
*/
*
* This file contains the VI resource manager.
*
- * Copyright 2005-2007: Solarflare Communications Inc,
+ * Copyright 2005-2010: Solarflare Communications Inc,
* 9501 Jeronimo Road, Suite 250,
* Irvine, CA 92618, USA
*
#include <ci/efhw/falcon.h>
#include <ci/efrm/private.h>
#include <ci/efrm/vi_resource_private.h>
+#include "efrm_internal.h"
+
int efrm_pt_pace(struct vi_resource *virs, unsigned int val)
{
-#if defined(__CI_HARDWARE_CONFIG_FALCON__)
- int instance, nic_i;
- struct efhw_nic *nic;
+ struct efhw_nic *nic = virs->rs.rs_client->nic;
+ int instance;
EFRM_RESOURCE_ASSERT_VALID(&virs->rs, 0);
instance = EFRM_RESOURCE_INSTANCE(virs->rs.rs_handle);
-
- EFRM_FOR_EACH_NIC_IN_SET(&virs->nic_set, nic_i, nic)
- falcon_nic_pace(nic, instance, val);
-
+ falcon_nic_pace(nic, instance, val);
EFRM_TRACE("%s[%d]=%d DONE", __FUNCTION__, instance, val);
return 0;
-#else
- return -EOPNOTSUPP;
-#endif
}
EXPORT_SYMBOL(efrm_pt_pace);
struct list_head *pos, *temp;
struct list_head flush_pending;
irq_flags_t lock_flags;
- int rc, i, n_evqs;
+ int rc;
unsigned dmaq_min, dmaq_lim;
EFRM_ASSERT(rm_in_out);
if (rc < 0)
goto fail_with_int_id_pool;
- n_evqs = max(efrm_vi_manager->with_timer_limit,
- efrm_vi_manager->with_interrupt_limit);
- rc = -ENOMEM;
- efrm_vi_manager->evq_infos =
- vmalloc(n_evqs * sizeof(struct vi_resource_evq_info));
- if (efrm_vi_manager->evq_infos == NULL)
- goto fail_alloc_evq_infos;
-
- for (i = 0; i < n_evqs; ++i) {
- efrm_vi_manager->evq_infos[i].evq_state = 0;
- efrm_vi_manager->evq_infos[i].evq_virs = NULL;
- }
-
INIT_LIST_HEAD(&efrm_vi_manager->rx_flush_waiting_list);
INIT_LIST_HEAD(&efrm_vi_manager->rx_flush_outstanding_list);
INIT_LIST_HEAD(&efrm_vi_manager->tx_flush_outstanding_list);
* efrm_resource_manager_dtor calls the vi_rm_dtor which ends up in
* this function. */
rc = efrm_resource_manager_ctor(&efrm_vi_manager->rm, efrm_vi_rm_dtor,
- "VI", EFRM_RESOURCE_VI, 0);
+ "VI", EFRM_RESOURCE_VI);
if (rc < 0)
goto fail_rm_ctor;
/* Abort outstanding flushes. Note, a VI resource can be on more
* than one of these lists. We handle this by starting with the TX
* list and then append VIs to this list if they aren't on the TX
- * list already. A VI is on the TX flush list if tx_flush_nic_set
+ * list already. A VI is on the TX flush list if tx_flushing
* is not empty. */
spin_lock_irqsave(&efrm_vi_manager->rm.rm_lock, lock_flags);
virs = container_of(pos, struct vi_resource, rx_flush_link);
list_del(&virs->rx_flush_link);
- if (efrm_nic_set_is_all_clear(&virs->tx_flush_nic_set))
+ if (virs->tx_flushing == 0)
list_add_tail(&virs->tx_flush_link, &flush_pending);
}
virs = container_of(pos, struct vi_resource, rx_flush_link);
list_del(&virs->rx_flush_link);
- if (efrm_nic_set_is_all_clear(&virs->tx_flush_nic_set))
+ if (virs->tx_flushing == 0)
list_add_tail(&virs->tx_flush_link, &flush_pending);
}
" with flush pending [Tx=0x%x, Rx=0x%x, RxO=0x%x]",
__FUNCTION__,
EFRM_RESOURCE_PRI_ARG(virs->rs.rs_handle),
- virs->tx_flush_nic_set.nics,
- virs->rx_flush_nic_set.nics,
- virs->rx_flush_outstanding_nic_set.nics);
+ virs->tx_flushing,
+ virs->rx_flushing,
+ virs->rx_flush_outstanding);
efrm_vi_rm_free_flushed_resource(virs);
}
fail_create_workqueue:
#endif
EFRM_ASSERT(list_empty(&efrm_vi_manager->close_pending));
-
- n_evqs = max(efrm_vi_manager->with_timer_limit,
- efrm_vi_manager->with_interrupt_limit);
- vfree(efrm_vi_manager->evq_infos);
-fail_alloc_evq_infos:
-
kfifo_vfree(efrm_vi_manager->instances_with_interrupt);
fail_with_int_id_pool:
projects / people / royger / linux-2.6.18-xen.git / commitdiff