target: Unify QOM style

Enforce the style described by commit 067109a11c ("docs/devel:
mention the spacing requirement for QOM"):

  The first declaration of a storage or class structure should
  always be the parent and leave a visual space between that
  declaration and the new code. It is also useful to separate
  backing for properties (options driven by the user) and internal
  state to make navigation easier.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Zhao Liu <zhao1.liu@intel.com>
Message-Id: <20231013140116.255-2-philmd@linaro.org>

diff --git a/target/alpha/cpu-qom.h b/target/alpha/cpu-qom.h
index 1f200724b67e9e5d3e52632033bcab802dbdfda7..c5fbd8f11a24dad74726806be60f700ffb6434c9 100644 (file)
--- a/target/alpha/cpu-qom.h
+++ b/target/alpha/cpu-qom.h
@@ -35,9 +35,7 @@ OBJECT_DECLARE_CPU_TYPE(AlphaCPU, AlphaCPUClass, ALPHA_CPU)
  * An Alpha CPU model.
  */
 struct AlphaCPUClass {
-    /*< private >*/
     CPUClass parent_class;
-    /*< public >*/
 
     DeviceRealize parent_realize;
     DeviceReset parent_reset;

diff --git a/target/alpha/cpu.h b/target/alpha/cpu.h
index e2a467ec1728ef0b30c86684dc1440c8eb449cb2..c8d97ac27af6b95a1f6a7a0b8182b1b3513cc917 100644 (file)
--- a/target/alpha/cpu.h
+++ b/target/alpha/cpu.h
@@ -259,9 +259,7 @@ typedef struct CPUArchState {
  * An Alpha CPU.
  */
 struct ArchCPU {
-    /*< private >*/
     CPUState parent_obj;
-    /*< public >*/
 
     CPUAlphaState env;
 

diff --git a/target/arm/cpu-qom.h b/target/arm/cpu-qom.h
index d06c08a734ed393f900e5e25d376b05653262cdd..153865d1bbdcdb67de6dad71b6ffad7f3ebdbf7d 100644 (file)
--- a/target/arm/cpu-qom.h
+++ b/target/arm/cpu-qom.h
@@ -46,9 +46,7 @@ void aarch64_cpu_register(const ARMCPUInfo *info);
  * An ARM CPU model.
  */
 struct ARMCPUClass {
-    /*< private >*/
     CPUClass parent_class;
-    /*< public >*/
 
     const ARMCPUInfo *info;
     DeviceRealize parent_realize;
@@ -62,9 +60,7 @@ DECLARE_CLASS_CHECKERS(AArch64CPUClass, AARCH64_CPU,
                        TYPE_AARCH64_CPU)
 
 struct AArch64CPUClass {
-    /*< private >*/
     ARMCPUClass parent_class;
-    /*< public >*/
 };
 
 void register_cp_regs_for_features(ARMCPU *cpu);

diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index d51dfe48db0f1542eddf49d301b3ea7a9d7054a6..2f7ab22169f5bd73022a16e1d34dce682ed80bfe 100644 (file)
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -852,9 +852,7 @@ typedef struct {
  * An ARM CPU core.
  */
 struct ArchCPU {
-    /*< private >*/
     CPUState parent_obj;
-    /*< public >*/
 
     CPUARMState env;
 

diff --git a/target/avr/cpu-qom.h b/target/avr/cpu-qom.h
index 01ea5f160b6e29dda5c0ce7f1f3c26c99edd53e0..d89be01e0fa55d134575fedb78f978c297896612 100644 (file)
--- a/target/avr/cpu-qom.h
+++ b/target/avr/cpu-qom.h
@@ -36,9 +36,8 @@ OBJECT_DECLARE_CPU_TYPE(AVRCPU, AVRCPUClass, AVR_CPU)
  *  A AVR CPU model.
  */
 struct AVRCPUClass {
-    /*< private >*/
     CPUClass parent_class;
-    /*< public >*/
+
     DeviceRealize parent_realize;
     ResettablePhases parent_phases;
 };

diff --git a/target/avr/cpu.h b/target/avr/cpu.h
index 4ce22d8e4f176aa58ed03520da6685d183370cee..f8b065ed793e914fc63c327676697922002a9093 100644 (file)
--- a/target/avr/cpu.h
+++ b/target/avr/cpu.h
@@ -144,9 +144,7 @@ typedef struct CPUArchState {
  *  A AVR CPU.
  */
 struct ArchCPU {
-    /*< private >*/
     CPUState parent_obj;
-    /*< public >*/
 
     CPUAVRState env;
 };

diff --git a/target/cris/cpu-qom.h b/target/cris/cpu-qom.h
index 431a1d536a96c288525067e586b4b35c3ae2b439..c2fee242f4c6a4d118ebf8023eef26f54b1df5bd 100644 (file)
--- a/target/cris/cpu-qom.h
+++ b/target/cris/cpu-qom.h
@@ -36,9 +36,7 @@ OBJECT_DECLARE_CPU_TYPE(CRISCPU, CRISCPUClass, CRIS_CPU)
  * A CRIS CPU model.
  */
 struct CRISCPUClass {
-    /*< private >*/
     CPUClass parent_class;
-    /*< public >*/
 
     DeviceRealize parent_realize;
     ResettablePhases parent_phases;

diff --git a/target/cris/cpu.h b/target/cris/cpu.h
index 676b8e93ca89dad7cd5632f2a1dc324a67d5d45c..6aa445348f0f50fa5212cdd99741145e8fa7d076 100644 (file)
--- a/target/cris/cpu.h
+++ b/target/cris/cpu.h
@@ -174,9 +174,7 @@ typedef struct CPUArchState {
  * A CRIS CPU.
  */
 struct ArchCPU {
-    /*< private >*/
     CPUState parent_obj;
-    /*< public >*/
 
     CPUCRISState env;
 };

diff --git a/target/hexagon/cpu.h b/target/hexagon/cpu.h
index 10cd1efd57f8f9b6316cdf7130a8da4c49522710..035ac4fb6d65e97e0462f46e3894ef9c2013516b 100644 (file)
--- a/target/hexagon/cpu.h
+++ b/target/hexagon/cpu.h
@@ -130,17 +130,14 @@ typedef struct CPUArchState {
 OBJECT_DECLARE_CPU_TYPE(HexagonCPU, HexagonCPUClass, HEXAGON_CPU)
 
 typedef struct HexagonCPUClass {
-    /*< private >*/
     CPUClass parent_class;
-    /*< public >*/
+
     DeviceRealize parent_realize;
     ResettablePhases parent_phases;
 } HexagonCPUClass;
 
 struct ArchCPU {
-    /*< private >*/
     CPUState parent_obj;
-    /*< public >*/
 
     CPUHexagonState env;
 

diff --git a/target/hppa/cpu-qom.h b/target/hppa/cpu-qom.h
index 4a85ebf5e083199a7cf4afe25ce15606a182afc8..cabd3b681e7e67d44aceaf11d02684a606752f82 100644 (file)
--- a/target/hppa/cpu-qom.h
+++ b/target/hppa/cpu-qom.h
@@ -36,9 +36,7 @@ OBJECT_DECLARE_CPU_TYPE(HPPACPU, HPPACPUClass, HPPA_CPU)
  * An HPPA CPU model.
  */
 struct HPPACPUClass {
-    /*< private >*/
     CPUClass parent_class;
-    /*< public >*/
 
     DeviceRealize parent_realize;
     DeviceReset parent_reset;

diff --git a/target/hppa/cpu.h b/target/hppa/cpu.h
index 144794d08907051028e52556caae5a5e2a089458..b39bae00d360ab03fffc4c565574a16e3bc0d130 100644 (file)
--- a/target/hppa/cpu.h
+++ b/target/hppa/cpu.h
@@ -247,9 +247,7 @@ typedef struct CPUArchState {
  * An HPPA CPU.
  */
 struct ArchCPU {
-    /*< private >*/
     CPUState parent_obj;
-    /*< public >*/
 
     CPUHPPAState env;
     QEMUTimer *alarm_timer;

diff --git a/target/i386/cpu-qom.h b/target/i386/cpu-qom.h
index 2350f4ae6098ec4b044ad1477467efe9470d6ec4..58145717ef14d9f0690691a96f47c2bbc233611f 100644 (file)
--- a/target/i386/cpu-qom.h
+++ b/target/i386/cpu-qom.h
@@ -47,9 +47,7 @@ typedef struct X86CPUModel X86CPUModel;
  * An x86 CPU model or family.
  */
 struct X86CPUClass {
-    /*< private >*/
     CPUClass parent_class;
-    /*< public >*/
 
     /* CPU definition, automatically loaded by instance_init if not NULL.
      * Should be eventually replaced by subclass-specific property defaults.

diff --git a/target/i386/cpu.h b/target/i386/cpu.h
index 471e71dbc5eb0dfa088780cf69e3ff1c7fe1da3e..096f85483eb221aafadeb84f542167708b1eee62 100644 (file)
--- a/target/i386/cpu.h
+++ b/target/i386/cpu.h
@@ -1897,9 +1897,7 @@ struct kvm_msrs;
  * An x86 CPU.
  */
 struct ArchCPU {
-    /*< private >*/
     CPUState parent_obj;
-    /*< public >*/
 
     CPUX86State env;
     VMChangeStateEntry *vmsentry;

diff --git a/target/loongarch/cpu.h b/target/loongarch/cpu.h
index 9d0f79f814c6b98b7e49f263a035a3290f21578c..555ea1f8d9d9e7d9ad035a26f47efbbc50e32cdf 100644 (file)
--- a/target/loongarch/cpu.h
+++ b/target/loongarch/cpu.h
@@ -371,9 +371,7 @@ typedef struct CPUArchState {
  * A LoongArch CPU.
  */
 struct ArchCPU {
-    /*< private >*/
     CPUState parent_obj;
-    /*< public >*/
 
     CPULoongArchState env;
     QEMUTimer timer;
@@ -398,9 +396,7 @@ OBJECT_DECLARE_CPU_TYPE(LoongArchCPU, LoongArchCPUClass,
  * A LoongArch CPU model.
  */
 struct LoongArchCPUClass {
-    /*< private >*/
     CPUClass parent_class;
-    /*< public >*/
 
     DeviceRealize parent_realize;
     ResettablePhases parent_phases;

diff --git a/target/m68k/cpu-qom.h b/target/m68k/cpu-qom.h
index 0ec7750a926b48b6c2f7fe5e8ed2a5c9329286d0..13d94c9fe36689e90486bfbda6bbb8aef5835450 100644 (file)
--- a/target/m68k/cpu-qom.h
+++ b/target/m68k/cpu-qom.h
@@ -35,9 +35,7 @@ OBJECT_DECLARE_CPU_TYPE(M68kCPU, M68kCPUClass, M68K_CPU)
  * A Motorola 68k CPU model.
  */
 struct M68kCPUClass {
-    /*< private >*/
     CPUClass parent_class;
-    /*< public >*/
 
     DeviceRealize parent_realize;
     ResettablePhases parent_phases;

diff --git a/target/m68k/cpu.h b/target/m68k/cpu.h
index 20afb0c94d9a203ab2e9f286c3316eb499a32c3f..9ea18028ad42889b0eedc8c46b6dfeb761430184 100644 (file)
--- a/target/m68k/cpu.h
+++ b/target/m68k/cpu.h
@@ -164,9 +164,7 @@ typedef struct CPUArchState {
  * A Motorola 68k CPU.
  */
 struct ArchCPU {
-    /*< private >*/
     CPUState parent_obj;
-    /*< public >*/
 
     CPUM68KState env;
 };

diff --git a/target/microblaze/cpu-qom.h b/target/microblaze/cpu-qom.h
index cda9220fa99f76c913ef19a37f5fcb40499cd81c..2a734e644d53bd220f3c93344a49d0984e904628 100644 (file)
--- a/target/microblaze/cpu-qom.h
+++ b/target/microblaze/cpu-qom.h
@@ -35,9 +35,7 @@ OBJECT_DECLARE_CPU_TYPE(MicroBlazeCPU, MicroBlazeCPUClass, MICROBLAZE_CPU)
  * A MicroBlaze CPU model.
  */
 struct MicroBlazeCPUClass {
-    /*< private >*/
     CPUClass parent_class;
-    /*< public >*/
 
     DeviceRealize parent_realize;
     ResettablePhases parent_phases;

diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h
index e43c49d4af8ac9ab539241ae9d54de26ca82b6cc..e8000237d877c787bef3c2a5917fd8bc2c613a68 100644 (file)
--- a/target/microblaze/cpu.h
+++ b/target/microblaze/cpu.h
@@ -343,9 +343,7 @@ typedef struct {
  * A MicroBlaze CPU.
  */
 struct ArchCPU {
-    /*< private >*/
     CPUState parent_obj;
-    /*< public >*/
 
     CPUMBState env;
 

diff --git a/target/mips/cpu-qom.h b/target/mips/cpu-qom.h
index 0dffab453b244865385a763985255819a382ea87..c70b4a34be2758c61aed7521537531a342a49857 100644 (file)
--- a/target/mips/cpu-qom.h
+++ b/target/mips/cpu-qom.h
@@ -39,9 +39,7 @@ OBJECT_DECLARE_CPU_TYPE(MIPSCPU, MIPSCPUClass, MIPS_CPU)
  * A MIPS CPU model.
  */
 struct MIPSCPUClass {
-    /*< private >*/
     CPUClass parent_class;
-    /*< public >*/
 
     DeviceRealize parent_realize;
     ResettablePhases parent_phases;

diff --git a/target/mips/cpu.h b/target/mips/cpu.h
index 5fddceff3a33c69cc8183b0ac73ae1e4a54d644b..617c3737970dfcc3686313f87f32f2df6eaf7f49 100644 (file)
--- a/target/mips/cpu.h
+++ b/target/mips/cpu.h
@@ -1209,9 +1209,7 @@ typedef struct CPUArchState {
  * A MIPS CPU.
  */
 struct ArchCPU {
-    /*< private >*/
     CPUState parent_obj;
-    /*< public >*/
 
     CPUMIPSState env;
 

diff --git a/target/nios2/cpu.h b/target/nios2/cpu.h
index 70b6377a4f8c947fd4685e92811ad566fd481c23..ede1ba214027ee8bff66b0a9d6a4b0c845078d90 100644 (file)
--- a/target/nios2/cpu.h
+++ b/target/nios2/cpu.h
@@ -42,9 +42,7 @@ OBJECT_DECLARE_CPU_TYPE(Nios2CPU, Nios2CPUClass, NIOS2_CPU)
  * A Nios2 CPU model.
  */
 struct Nios2CPUClass {
-    /*< private >*/
     CPUClass parent_class;
-    /*< public >*/
 
     DeviceRealize parent_realize;
     ResettablePhases parent_phases;
@@ -214,9 +212,7 @@ typedef struct {
  * A Nios2 CPU.
  */
 struct ArchCPU {
-    /*< private >*/
     CPUState parent_obj;
-    /*< public >*/
 
     CPUNios2State env;
 

diff --git a/target/openrisc/cpu.h b/target/openrisc/cpu.h
index 334997e9a103d016c90b33505d9ff0312bdb8689..29cda7279c0f47eedc250afd1ea03a076de9bbbd 100644 (file)
--- a/target/openrisc/cpu.h
+++ b/target/openrisc/cpu.h
@@ -39,9 +39,7 @@ OBJECT_DECLARE_CPU_TYPE(OpenRISCCPU, OpenRISCCPUClass, OPENRISC_CPU)
  * A OpenRISC CPU model.
  */
 struct OpenRISCCPUClass {
-    /*< private >*/
     CPUClass parent_class;
-    /*< public >*/
 
     DeviceRealize parent_realize;
     ResettablePhases parent_phases;
@@ -301,9 +299,7 @@ typedef struct CPUArchState {
  * A OpenRISC CPU.
  */
 struct ArchCPU {
-    /*< private >*/
     CPUState parent_obj;
-    /*< public >*/
 
     CPUOpenRISCState env;
 };

diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
index 30392ebeeef8f0c4bb9fcd79a85aedeea8916071..24dd6b1b0a3d07d49f6dc179930006edb2a6bc2e 100644 (file)
--- a/target/ppc/cpu.h
+++ b/target/ppc/cpu.h
@@ -1313,9 +1313,7 @@ typedef struct PPCVirtualHypervisorClass PPCVirtualHypervisorClass;
  * A PowerPC CPU.
  */
 struct ArchCPU {
-    /*< private >*/
     CPUState parent_obj;
-    /*< public >*/
 
     CPUPPCState env;
 

diff --git a/target/riscv/cpu-qom.h b/target/riscv/cpu-qom.h
index f3fbe37a2c9e9c04e34da5ac204482603311689f..b9164a8e5bd2a76e4172ef6e7d8ca5c53b843ab0 100644 (file)
--- a/target/riscv/cpu-qom.h
+++ b/target/riscv/cpu-qom.h
@@ -63,9 +63,8 @@ OBJECT_DECLARE_CPU_TYPE(RISCVCPU, RISCVCPUClass, RISCV_CPU)
  * A RISCV CPU model.
  */
 struct RISCVCPUClass {
-    /*< private >*/
     CPUClass parent_class;
-    /*< public >*/
+
     DeviceRealize parent_realize;
     ResettablePhases parent_phases;
 };

diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 8efc4d83ecee6ca1a09282ec0b3f49f0dad0b80c..149364745af33fea33ed549043b4522609df0a64 100644 (file)
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -411,9 +411,7 @@ struct CPUArchState {
  * A RISCV CPU.
  */
 struct ArchCPU {
-    /* < private > */
     CPUState parent_obj;
-    /* < public > */
 
     CPURISCVState env;
 

diff --git a/target/rx/cpu-qom.h b/target/rx/cpu-qom.h
index 1c8466a1870e3bcad7091b67ce9198b4880884f7..f4cd5664e5ccc5ac37de4db365a29f74bb913747 100644 (file)
--- a/target/rx/cpu-qom.h
+++ b/target/rx/cpu-qom.h
@@ -36,9 +36,7 @@ OBJECT_DECLARE_CPU_TYPE(RXCPU, RXCPUClass, RX_CPU)
  * A RX CPU model.
  */
 struct RXCPUClass {
-    /*< private >*/
     CPUClass parent_class;
-    /*< public >*/
 
     DeviceRealize parent_realize;
     ResettablePhases parent_phases;

diff --git a/target/rx/cpu.h b/target/rx/cpu.h
index f66754eb8af29bf96acf2340f47de81c7cdfc76c..8379f4a150d5dc09025709acc10a5fa7c27d2f44 100644 (file)
--- a/target/rx/cpu.h
+++ b/target/rx/cpu.h
@@ -107,9 +107,7 @@ typedef struct CPUArchState {
  * A RX CPU
  */
 struct ArchCPU {
-    /*< private >*/
     CPUState parent_obj;
-    /*< public >*/
 
     CPURXState env;
 };

diff --git a/target/s390x/cpu-qom.h b/target/s390x/cpu-qom.h
index 00cae2b1311bdf6fd0ca77ed6bbbd89307418f8b..1088965fd5af320dae13d14c167dc84d843ca4a7 100644 (file)
--- a/target/s390x/cpu-qom.h
+++ b/target/s390x/cpu-qom.h
@@ -49,9 +49,8 @@ typedef enum cpu_reset_type {
  * An S/390 CPU model.
  */
 struct S390CPUClass {
-    /*< private >*/
     CPUClass parent_class;
-    /*< public >*/
+
     const S390CPUDef *cpu_def;
     bool kvm_required;
     bool is_static;

diff --git a/target/s390x/cpu.h b/target/s390x/cpu.h
index 40c5cedd0e02e1ae97f7ef4a602a65745dab057d..4f366f9e4ee25ab71de5efce47a8511c98082e88 100644 (file)
--- a/target/s390x/cpu.h
+++ b/target/s390x/cpu.h
@@ -172,9 +172,7 @@ static inline uint64_t *get_freg(CPUS390XState *cs, int nr)
  * An S/390 CPU.
  */
 struct ArchCPU {
-    /*< private >*/
     CPUState parent_obj;
-    /*< public >*/
 
     CPUS390XState env;
     S390CPUModel *model;

diff --git a/target/sh4/cpu-qom.h b/target/sh4/cpu-qom.h
index 89785a90f02a578437e1743fab11c462afb9a9ca..08fbebc996f7a43a2f095e3dd5075e2198eb35cb 100644 (file)
--- a/target/sh4/cpu-qom.h
+++ b/target/sh4/cpu-qom.h
@@ -42,9 +42,7 @@ OBJECT_DECLARE_CPU_TYPE(SuperHCPU, SuperHCPUClass, SUPERH_CPU)
  * A SuperH CPU model.
  */
 struct SuperHCPUClass {
-    /*< private >*/
     CPUClass parent_class;
-    /*< public >*/
 
     DeviceRealize parent_realize;
     ResettablePhases parent_phases;

diff --git a/target/sh4/cpu.h b/target/sh4/cpu.h
index f75a235973d8a14837e4c5d0c10cc3149f43c39a..dc0561b73bf65202d14e4b95c3226becbff5a665 100644 (file)
--- a/target/sh4/cpu.h
+++ b/target/sh4/cpu.h
@@ -204,9 +204,7 @@ typedef struct CPUArchState {
  * A SuperH CPU.
  */
 struct ArchCPU {
-    /*< private >*/
     CPUState parent_obj;
-    /*< public >*/
 
     CPUSH4State env;
 };

diff --git a/target/sparc/cpu-qom.h b/target/sparc/cpu-qom.h
index 78bf00b9a232c05b1ed10dcd642d007f1d3a21e1..b4a0db84ce3a210468a6f18695756b5c66d200b0 100644 (file)
--- a/target/sparc/cpu-qom.h
+++ b/target/sparc/cpu-qom.h
@@ -40,9 +40,7 @@ typedef struct sparc_def_t sparc_def_t;
  * A SPARC CPU model.
  */
 struct SPARCCPUClass {
-    /*< private >*/
     CPUClass parent_class;
-    /*< public >*/
 
     DeviceRealize parent_realize;
     ResettablePhases parent_phases;

diff --git a/target/sparc/cpu.h b/target/sparc/cpu.h
index 3e361a5b7546287bc01f0617701a3167dcc01704..b48004f8c3258fffc290d04dc394fcad17e815ed 100644 (file)
--- a/target/sparc/cpu.h
+++ b/target/sparc/cpu.h
@@ -562,9 +562,7 @@ struct CPUArchState {
  * A SPARC CPU.
  */
 struct ArchCPU {
-    /*< private >*/
     CPUState parent_obj;
-    /*< public >*/
 
     CPUSPARCState env;
 };

diff --git a/target/tricore/cpu-qom.h b/target/tricore/cpu-qom.h
index 612731daa09abdedcd6de06786c09a9e631858c4..b3b6c75a3ae71aea099e45ea031c868a27a9a6a2 100644 (file)
--- a/target/tricore/cpu-qom.h
+++ b/target/tricore/cpu-qom.h
@@ -27,9 +27,7 @@
 OBJECT_DECLARE_CPU_TYPE(TriCoreCPU, TriCoreCPUClass, TRICORE_CPU)
 
 struct TriCoreCPUClass {
-    /*< private >*/
     CPUClass parent_class;
-    /*< public >*/
 
     DeviceRealize parent_realize;
     ResettablePhases parent_phases;

diff --git a/target/tricore/cpu.h b/target/tricore/cpu.h
index a357b573f28132e454e0e8293469862913a8d57c..b4a6ab141d82892abf8fd6ee1aa4c526221d3647 100644 (file)
--- a/target/tricore/cpu.h
+++ b/target/tricore/cpu.h
@@ -63,9 +63,7 @@ typedef struct CPUArchState {
  * A TriCore CPU.
  */
 struct ArchCPU {
-    /*< private >*/
     CPUState parent_obj;
-    /*< public >*/
 
     CPUTriCoreState env;
 };

diff --git a/target/xtensa/cpu-qom.h b/target/xtensa/cpu-qom.h
index 419c7d8e4a33b5a5c39768436c6d5e79bcc89cdb..424bcbd8ddb19e1ee3f327cdd7190b3ba4c6d595 100644 (file)
--- a/target/xtensa/cpu-qom.h
+++ b/target/xtensa/cpu-qom.h
@@ -47,9 +47,7 @@ typedef struct XtensaConfig XtensaConfig;
  * An Xtensa CPU model.
  */
 struct XtensaCPUClass {
-    /*< private >*/
     CPUClass parent_class;
-    /*< public >*/
 
     DeviceRealize parent_realize;
     ResettablePhases parent_phases;

diff --git a/target/xtensa/cpu.h b/target/xtensa/cpu.h
index c6bbef1e5da9b2f45176e8d2225485c19bd4e54d..85aab1bdf882afc43f45f4c3ee83826345dd8dd2 100644 (file)
--- a/target/xtensa/cpu.h
+++ b/target/xtensa/cpu.h
@@ -556,9 +556,7 @@ struct CPUArchState {
  * An Xtensa CPU.
  */
 struct ArchCPU {
-    /*< private >*/
     CPUState parent_obj;
-    /*< public >*/
 
     CPUXtensaState env;
     Clock *clock;