hvm/svm: Enable MSR events

At this moment there is no function to enable msr interception on svm.

This patch implements this function and moves the mov to msr monitor
event
form the Intel arch side to the common capabilities.

Signed-off-by: Alexandru Isaila <aisaila@bitdefender.com>
Acked-by: Tamas K Lengyel <tamas@tklengyel.com>
Reviewed-by: Boris Ostrovsky <boris.ostrovsky@oracle.com>
Acked-by: Andrew Cooper <andrew.cooper3@citrix.com>

diff --git a/xen/arch/x86/hvm/svm/svm.c b/xen/arch/x86/hvm/svm/svm.c
index 98a83d34854f0d441fac6a8ff9b2fcfef7945565..ad90205fb7379656cf07351090ca34b00156be4a 100644 (file)
--- a/xen/arch/x86/hvm/svm/svm.c
+++ b/xen/arch/x86/hvm/svm/svm.c
@@ -163,6 +163,14 @@ void svm_intercept_msr(struct vcpu *v, uint32_t msr, int flags)
         __clear_bit(msr * 2 + 1, msr_bit);
 }
 
+static void svm_enable_msr_interception(struct domain *d, uint32_t msr)
+{
+    struct vcpu *v;
+
+    for_each_vcpu ( d, v )
+        svm_intercept_msr(v, msr, MSR_INTERCEPT_WRITE);
+}
+
 static void svm_save_dr(struct vcpu *v)
 {
     struct vmcb_struct *vmcb = v->arch.hvm_svm.vmcb;
@@ -2457,6 +2465,7 @@ static struct hvm_function_table __initdata svm_function_table = {
     .fpu_dirty_intercept  = svm_fpu_dirty_intercept,
     .msr_read_intercept   = svm_msr_read_intercept,
     .msr_write_intercept  = svm_msr_write_intercept,
+    .enable_msr_interception = svm_enable_msr_interception,
     .set_rdtsc_exiting    = svm_set_rdtsc_exiting,
     .set_descriptor_access_exiting = svm_set_descriptor_access_exiting,
     .get_insn_bytes       = svm_get_insn_bytes,

diff --git a/xen/include/asm-x86/monitor.h b/xen/include/asm-x86/monitor.h
index b1902f2f3b297972d16d8d9e4740bb4f9a05dedf..9a8f9d9ca264366b7e246a7faeddb96dce6cc73f 100644 (file)
--- a/xen/include/asm-x86/monitor.h
+++ b/xen/include/asm-x86/monitor.h
@@ -78,12 +78,12 @@ static inline uint32_t arch_monitor_get_capabilities(struct domain *d)
         return capabilities;
 
     capabilities = ((1U << XEN_DOMCTL_MONITOR_EVENT_GUEST_REQUEST) |
-                    (1U << XEN_DOMCTL_MONITOR_EVENT_SOFTWARE_BREAKPOINT));
+                    (1U << XEN_DOMCTL_MONITOR_EVENT_SOFTWARE_BREAKPOINT) |
+                    (1U << XEN_DOMCTL_MONITOR_EVENT_MOV_TO_MSR));
 
     if ( cpu_has_vmx )
     {
         capabilities |= ((1U << XEN_DOMCTL_MONITOR_EVENT_WRITE_CTRLREG) |
-                         (1U << XEN_DOMCTL_MONITOR_EVENT_MOV_TO_MSR) |
                          (1U << XEN_DOMCTL_MONITOR_EVENT_DEBUG_EXCEPTION) |
                          (1U << XEN_DOMCTL_MONITOR_EVENT_CPUID) |
                          (1U << XEN_DOMCTL_MONITOR_EVENT_INTERRUPT) |