cpuid_edx(0x8000000A) : 0);
svm_function_table.hap_supported = cpu_has_svm_npt;
- svm_function_table.hap_1gb_pgtb =
- (CONFIG_PAGING_LEVELS == 4)? !!(cpuid_edx(0x80000001) & 0x04000000):0;
+ svm_function_table.hap_superpage_level =
+ ((CONFIG_PAGING_LEVELS == 4) && (cpuid_edx(0x80000001) & 0x04000000)) ?
+ 2 : 1;
return &svm_function_table;
}
if ( vmx_ept_super_page_level_limit )
printk("EPT supports %s super page.\n",
- vmx_ept_super_page_level_limit > 1 ? "1G" : "2M");
+ (vmx_ept_super_page_level_limit == 2) ? "1G" :
+ ((vmx_ept_super_page_level_limit == 1) ? "2M" : "4K"));
}
static u32 adjust_vmx_controls(
setup_ept_dump();
}
- vmx_function_table.hap_1gb_pgtb = (vmx_ept_super_page_level_limit == 2);
+ vmx_function_table.hap_superpage_level = vmx_ept_super_page_level_limit;
setup_vmcs_dump();
{
if ( is_hvm_domain(d) && paging_mode_hap(d) )
order = ( (((gfn | mfn_x(mfn) | todo) & ((1ul << 18) - 1)) == 0) &&
- hvm_funcs.hap_1gb_pgtb && opt_hap_1gb ) ? 18 :
- (((gfn | mfn_x(mfn) | todo) & ((1ul << 9) - 1)) == 0) ? 9 : 0;
+ (hvm_funcs.hap_superpage_level == 2) &&
+ opt_hap_1gb ) ? 18 :
+ ((((gfn | mfn_x(mfn) | todo) & ((1ul << 9) - 1)) == 0) &&
+ (hvm_funcs.hap_superpage_level >= 1)) ? 9 : 0;
else
order = 0;
- /* Note that we only enable hap_1gb_pgtb when CONFIG_PAGING_LEVELS==4.
- * So 1GB should never be enabled under 32bit or PAE modes. But for
- * safety's reason, we double-check the page order again..
- */
- BUG_ON(order == 18 && CONFIG_PAGING_LEVELS < 4);
-
if ( !d->arch.p2m->set_entry(d, gfn, mfn, order, p2mt) )
rc = 0;
gfn += 1ul << order;
/* Support Hardware-Assisted Paging? */
int hap_supported;
- /* Support 1GB Harware-Assisted Paging? */
- int hap_1gb_pgtb;
+ /*
+ * Indicate HAP super page level.
+ * 0 -- 4KB, 1 -- 2MB, 2 -- 1GB.
+ */
+ int hap_superpage_level;
/*