--- /dev/null
+/** @file\r
+ IPMI KCS Register Definitions\r
+\r
+ Copyright (C) 2023 Advanced Micro Devices, Inc. All rights reserved.<BR>\r
+ SPDX-License-Identifier: BSD-2-Clause-Patent\r
+\r
+ @par Revision Reference:\r
+ IPMI Specification\r
+ Version 2.0, Rev. 1.1\r
+ https://www.intel.com/content/www/us/en/products/docs/servers/ipmi/ipmi-second-gen-interface-spec-v2-rev1-1.html\r
+**/\r
+\r
+#ifndef IPMI_KCS_H_\r
+#define IPMI_KCS_H_\r
+\r
+#define IPMI_KCS_STATUS_REGISTER_OFFSET 1\r
+#define IPMI_KCS_COMMAND_REGISTER_OFFSET 1\r
+#define IPMI_KCS_DATA_OUT_REGISTER_OFFSET 0\r
+#define IPMI_KCS_DATA_IN_REGISTER_OFFSET 0\r
+\r
+///\r
+/// IPMI KCS Interface Status Bits\r
+///\r
+#define IPMI_KCS_OBF BIT0\r
+#define IPMI_KCS_IBF BIT1\r
+#define IPMI_KCS_SMS_ATN BIT2\r
+#define IPMI_KCS_COMMAND_DATA BIT3\r
+#define IPMI_KCS_OEM1 BIT4\r
+#define IPMI_KCS_OEM2 BIT5\r
+#define IPMI_KCS_S0 BIT6\r
+#define IPMI_KCS_S1 BIT7\r
+\r
+///\r
+/// IPMI KCS Interface Control Codes\r
+///\r
+#define IPMI_KCS_CONTROL_CODE_GET_STATUS_ABORT 0x60\r
+#define IPMI_KCS_CONTROL_CODE_WRITE_START 0x61\r
+#define IPMI_KCS_CONTROL_CODE_WRITE_END 0x62\r
+#define IPMI_KCS_CONTROL_CODE_READ 0x68\r
+\r
+///\r
+/// Status Codes\r
+///\r
+#define IPMI_KCS_STATUS_NO_ERROR 0x00\r
+#define IPMI_KCS_STATUS_ABORT 0x01\r
+#define IPMI_KCS_STATUS_ILLEGAL 0x02\r
+#define IPMI_KCS_STATUS_LENGTH_ERROR 0x06\r
+#define IPMI_KCS_STATUS_UNSPECIFIED 0xFF\r
+\r
+///\r
+/// KCS Interface State Bit\r
+///\r
+typedef enum {\r
+ IpmiKcsIdleState = 0,\r
+ IpmiKcsReadState,\r
+ IpmiKcsWriteState,\r
+ IpmiKcsErrorState\r
+} IPMI_KCS_STATE;\r
+\r
+///\r
+/// IPMI KCS Interface Request Format\r
+///\r
+typedef struct {\r
+ UINT8 NetFunc;\r
+ UINT8 Command;\r
+ UINT8 Data[];\r
+} IPMI_KCS_REQUEST_HEADER;\r
+\r
+///\r
+/// IPMI KCS Interface Response Format\r
+///\r
+typedef struct {\r
+ UINT8 NetFunc;\r
+ UINT8 Command;\r
+} IPMI_KCS_RESPONSE_HEADER;\r
+#endif\r
# (C) Copyright 2016 - 2021 Hewlett Packard Enterprise Development LP<BR>\r
# Copyright (c) 2022, Loongson Technology Corporation Limited. All rights reserved.<BR>\r
# Copyright (c) 2021 - 2022, Arm Limited. All rights reserved.<BR>\r
+# Copyright (C) 2023 Advanced Micro Devices, Inc. All rights reserved.<BR>\r
#\r
# SPDX-License-Identifier: BSD-2-Clause-Patent\r
#\r
# @Prompt Memory Address of GuidedExtractHandler Table.\r
gEfiMdePkgTokenSpaceGuid.PcdGuidedExtractHandlerTableAddress|0x1000000|UINT64|0x30001015\r
\r
+ ## This value is the IPMI KCS Interface I/O base address used to transmit IPMI commands.\r
+ # The value of 0xca2 is the default I/O base address defined in IPMI specification.\r
+ # @Prompt IPMI KCS Interface I/O Base Address\r
+ gEfiMdePkgTokenSpaceGuid.PcdIpmiKcsIoBaseAddress|0xca2|UINT16|0x00000031\r
+\r
[PcdsFixedAtBuild, PcdsPatchableInModule, PcdsDynamic, PcdsDynamicEx]\r
## This value is used to set the base address of PCI express hierarchy.\r
# @Prompt PCI Express Base Address.\r