/* Helpers for instruction counting code generation. */
+#define ENV_OFFSET offsetof(ArchCPU, env)
+
static TCGOp *icount_start_insn;
static inline void gen_tb_start(TranslationBlock *tb)
QEMUTimer *alarm_timer;
};
-#define ENV_OFFSET offsetof(AlphaCPU, env)
#ifndef CONFIG_USER_ONLY
extern const struct VMStateDescription vmstate_alpha_cpu;
uint64_t arm_cpu_mp_affinity(int idx, uint8_t clustersz);
-#define ENV_OFFSET offsetof(ARMCPU, env)
-
#ifndef CONFIG_USER_ONLY
extern const struct VMStateDescription vmstate_arm_cpu;
#endif
CPUCRISState env;
};
-#define ENV_OFFSET offsetof(CRISCPU, env)
#ifndef CONFIG_USER_ONLY
extern const struct VMStateDescription vmstate_cris_cpu;
QEMUTimer *alarm_timer;
};
-#define ENV_OFFSET offsetof(HPPACPU, env)
typedef CPUHPPAState CPUArchState;
typedef HPPACPU ArchCPU;
int32_t hv_max_vps;
};
-#define ENV_OFFSET offsetof(X86CPU, env)
#ifndef CONFIG_USER_ONLY
extern struct VMStateDescription vmstate_x86_cpu;
uint32_t features;
};
-#define ENV_OFFSET offsetof(LM32CPU, env)
#ifndef CONFIG_USER_ONLY
extern const struct VMStateDescription vmstate_lm32_cpu;
CPUM68KState env;
};
-#define ENV_OFFSET offsetof(M68kCPU, env)
void m68k_cpu_do_interrupt(CPUState *cpu);
bool m68k_cpu_exec_interrupt(CPUState *cpu, int int_req);
CPUMBState env;
};
-#define ENV_OFFSET offsetof(MicroBlazeCPU, env)
void mb_cpu_do_interrupt(CPUState *cs);
bool mb_cpu_exec_interrupt(CPUState *cs, int int_req);
CPUMIPSState env;
};
-#define ENV_OFFSET offsetof(MIPSCPU, env)
void mips_cpu_list(void);
CPUMoxieState env;
} MoxieCPU;
-#define ENV_OFFSET offsetof(MoxieCPU, env)
void moxie_cpu_do_interrupt(CPUState *cs);
void moxie_cpu_dump_state(CPUState *cpu, FILE *f, int flags);
uint32_t fast_tlb_miss_addr;
} Nios2CPU;
-#define ENV_OFFSET offsetof(Nios2CPU, env)
void nios2_tcg_init(void);
void nios2_cpu_do_interrupt(CPUState *cs);
} OpenRISCCPU;
-#define ENV_OFFSET offsetof(OpenRISCCPU, env)
void cpu_openrisc_list(void);
void openrisc_cpu_do_interrupt(CPUState *cpu);
int32_t mig_slb_nr;
};
-#define ENV_OFFSET offsetof(PowerPCCPU, env)
PowerPCCPUClass *ppc_cpu_class_by_pvr(uint32_t pvr);
PowerPCCPUClass *ppc_cpu_class_by_pvr_mask(uint32_t pvr);
extern const char * const riscv_excp_names[];
extern const char * const riscv_intr_names[];
-#define ENV_OFFSET offsetof(RISCVCPU, env)
-
void riscv_cpu_do_interrupt(CPUState *cpu);
int riscv_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg);
int riscv_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
uint32_t irqstate_saved_size;
};
-#define ENV_OFFSET offsetof(S390CPU, env)
#ifndef CONFIG_USER_ONLY
extern const struct VMStateDescription vmstate_s390_cpu;
CPUSH4State env;
};
-#define ENV_OFFSET offsetof(SuperHCPU, env)
void superh_cpu_do_interrupt(CPUState *cpu);
bool superh_cpu_exec_interrupt(CPUState *cpu, int int_req);
CPUSPARCState env;
};
-#define ENV_OFFSET offsetof(SPARCCPU, env)
#ifndef CONFIG_USER_ONLY
extern const struct VMStateDescription vmstate_sparc_cpu;
CPUTLGState env;
} TileGXCPU;
-#define ENV_OFFSET offsetof(TileGXCPU, env)
/* TILE-Gx memory attributes */
#define MMU_USER_IDX 0 /* Current memory operation is in user mode */
CPUTriCoreState env;
};
-#define ENV_OFFSET offsetof(TriCoreCPU, env)
hwaddr tricore_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
void tricore_cpu_dump_state(CPUState *cpu, FILE *f, int flags);
CPUUniCore32State env;
};
-#define ENV_OFFSET offsetof(UniCore32CPU, env)
void uc32_cpu_do_interrupt(CPUState *cpu);
bool uc32_cpu_exec_interrupt(CPUState *cpu, int int_req);
CPUXtensaState env;
};
-#define ENV_OFFSET offsetof(XtensaCPU, env)
-
bool xtensa_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
MMUAccessType access_type, int mmu_idx,