x86: set ARAT feature flag for non-buggy AMD CPUs

This is the equivalent of a recent Linux change.

Signed-off-by: Jan Beulich <jbeulich@novell.com>

diff --git a/xen/arch/x86/cpu/amd.c b/xen/arch/x86/cpu/amd.c
index 3533d3e404cfb2941f687d2ef86fb73da1edafd9..7255e0ebbad6ac0176ad870e0cc9155ecb814354 100644 (file)
--- a/xen/arch/x86/cpu/amd.c
+++ b/xen/arch/x86/cpu/amd.c
@@ -474,6 +474,10 @@ static void __devinit init_amd(struct cpuinfo_x86 *c)
        }
 #endif
 
+       /* As a rule processors have APIC timer running in deep C states */
+       if (c->x86 >= 0xf && !cpu_has_amd_erratum(c, AMD_ERRATUM_400))
+               set_bit(X86_FEATURE_ARAT, c->x86_capability);
+
        /* Prevent TSC drift in non single-processor, single-core platforms. */
        if ((smp_processor_id() == 1) && c1_ramping_may_cause_clock_drift(c))
                disable_c1_ramping();

diff --git a/xen/include/asm-x86/amd.h b/xen/include/asm-x86/amd.h
index d7fb1a5b53a5fd3115f93c9ee4245043f1ddc9a3..283c17207468b80c0e876bf1313f56f9baec5210 100644 (file)
--- a/xen/include/asm-x86/amd.h
+++ b/xen/include/asm-x86/amd.h
@@ -134,6 +134,10 @@
     AMD_OSVW_ERRATUM(3, AMD_MODEL_RANGE(0x10, 0x2, 0x1, 0xff, 0xf),    \
                        AMD_MODEL_RANGE(0x12, 0x0, 0x0, 0x1, 0x0))
 
+#define AMD_ERRATUM_400                                                 \
+    AMD_OSVW_ERRATUM(1, AMD_MODEL_RANGE(0xf, 0x41, 0x2, 0xff, 0xf),     \
+                        AMD_MODEL_RANGE(0x10, 0x2, 0x1, 0xff, 0xf))
+
 struct cpuinfo_x86;
 int cpu_has_amd_erratum(const struct cpuinfo_x86 *, int, ...);