ArmPkg/ArmLib: Drop set/way Dcache operations

Cache maintenance operations by set/way are not broadcast, and operate
on individual architected caches, making them suitable only for
en/disabling cache levels, which is the job of secure firmware, to be
carried out while the CPU in question is not taking part in the
cache coherency protocol.

Managing the clean/dirty state of a memory range can only be done using
cache maintenance by virtual address.

So drop the set/way handling from ArmLib for ARM and AARCH64, as there
is no context where it can be used correctly from EDK2.

Signed-off-by: Ard Biesheuvel <ardb@kernel.org>

diff --git a/ArmPkg/Library/ArmLib/AArch64/AArch64Lib.c b/ArmPkg/Library/ArmLib/AArch64/AArch64Lib.c
index 6739f5c37d38640694a4e82c9d7618c1fea57e64..53b202ff34a86eeb266ab6ba2b309926a1661023 100644 (file)
--- a/ArmPkg/Library/ArmLib/AArch64/AArch64Lib.c
+++ b/ArmPkg/Library/ArmLib/AArch64/AArch64Lib.c
@@ -18,61 +18,6 @@
 #include "AArch64Lib.h"\r
 #include "ArmLibPrivate.h"\r
 \r
-VOID\r
-AArch64DataCacheOperation (\r
-  IN  AARCH64_CACHE_OPERATION  DataCacheOperation\r
-  )\r
-{\r
-  UINTN  SavedInterruptState;\r
-\r
-  SavedInterruptState = ArmGetInterruptState ();\r
-  ArmDisableInterrupts ();\r
-\r
-  AArch64AllDataCachesOperation (DataCacheOperation);\r
-\r
-  ArmDataSynchronizationBarrier ();\r
-\r
-  if (SavedInterruptState) {\r
-    ArmEnableInterrupts ();\r
-  }\r
-}\r
-\r
-VOID\r
-EFIAPI\r
-ArmInvalidateDataCache (\r
-  VOID\r
-  )\r
-{\r
-  ASSERT (!ArmMmuEnabled ());\r
-\r
-  ArmDataSynchronizationBarrier ();\r
-  AArch64DataCacheOperation (ArmInvalidateDataCacheEntryBySetWay);\r
-}\r
-\r
-VOID\r
-EFIAPI\r
-ArmCleanInvalidateDataCache (\r
-  VOID\r
-  )\r
-{\r
-  ASSERT (!ArmMmuEnabled ());\r
-\r
-  ArmDataSynchronizationBarrier ();\r
-  AArch64DataCacheOperation (ArmCleanInvalidateDataCacheEntryBySetWay);\r
-}\r
-\r
-VOID\r
-EFIAPI\r
-ArmCleanDataCache (\r
-  VOID\r
-  )\r
-{\r
-  ASSERT (!ArmMmuEnabled ());\r
-\r
-  ArmDataSynchronizationBarrier ();\r
-  AArch64DataCacheOperation (ArmCleanDataCacheEntryBySetWay);\r
-}\r
-\r
 /**\r
   Check whether the CPU supports the GIC system register interface (any version)\r
 \r

diff --git a/ArmPkg/Library/ArmLib/AArch64/AArch64Lib.h b/ArmPkg/Library/ArmLib/AArch64/AArch64Lib.h
index 6380a019ddc54e0d665afbb1d843df7ba65320a7..7127a768ef8e16476f2949ea26763f85a1d338bc 100644 (file)
--- a/ArmPkg/Library/ArmLib/AArch64/AArch64Lib.h
+++ b/ArmPkg/Library/ArmLib/AArch64/AArch64Lib.h
@@ -11,33 +11,6 @@
 #ifndef AARCH64_LIB_H_\r
 #define AARCH64_LIB_H_\r
 \r
-typedef VOID (*AARCH64_CACHE_OPERATION)(\r
-  UINTN\r
-  );\r
-\r
-VOID\r
-AArch64AllDataCachesOperation (\r
-  IN  AARCH64_CACHE_OPERATION  DataCacheOperation\r
-  );\r
-\r
-VOID\r
-EFIAPI\r
-ArmInvalidateDataCacheEntryBySetWay (\r
-  IN  UINTN  SetWayFormat\r
-  );\r
-\r
-VOID\r
-EFIAPI\r
-ArmCleanDataCacheEntryBySetWay (\r
-  IN  UINTN  SetWayFormat\r
-  );\r
-\r
-VOID\r
-EFIAPI\r
-ArmCleanInvalidateDataCacheEntryBySetWay (\r
-  IN  UINTN  SetWayFormat\r
-  );\r
-\r
 UINTN\r
 EFIAPI\r
 ArmReadIdAA64Dfr0 (\r

diff --git a/ArmPkg/Library/ArmLib/AArch64/AArch64Support.S b/ArmPkg/Library/ArmLib/AArch64/AArch64Support.S
index 19c77d31b5e0a72aec5a454130befcef0203ab8a..66daa27fb4018aac1b8c2151be5b60514408c8fe 100644 (file)
--- a/ArmPkg/Library/ArmLib/AArch64/AArch64Support.S
+++ b/ArmPkg/Library/ArmLib/AArch64/AArch64Support.S
@@ -43,22 +43,6 @@ ASM_FUNC(ArmCleanInvalidateDataCacheEntryByMVA)
   dc      civac, x0   // Clean and invalidate single data cache line\r
   ret\r
 \r
-\r
-ASM_FUNC(ArmInvalidateDataCacheEntryBySetWay)\r
-  dc      isw, x0     // Invalidate this line\r
-  ret\r
-\r
-\r
-ASM_FUNC(ArmCleanInvalidateDataCacheEntryBySetWay)\r
-  dc      cisw, x0    // Clean and Invalidate this line\r
-  ret\r
-\r
-\r
-ASM_FUNC(ArmCleanDataCacheEntryBySetWay)\r
-  dc      csw, x0     // Clean this line\r
-  ret\r
-\r
-\r
 ASM_FUNC(ArmInvalidateInstructionCache)\r
   ic      iallu       // Invalidate entire instruction cache\r
   dsb     sy\r
@@ -257,65 +241,6 @@ ASM_FUNC(ArmDisableBranchPrediction)
   ret\r
 \r
 \r
-ASM_FUNC(AArch64AllDataCachesOperation)\r
-// We can use regs 0-7 and 9-15 without having to save/restore.\r
-// Save our link register on the stack. - The stack must always be quad-word aligned\r
-  stp   x29, x30, [sp, #-16]!\r
-  mov   x29, sp\r
-  mov   x1, x0                  // Save Function call in x1\r
-  mrs   x6, clidr_el1           // Read EL1 CLIDR\r
-  and   x3, x6, #0x7000000      // Mask out all but Level of Coherency (LoC)\r
-  lsr   x3, x3, #23             // Left align cache level value - the level is shifted by 1 to the\r
-                                // right to ease the access to CSSELR and the Set/Way operation.\r
-  cbz   x3, L_Finished          // No need to clean if LoC is 0\r
-  mov   x10, #0                 // Start clean at cache level 0\r
-\r
-Loop1:\r
-  add   x2, x10, x10, lsr #1    // Work out 3x cachelevel for cache info\r
-  lsr   x12, x6, x2             // bottom 3 bits are the Cache type for this level\r
-  and   x12, x12, #7            // get those 3 bits alone\r
-  cmp   x12, #2                 // what cache at this level?\r
-  b.lt  L_Skip                  // no cache or only instruction cache at this level\r
-  msr   csselr_el1, x10         // write the Cache Size selection register with current level (CSSELR)\r
-  isb                           // isb to sync the change to the CacheSizeID reg\r
-  mrs   x12, ccsidr_el1         // reads current Cache Size ID register (CCSIDR)\r
-  and   x2, x12, #0x7           // extract the line length field\r
-  add   x2, x2, #4              // add 4 for the line length offset (log2 16 bytes)\r
-  mov   x4, #0x400\r
-  sub   x4, x4, #1\r
-  and   x4, x4, x12, lsr #3     // x4 is the max number on the way size (right aligned)\r
-  clz   w5, w4                  // w5 is the bit position of the way size increment\r
-  mov   x7, #0x00008000\r
-  sub   x7, x7, #1\r
-  and   x7, x7, x12, lsr #13    // x7 is the max number of the index size (right aligned)\r
-\r
-Loop2:\r
-  mov   x9, x4                  // x9 working copy of the max way size (right aligned)\r
-\r
-Loop3:\r
-  lsl   x11, x9, x5\r
-  orr   x0, x10, x11            // factor in the way number and cache number\r
-  lsl   x11, x7, x2\r
-  orr   x0, x0, x11             // factor in the index number\r
-\r
-  blr   x1                      // Goto requested cache operation\r
-\r
-  subs  x9, x9, #1              // decrement the way number\r
-  b.ge  Loop3\r
-  subs  x7, x7, #1              // decrement the index\r
-  b.ge  Loop2\r
-L_Skip:\r
-  add   x10, x10, #2            // increment the cache number\r
-  cmp   x3, x10\r
-  b.gt  Loop1\r
-\r
-L_Finished:\r
-  dsb   sy\r
-  isb\r
-  ldp   x29, x30, [sp], #0x10\r
-  ret\r
-\r
-\r
 ASM_FUNC(ArmDataMemoryBarrier)\r
   dmb   sy\r
   ret\r

diff --git a/ArmPkg/Library/ArmLib/Arm/ArmV7Lib.c b/ArmPkg/Library/ArmLib/Arm/ArmV7Lib.c
index 6acc4d3e7cc5bc99b1cca2a351b08e01fb0af224..dd1e8c5930c2f6cb259c0ec2696f5de3cb84e11c 100644 (file)
--- a/ArmPkg/Library/ArmLib/Arm/ArmV7Lib.c
+++ b/ArmPkg/Library/ArmLib/Arm/ArmV7Lib.c
@@ -18,61 +18,6 @@
 #include "ArmV7Lib.h"\r
 #include "ArmLibPrivate.h"\r
 \r
-VOID\r
-ArmV7DataCacheOperation (\r
-  IN  ARM_V7_CACHE_OPERATION  DataCacheOperation\r
-  )\r
-{\r
-  UINTN  SavedInterruptState;\r
-\r
-  SavedInterruptState = ArmGetInterruptState ();\r
-  ArmDisableInterrupts ();\r
-\r
-  ArmV7AllDataCachesOperation (DataCacheOperation);\r
-\r
-  ArmDataSynchronizationBarrier ();\r
-\r
-  if (SavedInterruptState) {\r
-    ArmEnableInterrupts ();\r
-  }\r
-}\r
-\r
-VOID\r
-EFIAPI\r
-ArmInvalidateDataCache (\r
-  VOID\r
-  )\r
-{\r
-  ASSERT (!ArmMmuEnabled ());\r
-\r
-  ArmDataSynchronizationBarrier ();\r
-  ArmV7DataCacheOperation (ArmInvalidateDataCacheEntryBySetWay);\r
-}\r
-\r
-VOID\r
-EFIAPI\r
-ArmCleanInvalidateDataCache (\r
-  VOID\r
-  )\r
-{\r
-  ASSERT (!ArmMmuEnabled ());\r
-\r
-  ArmDataSynchronizationBarrier ();\r
-  ArmV7DataCacheOperation (ArmCleanInvalidateDataCacheEntryBySetWay);\r
-}\r
-\r
-VOID\r
-EFIAPI\r
-ArmCleanDataCache (\r
-  VOID\r
-  )\r
-{\r
-  ASSERT (!ArmMmuEnabled ());\r
-\r
-  ArmDataSynchronizationBarrier ();\r
-  ArmV7DataCacheOperation (ArmCleanDataCacheEntryBySetWay);\r
-}\r
-\r
 /**\r
   Check whether the CPU supports the GIC system register interface (any version)\r
 \r

diff --git a/ArmPkg/Library/ArmLib/Arm/ArmV7Lib.h b/ArmPkg/Library/ArmLib/Arm/ArmV7Lib.h
index 404ff92c4e06e436d9454e788cc7162e6b1995d0..548be5cf28b090fb13a28b283029b44d84dd8d45 100644 (file)
--- a/ArmPkg/Library/ArmLib/Arm/ArmV7Lib.h
+++ b/ArmPkg/Library/ArmLib/Arm/ArmV7Lib.h
@@ -23,33 +23,6 @@
 #define ID_MMFR0_SHR_IMP_HW_COHERENT  1\r
 #define ID_MMFR0_SHR_IGNORED          0xf\r
 \r
-typedef VOID (*ARM_V7_CACHE_OPERATION)(\r
-  UINT32\r
-  );\r
-\r
-VOID\r
-ArmV7AllDataCachesOperation (\r
-  IN  ARM_V7_CACHE_OPERATION  DataCacheOperation\r
-  );\r
-\r
-VOID\r
-EFIAPI\r
-ArmInvalidateDataCacheEntryBySetWay (\r
-  IN  UINTN  SetWayFormat\r
-  );\r
-\r
-VOID\r
-EFIAPI\r
-ArmCleanDataCacheEntryBySetWay (\r
-  IN  UINTN  SetWayFormat\r
-  );\r
-\r
-VOID\r
-EFIAPI\r
-ArmCleanInvalidateDataCacheEntryBySetWay (\r
-  IN  UINTN  SetWayFormat\r
-  );\r
-\r
 /** Reads the ID_MMFR4 register.\r
 \r
    @return The contents of the ID_MMFR4 register.\r

diff --git a/ArmPkg/Library/ArmLib/Arm/ArmV7Support.S b/ArmPkg/Library/ArmLib/Arm/ArmV7Support.S
index 70b27da70c6523ea4cdf629567aaf9c549ffda95..0bfb5f1c9971bf801548838ca0b05da489e289d1 100644 (file)
--- a/ArmPkg/Library/ArmLib/Arm/ArmV7Support.S
+++ b/ArmPkg/Library/ArmLib/Arm/ArmV7Support.S
@@ -42,20 +42,6 @@ ASM_FUNC(ArmCleanInvalidateDataCacheEntryByMVA)
   bx      lr\r
 \r
 \r
-ASM_FUNC(ArmInvalidateDataCacheEntryBySetWay)\r
-  mcr     p15, 0, r0, c7, c6, 2        @ Invalidate this line\r
-  bx      lr\r
-\r
-\r
-ASM_FUNC(ArmCleanInvalidateDataCacheEntryBySetWay)\r
-  mcr     p15, 0, r0, c7, c14, 2       @ Clean and Invalidate this line\r
-  bx      lr\r
-\r
-\r
-ASM_FUNC(ArmCleanDataCacheEntryBySetWay)\r
-  mcr     p15, 0, r0, c7, c10, 2       @ Clean this line\r
-  bx      lr\r
-\r
 ASM_FUNC(ArmInvalidateInstructionCache)\r
   mcr     p15,0,R0,c7,c5,0      @Invalidate entire instruction cache\r
   dsb\r
@@ -171,59 +157,6 @@ ASM_FUNC(ArmSetHighVectors)
   isb\r
   bx      LR\r
 \r
-ASM_FUNC(ArmV7AllDataCachesOperation)\r
-  stmfd SP!,{r4-r12, LR}\r
-  mov   R1, R0                @ Save Function call in R1\r
-  mrc   p15, 1, R6, c0, c0, 1 @ Read CLIDR\r
-  ands  R3, R6, #0x7000000    @ Mask out all but Level of Coherency (LoC)\r
-  mov   R3, R3, LSR #23       @ Cache level value (naturally aligned)\r
-  beq   L_Finished\r
-  mov   R10, #0\r
-\r
-Loop1:\r
-  add   R2, R10, R10, LSR #1  @ Work out 3xcachelevel\r
-  mov   R12, R6, LSR R2       @ bottom 3 bits are the Cache type for this level\r
-  and   R12, R12, #7          @ get those 3 bits alone\r
-  cmp   R12, #2\r
-  blt   L_Skip                  @ no cache or only instruction cache at this level\r
-  mcr   p15, 2, R10, c0, c0, 0  @ write the Cache Size selection register (CSSELR) // OR in 1 for Instruction\r
-  isb                           @ isb to sync the change to the CacheSizeID reg\r
-  mrc   p15, 1, R12, c0, c0, 0  @ reads current Cache Size ID register (CCSIDR)\r
-  and   R2, R12, #0x7           @ extract the line length field\r
-  add   R2, R2, #4              @ add 4 for the line length offset (log2 16 bytes)\r
-@  ldr   R4, =0x3FF\r
-  mov   R4, #0x400\r
-  sub   R4, R4, #1\r
-  ands  R4, R4, R12, LSR #3     @ R4 is the max number on the way size (right aligned)\r
-  clz   R5, R4                  @ R5 is the bit position of the way size increment\r
-@  ldr   R7, =0x00007FFF\r
-  mov   R7, #0x00008000\r
-  sub   R7, R7, #1\r
-  ands  R7, R7, R12, LSR #13    @ R7 is the max number of the index size (right aligned)\r
-\r
-Loop2:\r
-  mov   R9, R4                  @ R9 working copy of the max way size (right aligned)\r
-\r
-Loop3:\r
-  orr   R0, R10, R9, LSL R5     @ factor in the way number and cache number into R11\r
-  orr   R0, R0, R7, LSL R2      @ factor in the index number\r
-\r
-  blx   R1\r
-\r
-  subs  R9, R9, #1              @ decrement the way number\r
-  bge   Loop3\r
-  subs  R7, R7, #1              @ decrement the index\r
-  bge   Loop2\r
-L_Skip:\r
-  add   R10, R10, #2            @ increment the cache number\r
-  cmp   R3, R10\r
-  bgt   Loop1\r
-\r
-L_Finished:\r
-  dsb\r
-  ldmfd SP!, {r4-r12, lr}\r
-  bx    LR\r
-\r
 ASM_FUNC(ArmDataMemoryBarrier)\r
   dmb\r
   bx      LR\r