i.MX: split the GPT timer implementation into per SOC definitions

In various Freescale SOCs, the GPT timers can be configured to select
its input clock.

Depending on the SOC the set of available input clocks may vary.

The actual single GPT definition was no good enough and because of it
booting the sabrelite board with a i.MX6DL device tree would fail
because of an incorrect input clock definition for the i.MX6DL SOC.

This patch fixes the i.MX6DL boot failure by adding the ability to
define a different set of input clocks depending on the considered SOC.

A different class has been defined for i.MX25, i.MX31 and i.MX6 each with
its specific set of input clocks.

The patch has been tested by booting KZM, i.MX25 PDK, i.MX6Q sabrelite
and i.MX6DL sabrelite.

Signed-off-by: Jean-Christophe Dubois <jcd@tribudubois.net>
Message-id: 1467325619-8374-1-git-send-email-jcd@tribudubois.net
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
[PMM: fixed spacing round '/' operator]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

diff --git a/hw/arm/fsl-imx25.c b/hw/arm/fsl-imx25.c
index 1a53e51cf129c7e12b81b04767732251d97f36cf..b4e358db65bb7a59921305e01aacc99ffa34e305 100644 (file)
--- a/hw/arm/fsl-imx25.c
+++ b/hw/arm/fsl-imx25.c
@@ -51,7 +51,7 @@ static void fsl_imx25_init(Object *obj)
     }
 
     for (i = 0; i < FSL_IMX25_NUM_GPTS; i++) {
-        object_initialize(&s->gpt[i], sizeof(s->gpt[i]), TYPE_IMX_GPT);
+        object_initialize(&s->gpt[i], sizeof(s->gpt[i]), TYPE_IMX25_GPT);
         qdev_set_parent_bus(DEVICE(&s->gpt[i]), sysbus_get_default());
     }
 

diff --git a/hw/arm/fsl-imx31.c b/hw/arm/fsl-imx31.c
index b283b71eb47e0ec41c9a03927514fbd0112ccd5b..fe204ace626edbc8d64fa0e277d7046c9315f6ab 100644 (file)
--- a/hw/arm/fsl-imx31.c
+++ b/hw/arm/fsl-imx31.c
@@ -47,7 +47,7 @@ static void fsl_imx31_init(Object *obj)
         qdev_set_parent_bus(DEVICE(&s->uart[i]), sysbus_get_default());
     }
 
-    object_initialize(&s->gpt, sizeof(s->gpt), TYPE_IMX_GPT);
+    object_initialize(&s->gpt, sizeof(s->gpt), TYPE_IMX31_GPT);
     qdev_set_parent_bus(DEVICE(&s->gpt), sysbus_get_default());
 
     for (i = 0; i < FSL_IMX31_NUM_EPITS; i++) {

diff --git a/hw/arm/fsl-imx6.c b/hw/arm/fsl-imx6.c
index ed392a9e7f2bbc4b0d1a3841249a8789361123b8..6a1bf263a51d6354e4d87c20375446bd96485545 100644 (file)
--- a/hw/arm/fsl-imx6.c
+++ b/hw/arm/fsl-imx6.c
@@ -67,7 +67,7 @@ static void fsl_imx6_init(Object *obj)
         object_property_add_child(obj, name, OBJECT(&s->uart[i]), NULL);
     }
 
-    object_initialize(&s->gpt, sizeof(s->gpt), TYPE_IMX_GPT);
+    object_initialize(&s->gpt, sizeof(s->gpt), TYPE_IMX6_GPT);
     qdev_set_parent_bus(DEVICE(&s->gpt), sysbus_get_default());
     object_property_add_child(obj, "gpt", OBJECT(&s->gpt), NULL);
 

diff --git a/hw/misc/imx6_ccm.c b/hw/misc/imx6_ccm.c
index ec58eef92d1bd82b844731582aad587eff14414f..17e15d4c92eba70ce581d9a4681909d2ad3454e1 100644 (file)
--- a/hw/misc/imx6_ccm.c
+++ b/hw/misc/imx6_ccm.c
@@ -371,6 +371,12 @@ static uint32_t imx6_ccm_get_clock_frequency(IMXCCMState *dev, IMXClk clock)
     case CLK_32k:
         freq = CKIL_FREQ;
         break;
+    case CLK_HIGH:
+        freq = 24000000;
+        break;
+    case CLK_HIGH_DIV:
+        freq = 24000000 / 8;
+        break;
     default:
         qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: unsupported clock %d\n",
                       TYPE_IMX6_CCM, __func__, clock);

diff --git a/hw/timer/imx_gpt.c b/hw/timer/imx_gpt.c
index 3c2f01ab99160a2568b326b9160086762517dc00..82bc73cb86890393d5e4f804f12a5911abd97801 100644 (file)
--- a/hw/timer/imx_gpt.c
+++ b/hw/timer/imx_gpt.c
@@ -14,7 +14,6 @@
 
 #include "qemu/osdep.h"
 #include "hw/timer/imx_gpt.h"
-#include "hw/misc/imx_ccm.h"
 #include "qemu/main-loop.h"
 #include "qemu/log.h"
 
@@ -81,7 +80,18 @@ static const VMStateDescription vmstate_imx_timer_gpt = {
     }
 };
 
-static const IMXClk imx_gpt_clocks[] = {
+static const IMXClk imx25_gpt_clocks[] = {
+    CLK_NONE,      /* 000 No clock source */
+    CLK_IPG,       /* 001 ipg_clk, 532MHz*/
+    CLK_IPG_HIGH,  /* 010 ipg_clk_highfreq */
+    CLK_NONE,      /* 011 not defined */
+    CLK_32k,       /* 100 ipg_clk_32k */
+    CLK_32k,       /* 101 ipg_clk_32k */
+    CLK_32k,       /* 110 ipg_clk_32k */
+    CLK_32k,       /* 111 ipg_clk_32k */
+};
+
+static const IMXClk imx31_gpt_clocks[] = {
     CLK_NONE,      /* 000 No clock source */
     CLK_IPG,       /* 001 ipg_clk, 532MHz*/
     CLK_IPG_HIGH,  /* 010 ipg_clk_highfreq */
@@ -92,12 +102,23 @@ static const IMXClk imx_gpt_clocks[] = {
     CLK_NONE,      /* 111 not defined */
 };
 
+static const IMXClk imx6_gpt_clocks[] = {
+    CLK_NONE,      /* 000 No clock source */
+    CLK_IPG,       /* 001 ipg_clk, 532MHz*/
+    CLK_IPG_HIGH,  /* 010 ipg_clk_highfreq */
+    CLK_EXT,       /* 011 External clock */
+    CLK_32k,       /* 100 ipg_clk_32k */
+    CLK_HIGH_DIV,  /* 101 reference clock / 8 */
+    CLK_NONE,      /* 110 not defined */
+    CLK_HIGH,      /* 111 reference clock */
+};
+
 static void imx_gpt_set_freq(IMXGPTState *s)
 {
     uint32_t clksrc = extract32(s->cr, GPT_CR_CLKSRC_SHIFT, 3);
 
     s->freq = imx_ccm_get_clock_frequency(s->ccm,
-                                imx_gpt_clocks[clksrc]) / (1 + s->pr);
+                                          s->clocks[clksrc]) / (1 + s->pr);
 
     DPRINTF("Setting clksrc %d to frequency %d\n", clksrc, s->freq);
 
@@ -453,16 +474,52 @@ static void imx_gpt_class_init(ObjectClass *klass, void *data)
     dc->desc = "i.MX general timer";
 }
 
-static const TypeInfo imx_gpt_info = {
-    .name = TYPE_IMX_GPT,
+static void imx25_gpt_init(Object *obj)
+{
+    IMXGPTState *s = IMX_GPT(obj);
+
+    s->clocks = imx25_gpt_clocks;
+}
+
+static void imx31_gpt_init(Object *obj)
+{
+    IMXGPTState *s = IMX_GPT(obj);
+
+    s->clocks = imx31_gpt_clocks;
+}
+
+static void imx6_gpt_init(Object *obj)
+{
+    IMXGPTState *s = IMX_GPT(obj);
+
+    s->clocks = imx6_gpt_clocks;
+}
+
+static const TypeInfo imx25_gpt_info = {
+    .name = TYPE_IMX25_GPT,
     .parent = TYPE_SYS_BUS_DEVICE,
     .instance_size = sizeof(IMXGPTState),
+    .instance_init = imx25_gpt_init,
     .class_init = imx_gpt_class_init,
 };
 
+static const TypeInfo imx31_gpt_info = {
+    .name = TYPE_IMX31_GPT,
+    .parent = TYPE_IMX25_GPT,
+    .instance_init = imx31_gpt_init,
+};
+
+static const TypeInfo imx6_gpt_info = {
+    .name = TYPE_IMX6_GPT,
+    .parent = TYPE_IMX25_GPT,
+    .instance_init = imx6_gpt_init,
+};
+
 static void imx_gpt_register_types(void)
 {
-    type_register_static(&imx_gpt_info);
+    type_register_static(&imx25_gpt_info);
+    type_register_static(&imx31_gpt_info);
+    type_register_static(&imx6_gpt_info);
 }
 
 type_init(imx_gpt_register_types)

diff --git a/include/hw/misc/imx_ccm.h b/include/hw/misc/imx_ccm.h
index 48a7afad5e7ef4125e008fab10599bccacd70835..33cbc099526837d8b5c186593ab710c7ba9138f3 100644 (file)
--- a/include/hw/misc/imx_ccm.h
+++ b/include/hw/misc/imx_ccm.h
@@ -46,7 +46,10 @@ typedef enum  {
     CLK_NONE,
     CLK_IPG,
     CLK_IPG_HIGH,
-    CLK_32k
+    CLK_32k,
+    CLK_EXT,
+    CLK_HIGH_DIV,
+    CLK_HIGH,
 } IMXClk;
 
 typedef struct IMXCCMClass {

diff --git a/include/hw/timer/imx_gpt.h b/include/hw/timer/imx_gpt.h
index 461adbe53f935fddd7cc31d349bffcb1a0679fe4..eac59b2a70ca9b7c0e2eda3079f04ec6dd08e59a 100644 (file)
--- a/include/hw/timer/imx_gpt.h
+++ b/include/hw/timer/imx_gpt.h
@@ -74,7 +74,12 @@
 #define GPT_IR_OF3IE  (1 << 2)
 #define GPT_IR_ROVIE  (1 << 5)
 
-#define TYPE_IMX_GPT "imx.gpt"
+#define TYPE_IMX25_GPT "imx25.gpt"
+#define TYPE_IMX31_GPT "imx31.gpt"
+#define TYPE_IMX6_GPT "imx6.gpt"
+
+#define TYPE_IMX_GPT TYPE_IMX25_GPT
+
 #define IMX_GPT(obj) OBJECT_CHECK(IMXGPTState, (obj), TYPE_IMX_GPT)
 
 typedef struct IMXGPTState{
@@ -103,6 +108,8 @@ typedef struct IMXGPTState{
     uint32_t freq;
 
     qemu_irq irq;
+
+    const IMXClk *clocks;
 } IMXGPTState;
 
 #endif /* IMX_GPT_H */