xen/arm: Don't boot Xen on platform using AIVIVT instruction caches

The AIVIVT is a type of instruction cache available on Armv7. This is
the only cache not implementing the IVIPT extension and therefore
requiring specific care.

To simplify maintenance requirements, Xen will not boot on platform
using AIVIVT cache.

This should not be an issue because Xen Arm32 can only boot on a small
number of processors (see arch/arm/arm32/proc-v7.S). All of them are
not using AIVIVT cache.

Signed-off-by: Julien Grall <julien.grall@arm.com>
Acked-by: Stefano Stabellini <sstabellini@kernel.org>

diff --git a/xen/arch/arm/setup.c b/xen/arch/arm/setup.c
index 5af49c7a08a1d3b9f376ae7948f61e3bd2697764..9ff6f83981b534c0a64ba5ff41a5f62d43fd35db 100644 (file)
--- a/xen/arch/arm/setup.c
+++ b/xen/arch/arm/setup.c
@@ -526,10 +526,15 @@ static void __init setup_mm(unsigned long dtb_paddr, size_t dtb_size)
     unsigned long boot_mfn_start, boot_mfn_end;
     int i;
     void *fdt;
+    const uint32_t ctr = READ_CP32(CTR);
 
     if ( !bootinfo.mem.nr_banks )
         panic("No memory bank\n");
 
+    /* We only supports instruction caches implementing the IVIPT extension. */
+    if ( ((ctr >> CTR_L1Ip_SHIFT) & CTR_L1Ip_MASK) == CTR_L1Ip_AIVIVT )
+        panic("AIVIVT instruction cache not supported\n");
+
     init_pdx();
 
     ram_start = bootinfo.mem.bank[0].start;

diff --git a/xen/include/asm-arm/processor.h b/xen/include/asm-arm/processor.h
index a54583baeb18fd3e341ccb1ef0acd21c538264b6..bbcba061caad9608390fab048d058969347f01d3 100644 (file)
--- a/xen/include/asm-arm/processor.h
+++ b/xen/include/asm-arm/processor.h
@@ -6,6 +6,11 @@
 #endif
 #include <public/arch-arm.h>
 
+/* CTR Cache Type Register */
+#define CTR_L1Ip_MASK       0x3
+#define CTR_L1Ip_SHIFT      14
+#define CTR_L1Ip_AIVIVT     0x1
+
 /* MIDR Main ID Register */
 #define MIDR_REVISION_MASK      0xf
 #define MIDR_RESIVION(midr)     ((midr) & MIDR_REVISION_MASK)