x86/spec-ctrl: Expose RRSBA_CTRL to guests

The CPUID feature bit signals the presence of the RRSBA_DIS_{U,S} controls in
SPEC_CTRL MSR, first available in Intel AlderLake and Sapphire Rapids CPUs.

Xen already knows how to context switch MSR_SPEC_CTRL properly between guest
and hypervisor context.

Signed-off-by: Roger Pau Monné <roger.pau@citrix.com>
Reviewed-by: Jan Beulich <jbeulich@suse.com>
Reviewed-by: Andrew Cooper <andrew.cooper3@citrix.com>
(cherry picked from commit 478e4787fa64b621061177a7843c452e9a19916d)

diff --git a/tools/misc/xen-cpuid.c b/tools/misc/xen-cpuid.c
index e59e17c722e75ab981b0304f3b4c71f8d4ad3502..9b3378fca763b8334360c2b24f9b8a0c6c18fcc1 100644 (file)
--- a/tools/misc/xen-cpuid.c
+++ b/tools/misc/xen-cpuid.c
@@ -213,6 +213,7 @@ static const char *const str_7d1[32] =
 static const char *const str_7d2[32] =
 {
     [ 0] = "intel-psfd",    [ 1] = "ipred-ctrl",
+    [ 2] = "rrsba-ctrl",
 };
 
 static const char *const str_m10Al[32] =

diff --git a/xen/arch/x86/msr.c b/xen/arch/x86/msr.c
index 91b7402fba780cf2e44096759df305c1d9b248ec..0000d4a4c2fa452465c2d0e07210eb2c5e0da129 100644 (file)
--- a/xen/arch/x86/msr.c
+++ b/xen/arch/x86/msr.c
@@ -323,6 +323,8 @@ uint64_t msr_spec_ctrl_valid_bits(const struct cpu_policy *cp)
             (psfd       ? SPEC_CTRL_PSFD       : 0) |
             (cp->feat.ipred_ctrl
              ? (SPEC_CTRL_IPRED_DIS_U | SPEC_CTRL_IPRED_DIS_S) : 0) |
+            (cp->feat.rrsba_ctrl
+             ? (SPEC_CTRL_RRSBA_DIS_U | SPEC_CTRL_RRSBA_DIS_S) : 0) |
             0);
 }
 

diff --git a/xen/include/asm-x86/msr-index.h b/xen/include/asm-x86/msr-index.h
index cab836c88fe5426ab8ab57c86ec2c13fc0dca2dc..2380d1955866ba6ad811cd0bbf27219d713e42f5 100644 (file)
--- a/xen/include/asm-x86/msr-index.h
+++ b/xen/include/asm-x86/msr-index.h
@@ -38,6 +38,8 @@
 #define  SPEC_CTRL_SSBD                     (_AC(1, ULL) <<  2)
 #define  SPEC_CTRL_IPRED_DIS_U              (_AC(1, ULL) <<  3)
 #define  SPEC_CTRL_IPRED_DIS_S              (_AC(1, ULL) <<  4)
+#define  SPEC_CTRL_RRSBA_DIS_U              (_AC(1, ULL) <<  5)
+#define  SPEC_CTRL_RRSBA_DIS_S              (_AC(1, ULL) <<  6)
 #define  SPEC_CTRL_PSFD                     (_AC(1, ULL) <<  7)
 
 #define MSR_PRED_CMD                        0x00000049

diff --git a/xen/include/public/arch-x86/cpufeatureset.h b/xen/include/public/arch-x86/cpufeatureset.h
index 96601c5c2091122888dddf20be9ee67df4f5a2d0..f4563212d6284212644efa4b4dbd08044e72a38e 100644 (file)
--- a/xen/include/public/arch-x86/cpufeatureset.h
+++ b/xen/include/public/arch-x86/cpufeatureset.h
@@ -308,6 +308,7 @@ XEN_CPUFEATURE(SRSO_NO,            11*32+29) /*A  Hardware not vulenrable to Spe
 /* Intel-defined CPU features, CPUID level 0x00000007:2.edx, word 13 */
 XEN_CPUFEATURE(INTEL_PSFD,         13*32+ 0) /*A  MSR_SPEC_CTRL.PSFD */
 XEN_CPUFEATURE(IPRED_CTRL,         13*32+ 1) /*A  MSR_SPEC_CTRL.IPRED_DIS_* */
+XEN_CPUFEATURE(RRSBA_CTRL,         13*32+ 2) /*A  MSR_SPEC_CTRL.RRSBA_DIS_* */
 
 /* Intel-defined CPU features, CPUID level 0x00000007:1.ecx, word 14 */
 

diff --git a/xen/tools/gen-cpuid.py b/xen/tools/gen-cpuid.py
index f68e3ff875df2986b0f42855dfccb3f3a38da00f..a1742094a9a7915531be8f61870b2ee47bfd64d7 100755 (executable)
--- a/xen/tools/gen-cpuid.py
+++ b/xen/tools/gen-cpuid.py
@@ -318,7 +318,7 @@ def crunch_numbers(state):
         # as dependent features simplifies Xen's logic, and prevents the guest
         # from seeing implausible configurations.
         IBRSB: [STIBP, SSBD, INTEL_PSFD, EIBRS,
-                IPRED_CTRL],
+                IPRED_CTRL, RRSBA_CTRL],
         IBRS: [AMD_STIBP, AMD_SSBD, PSFD,
                IBRS_ALWAYS, IBRS_FAST, IBRS_SAME_MODE],
         IBPB: [IBPB_RET, SBPB, IBPB_BRTYPE],