cpuid results are possible to be changed now. For example, changing
CR4.OSXSAVE bit or setting MSR XCR_XFEATURE_ENABLED_MASK may change
XSAVE related cpuid leave return values.
The volatile prefix is required to avoid the second cpuid calls
following some possible changing operations being optimized in
incorrect way by compiler.
The sample bug is in xsave_init while debug=3Dn. The second call to
cpuid_count() may be optimized and lead to a BUG_ON case while compare
xsave_cntxt_size with ebx.
Signed-off-by: Wei Gang <gang.wei@intel.com>
xen-unstable changeset: 23036:
9a15ff175e00
xen-unstable date: Mon Mar 14 17:04:42 2011 +0000
* resulting in stale register contents being returned.
*/
#define cpuid(_op,_eax,_ebx,_ecx,_edx) \
- asm ( "cpuid" \
+ asm volatile ( "cpuid" \
: "=a" (*(int *)(_eax)), \
"=b" (*(int *)(_ebx)), \
"=c" (*(int *)(_ecx)), \
unsigned int *ecx,
unsigned int *edx)
{
- asm ( "cpuid"
+ asm volatile ( "cpuid"
: "=a" (*eax), "=b" (*ebx), "=c" (*ecx), "=d" (*edx)
: "0" (op), "c" (count) );
}
{
unsigned int eax;
- asm ( "cpuid"
+ asm volatile ( "cpuid"
: "=a" (eax)
: "0" (op)
: "bx", "cx", "dx" );
{
unsigned int eax, ebx;
- asm ( "cpuid"
+ asm volatile ( "cpuid"
: "=a" (eax), "=b" (ebx)
: "0" (op)
: "cx", "dx" );
{
unsigned int eax, ecx;
- asm ( "cpuid"
+ asm volatile ( "cpuid"
: "=a" (eax), "=c" (ecx)
: "0" (op)
: "bx", "dx" );
{
unsigned int eax, edx;
- asm ( "cpuid"
+ asm volatile ( "cpuid"
: "=a" (eax), "=d" (edx)
: "0" (op)
: "bx", "cx" );