Provide PTE_SIZE and PTE_ORDER appropriate for the in-use paging mode

Signed-off-by: Andrew Cooper <andrew.cooper3@citrix.com>

diff --git a/arch/x86/hvm/pagetables.S b/arch/x86/hvm/pagetables.S
index a0d5431c31c0dd804aff01e9756c23a444b181a0..ffb94dc6337ca1d406b750001f43e94c28ac9a4d 100644 (file)
--- a/arch/x86/hvm/pagetables.S
+++ b/arch/x86/hvm/pagetables.S
@@ -11,8 +11,8 @@
 
 #define PAGE_COMMON _PAGE_DIRTY + _PAGE_ACCESSED + _PAGE_USER + _PAGE_RW + _PAGE_PRESENT
 
-#define PAE_IDX(sym) ((. - (sym)) / PAE_PTE_SZ)
-#define PSE_IDX(sym) ((. - (sym)) / PSE_PTE_SZ)
+#define PAE_IDX(sym) ((. - (sym)) / PAE_PTE_SIZE)
+#define PSE_IDX(sym) ((. - (sym)) / PSE_PTE_SIZE)
 
         .data
         .p2align PAGE_SHIFT

diff --git a/include/arch/x86/page-pae.h b/include/arch/x86/page-pae.h
index fcade43b06093d29ae7daea31ff62975a8a5826d..2e3231cf1022b3e0988501e606c96994b38e8975 100644 (file)
--- a/include/arch/x86/page-pae.h
+++ b/include/arch/x86/page-pae.h
@@ -7,17 +7,19 @@
 #define XTF_X86_PAGE_PAE_H
 
 /** PAE pagetable entries are 64 bits wide. */
-#define PAE_PTE_SZ 8
+#define PAE_PTE_SIZE 8
+/** PAE pagetable entries are 64 bits wide. */
+#define PAE_PTE_ORDER 3
 
 /** PAE pagetables encode 9 bits of index. */
 #define PAE_PT_ORDER     9
 
 /** @{ */
 /** All PAE pagetables contain 512 entries. */
-#define PAE_L1_PT_ENTRIES (PAGE_SIZE / PAE_PTE_SZ)
-#define PAE_L2_PT_ENTRIES (PAGE_SIZE / PAE_PTE_SZ)
-#define PAE_L3_PT_ENTRIES (PAGE_SIZE / PAE_PTE_SZ)
-#define PAE_L4_PT_ENTRIES (PAGE_SIZE / PAE_PTE_SZ)
+#define PAE_L1_PT_ENTRIES (PAGE_SIZE / PAE_PTE_SIZE)
+#define PAE_L2_PT_ENTRIES (PAGE_SIZE / PAE_PTE_SIZE)
+#define PAE_L3_PT_ENTRIES (PAGE_SIZE / PAE_PTE_SIZE)
+#define PAE_L4_PT_ENTRIES (PAGE_SIZE / PAE_PTE_SIZE)
 
 /* Other than PAE32_L3, which has 4 entries. */
 #define PAE32_L3_ENTRIES 4

diff --git a/include/arch/x86/page-pse.h b/include/arch/x86/page-pse.h
index 517cdc76dd94c560dd7a79a3656440c435507bfd..0d233edb78381872989e468318dd8b93acceb708 100644 (file)
--- a/include/arch/x86/page-pse.h
+++ b/include/arch/x86/page-pse.h
@@ -7,15 +7,17 @@
 #define XTF_X86_PAGE_PSE_H
 
 /** PSE pagetable entries are 32 bits wide. */
-#define PSE_PTE_SZ 4
+#define PSE_PTE_SIZE 4
+/** PSE pagetable entries are 32 bits wide. */
+#define PSE_PTE_ORDER 2
 
 /** PAE pagetables encode 10 bits of index. */
 #define PSE_PT_ORDER 10
 
 /** @{ */
 /** All PSE pagetables contain 1024 entries. */
-#define PSE_L1_PT_ENTRIES (PAGE_SIZE / PSE_PTE_SZ)
-#define PSE_L2_PT_ENTRIES (PAGE_SIZE / PSE_PTE_SZ)
+#define PSE_L1_PT_ENTRIES (PAGE_SIZE / PSE_PTE_SIZE)
+#define PSE_L2_PT_ENTRIES (PAGE_SIZE / PSE_PTE_SIZE)
 /** @} */
 
 #define PSE_L1_PT_SHIFT 12

diff --git a/include/arch/x86/page.h b/include/arch/x86/page.h
index 95052c83ba23e80b57d45e5c8d8f448d1e94f2d2..9241525523497153003947d097cbccb29e43610b 100644 (file)
--- a/include/arch/x86/page.h
+++ b/include/arch/x86/page.h
@@ -39,6 +39,9 @@
 
 #if CONFIG_PAGING_LEVELS == 2 /* PSE Paging */
 
+#define PTE_SIZE  PSE_PTE_SIZE
+#define PTE_ORDER PSE_PTE_ORDER
+
 #define PT_ORDER PSE_PT_ORDER
 
 #define L1_PT_SHIFT PSE_L1_PT_SHIFT
@@ -49,6 +52,9 @@
 
 #else /* CONFIG_PAGING_LEVELS == 2 */ /* PAE Paging */
 
+#define PTE_SIZE  PAE_PTE_SIZE
+#define PTE_ORDER PAE_PTE_ORDER
+
 #define PT_ORDER PAE_PT_ORDER
 
 #define L1_PT_SHIFT PAE_L1_PT_SHIFT