OvmfPkg/PlatformInitLib: update address space layout comment

Move the commment up so it is placed just before the address space
calculations start.  Also add q35 memory layout.

Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
Reviewed-by: Anthony PERARD <anthony.perard@citrix.com>

diff --git a/OvmfPkg/Library/PlatformInitLib/Platform.c b/OvmfPkg/Library/PlatformInitLib/Platform.c
index 9fee6e481038647d0140a66eb331c568a1f63736..678e8e329023b753a2e317485fdb8d91e554effb 100644 (file)
--- a/OvmfPkg/Library/PlatformInitLib/Platform.c
+++ b/OvmfPkg/Library/PlatformInitLib/Platform.c
@@ -152,6 +152,21 @@ PlatformMemMapInitialization (
     return;\r
   }\r
 \r
+  //\r
+  // address       purpose   size\r
+  // ------------  --------  -------------------------\r
+  // max(top, 2g)  PCI MMIO  0xFC000000 - max(top, 2g)  (pc)\r
+  // 0xB0000000    MMCONFIG                     256 MB  (q35)\r
+  // 0xC0000000    PCI MMIO                     960 MB  (q35)\r
+  // 0xFC000000    gap                           44 MB\r
+  // 0xFEC00000    IO-APIC                        4 KB\r
+  // 0xFEC01000    gap                         1020 KB\r
+  // 0xFED00000    HPET                           1 KB\r
+  // 0xFED00400    gap                          111 KB\r
+  // 0xFED1C000    gap (PIIX4) / RCRB (ICH9)     16 KB\r
+  // 0xFED20000    gap                          896 KB\r
+  // 0xFEE00000    LAPIC                          1 MB\r
+  //\r
   PlatformGetSystemMemorySizeBelow4gb (PlatformInfoHob);\r
   PciExBarBase = 0;\r
   if (PlatformInfoHob->HostBridgeDevId == INTEL_Q35_MCH_DEVICE_ID) {\r
@@ -168,19 +183,6 @@ PlatformMemMapInitialization (
     PciBase = PlatformInfoHob->Uc32Base;\r
   }\r
 \r
-  //\r
-  // address       purpose   size\r
-  // ------------  --------  -------------------------\r
-  // max(top, 2g)  PCI MMIO  0xFC000000 - max(top, 2g)\r
-  // 0xFC000000    gap                           44 MB\r
-  // 0xFEC00000    IO-APIC                        4 KB\r
-  // 0xFEC01000    gap                         1020 KB\r
-  // 0xFED00000    HPET                           1 KB\r
-  // 0xFED00400    gap                          111 KB\r
-  // 0xFED1C000    gap (PIIX4) / RCRB (ICH9)     16 KB\r
-  // 0xFED20000    gap                          896 KB\r
-  // 0xFEE00000    LAPIC                          1 MB\r
-  //\r
   PciSize = 0xFC000000 - PciBase;\r
   PlatformAddIoMemoryBaseSizeHob (PciBase, PciSize);\r
 \r