]> xenbits.xensource.com Git - people/dwmw2/xen.git/commitdiff
x86/AMD: limit C1E disable family range
authorJan Beulich <jbeulich@suse.com>
Tue, 18 Jun 2019 14:34:51 +0000 (16:34 +0200)
committerJan Beulich <jbeulich@suse.com>
Tue, 18 Jun 2019 14:34:51 +0000 (16:34 +0200)
Just like for other family values of 0x17 (see "x86/AMD: correct certain
Fam17 checks"), commit 3157bb4e13 ("Add MSR support for various feature
AMD processor families") made the original check for Fam11 here include
families all the way up to Fam17. The involved MSR (0xC0010055),
however, is fully reserved starting from Fam16, and the two bits of
interest are reserved for Fam12 and onwards (albeit I admit I wasn't
able to find any Fam13 doc). Restore the upper bound to be Fam11.

Signed-off-by: Jan Beulich <jbeulich@suse.com>
Acked-by: Andrew Cooper <andrew.cooper3@citrix.com>
xen/arch/x86/cpu/amd.c

index e8be2e6c50d83b1f9ff94fae87d6ed2a62c66d38..839f19292d5efe62a10018abc5a7c5b1044d4b32 100644 (file)
@@ -635,7 +635,7 @@ static void init_amd(struct cpuinfo_x86 *c)
 
        switch(c->x86)
        {
-       case 0xf ... 0x17:
+       case 0xf ... 0x11:
                disable_c1e(NULL);
                if (acpi_smi_cmd && (acpi_enable_value | acpi_disable_value))
                        amd_acpi_c1e_quirk = true;