]> xenbits.xensource.com Git - xen.git/commitdiff
x86/spec_ctrl: Add Hygon Dhyana to the respective mitigation machinery
authorPu Wen <puwen@hygon.cn>
Thu, 4 Apr 2019 13:46:33 +0000 (21:46 +0800)
committerAndrew Cooper <andrew.cooper3@citrix.com>
Thu, 6 Jun 2019 14:28:21 +0000 (15:28 +0100)
The Hygon Dhyana CPU has the same speculative execution as AMD family
17h, so share AMD Retpoline and PTI mitigation code with Hygon Dhyana.

Signed-off-by: Pu Wen <puwen@hygon.cn>
Acked-by: Jan Beulich <jbeulich@suse.com>
[Rebase over 0cd074144cb "x86/cpu: Renumber X86_VENDOR_* to form a bitmap"]
Signed-off-by: Andrew Cooper <andrew.cooper3@citrix.com>
xen/arch/x86/spec_ctrl.c

index e66879f5c05a57fd4b831ec64e03184c2c68a3b5..cada9a058e1af4b2938bd9a19d2c151ec452c8eb 100644 (file)
@@ -192,7 +192,7 @@ int8_t __read_mostly opt_xpti_domu = -1;
 
 static __init void xpti_init_default(uint64_t caps)
 {
-    if ( boot_cpu_data.x86_vendor == X86_VENDOR_AMD )
+    if ( boot_cpu_data.x86_vendor & (X86_VENDOR_AMD | X86_VENDOR_HYGON) )
         caps = ARCH_CAPS_RDCL_NO;
 
     if ( caps & ARCH_CAPS_RDCL_NO )
@@ -438,7 +438,7 @@ static bool __init retpoline_safe(uint64_t caps)
 {
     unsigned int ucode_rev = this_cpu(ucode_cpu_info).cpu_sig.rev;
 
-    if ( boot_cpu_data.x86_vendor == X86_VENDOR_AMD )
+    if ( boot_cpu_data.x86_vendor & (X86_VENDOR_AMD | X86_VENDOR_HYGON) )
         return true;
 
     if ( boot_cpu_data.x86_vendor != X86_VENDOR_INTEL ||