]> xenbits.xensource.com Git - qemu-xen.git/commitdiff
hw/sparc64: Fix code style for checkpatch.pl
authorPhilippe Mathieu-Daudé <f4bug@amsat.org>
Wed, 28 Apr 2021 14:16:53 +0000 (16:16 +0200)
committerMark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Tue, 4 May 2021 21:45:53 +0000 (22:45 +0100)
We are going to move this code, fix its style first.

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: KONRAD Frederic <frederic.konrad@adacore.com>
Reviewed-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20210428141655.387430-4-f4bug@amsat.org>
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
hw/sparc64/sparc64.c

index cc0b9bd30d39029849f24c57d1d1b8dcd52ca37c..fd29a79edc0479d077ca14970aadb114211c8b3c 100644 (file)
@@ -48,14 +48,18 @@ void cpu_check_irqs(CPUSPARCState *env)
         return;
     }
     cs = env_cpu(env);
-    /* check if TM or SM in SOFTINT are set
-       setting these also causes interrupt 14 */
+    /*
+     * check if TM or SM in SOFTINT are set
+     * setting these also causes interrupt 14
+     */
     if (env->softint & (SOFTINT_TIMER | SOFTINT_STIMER)) {
         pil |= 1 << 14;
     }
 
-    /* The bit corresponding to psrpil is (1<< psrpil), the next bit
-       is (2 << psrpil). */
+    /*
+     * The bit corresponding to psrpil is (1<< psrpil),
+     * the next bit is (2 << psrpil).
+     */
     if (pil < (2 << env->psrpil)) {
         if (cs->interrupt_request & CPU_INTERRUPT_HARD) {
             trace_sparc64_cpu_check_irqs_reset_irq(env->interrupt_index);