]> xenbits.xensource.com Git - xen.git/commitdiff
xen/pvh: Fix segment selector ABI
authorAndrew Cooper <andrew.cooper3@citrix.com>
Thu, 5 Mar 2020 10:35:17 +0000 (11:35 +0100)
committerIan Jackson <ian.jackson@eu.citrix.com>
Tue, 5 May 2020 14:33:08 +0000 (15:33 +0100)
The written ABI states that %es will be set up, but libxc doesn't do so.  In
practice, it breaks `rep movs` inside guests before they reload %es.

The written ABI doesn't mention %ss, but libxc does set it up.  Having %ds
different to %ss is obnoxous to work with, as different registers have
different implicit segments.

Modify the spec to state that %ss is set up as a flat read/write segment.
This a) matches the Multiboot 1 spec, b) matches what is set up in practice,
and c) is the more sane behaviour for guests to use.

Fixes: 68e1183411b ('libxc: introduce a xc_dom_arch for hvm-3.0-x86_32 guests')
Signed-off-by: Andrew Cooper <andrew.cooper3@citrix.com>
Reviewed-by: Wei Liu <wl@xen.org>
Reviewed-by: Roger Pau Monné <roger.pau@citrix.com>
x86/pvh: Adjust dom0's starting state

Fixes: b25fb1a04e "xen/pvh: Fix segment selector ABI"
Signed-off-by: Andrew Cooper <andrew.cooper3@citrix.com>
Reviewed-by: Wei Liu <wl@xen.org>
Acked-by: Jan Beulich <jbeulich@suse.com>
master commit: b25fb1a04e99cc03359eade1affb56ef0eee766f
master date: 2020-02-10 15:26:09 +0000
master commit: 6ee10313623c1f41fc72fe12372e176e744463c1
master date: 2020-02-11 11:04:26 +0000

(cherry picked from commit 722458767a297a3ced04743c0156e6ac614e89bf)

docs/misc/pvh.markdown
tools/libxc/xc_dom_x86.c
xen/arch/x86/hvm/dom0_build.c

index e85fb15374b162ec77eaaaa7e3f940cfcadc9996..09db72b8bca3b95d6c19044c4547c23470468240 100644 (file)
@@ -23,7 +23,7 @@ following machine state:
  * `cs`: must be a 32-bit read/execute code segment with a base of ‘0’
    and a limit of ‘0xFFFFFFFF’. The selector value is unspecified.
 
- * `ds`, `es`: must be a 32-bit read/write data segment with a base of
+ * `ds`, `es`, `ss`: must be a 32-bit read/write data segment with a base of
    ‘0’ and a limit of ‘0xFFFFFFFF’. The selector values are all unspecified.
 
  * `tr`: must be a 32-bit TSS (active) with a base of '0' and a limit of '0x67'.
index f935d4991d9fdf56c59d75c88ea4e896a7832678..7ad9609103e4ad869a5caf27d00a75461248740f 100644 (file)
@@ -998,14 +998,17 @@ static int vcpu_hvm(struct xc_dom_image *dom)
     /* Set the cached part of the relevant segment registers. */
     bsp_ctx.cpu.cs_base = 0;
     bsp_ctx.cpu.ds_base = 0;
+    bsp_ctx.cpu.es_base = 0;
     bsp_ctx.cpu.ss_base = 0;
     bsp_ctx.cpu.tr_base = 0;
     bsp_ctx.cpu.cs_limit = ~0u;
     bsp_ctx.cpu.ds_limit = ~0u;
+    bsp_ctx.cpu.es_limit = ~0u;
     bsp_ctx.cpu.ss_limit = ~0u;
     bsp_ctx.cpu.tr_limit = 0x67;
     bsp_ctx.cpu.cs_arbytes = 0xc9b;
     bsp_ctx.cpu.ds_arbytes = 0xc93;
+    bsp_ctx.cpu.es_arbytes = 0xc93;
     bsp_ctx.cpu.ss_arbytes = 0xc93;
     bsp_ctx.cpu.tr_arbytes = 0x8b;
 
index 303ae4e7b5b373ed744edf7a04520fb5b8e4572c..d6763b8753da6d7d12f252217308cb408235cbb1 100644 (file)
@@ -577,10 +577,12 @@ static int __init pvh_setup_cpus(struct domain *d, paddr_t entry,
         .cpu_regs.x86_32.cr0 = X86_CR0_PE | X86_CR0_ET,
         .cpu_regs.x86_32.cs_limit = ~0u,
         .cpu_regs.x86_32.ds_limit = ~0u,
+        .cpu_regs.x86_32.es_limit = ~0u,
         .cpu_regs.x86_32.ss_limit = ~0u,
         .cpu_regs.x86_32.tr_limit = 0x67,
         .cpu_regs.x86_32.cs_ar = 0xc9b,
         .cpu_regs.x86_32.ds_ar = 0xc93,
+        .cpu_regs.x86_32.es_ar = 0xc93,
         .cpu_regs.x86_32.ss_ar = 0xc93,
         .cpu_regs.x86_32.tr_ar = 0x8b,
     };