static const uint32_t msrs_to_send[] = {
MSR_SPEC_CTRL,
MSR_INTEL_MISC_FEATURES_ENABLES,
+ MSR_PKRS,
MSR_IA32_BNDCFGS,
MSR_IA32_XSS,
MSR_VIRT_SPEC_CTRL,
case MSR_SPEC_CTRL:
case MSR_INTEL_MISC_FEATURES_ENABLES:
+ case MSR_PKRS:
case MSR_IA32_BNDCFGS:
case MSR_IA32_XSS:
case MSR_VIRT_SPEC_CTRL:
else
vmx_set_msr_intercept(v, MSR_FLUSH_CMD, VMX_MSR_RW);
+ if ( cp->feat.pks )
+ vmx_clear_msr_intercept(v, MSR_PKRS, VMX_MSR_RW);
+ else
+ vmx_set_msr_intercept(v, MSR_PKRS, VMX_MSR_RW);
+
out:
vmx_vmcs_exit(v);
{
const struct vcpu *curr = current;
struct domain *d = v->domain;
+ const struct vcpu_msrs *msrs = v->arch.msrs;
uint64_t val = 0;
int rc;
}
return val;
+ case MSR_PKRS:
+ return (v == curr) ? rdpkrs() : msrs->pkrs;
+
case MSR_SHADOW_GS_BASE:
if ( v != curr )
return v->arch.hvm.vmx.shadow_gs;
static void cf_check vmx_set_reg(struct vcpu *v, unsigned int reg, uint64_t val)
{
+ const struct vcpu *curr = current;
+ struct vcpu_msrs *msrs = v->arch.msrs;
struct domain *d = v->domain;
int rc;
domain_crash(d);
}
return;
+
+ case MSR_PKRS:
+ msrs->pkrs = val;
+ if ( v == curr )
+ wrpkrs(val);
+ return;
}
/* Logic which maybe requires remote VMCS acquisition. */
*val = 0;
break;
+ case MSR_PKRS:
+ if ( !cp->feat.pks )
+ goto gp_fault;
+ goto get_reg;
+
case MSR_X2APIC_FIRST ... MSR_X2APIC_LAST:
if ( !is_hvm_domain(d) || v != curr )
goto gp_fault;
break;
goto gp_fault;
+ case MSR_PKRS:
+ if ( !cp->feat.pks || val != (uint32_t)val )
+ goto gp_fault;
+ goto set_reg;
+
case MSR_X2APIC_FIRST ... MSR_X2APIC_LAST:
if ( !is_hvm_domain(d) || v != curr )
goto gp_fault;