x86/AMD: work around erratum 793

The recommendation is to set a bit in an MSR - do this if the firmware
didn't, considering that otherwise we expose ourselves to a guest
induced DoS.

This is CVE-2013-6885 / XSA-82.

Signed-off-by: Jan Beulich <jbeulich@suse.com>
Acked-by: Suravee Suthikulpanit <suravee.suthikulpanit@amd.com>
Acked-by: Ian Campbell <ian.campbell@citrix.com>
master commit: 98162f256ee33994a9881a720419dda9ad4c03a8
master date: 2013-12-03 09:49:54 +0100

diff --git a/xen/arch/x86/cpu/amd.c b/xen/arch/x86/cpu/amd.c
index bd19c2360d14514caad34db84411907041b2b46a..54ca33c6543290f59b3afd6ccf291e4709f8391b 100644 (file)
--- a/xen/arch/x86/cpu/amd.c
+++ b/xen/arch/x86/cpu/amd.c
@@ -649,6 +649,20 @@ static void __devinit init_amd(struct cpuinfo_x86 *c)
                       "*** Pass \"allow_unsafe\" if you're trusting"
                       " all your (PV) guest kernels. ***\n");
 
+       if (c->x86 == 0x16 && c->x86_model <= 0xf) {
+               rdmsrl(MSR_AMD64_LS_CFG, value);
+               if (!(value & (1 << 15))) {
+                       static bool_t warned;
+
+                       if (c == &boot_cpu_data || opt_cpu_info ||
+                           !test_and_set_bool(warned))
+                               printk(KERN_WARNING
+                                      "CPU%u: Applying workaround for erratum 793\n",
+                                      smp_processor_id());
+                       wrmsrl(MSR_AMD64_LS_CFG, value | (1 << 15));
+               }
+       }
+
        /* AMD CPUs do not support SYSENTER outside of legacy mode. */
        clear_bit(X86_FEATURE_SEP, c->x86_capability);
 

diff --git a/xen/include/asm-x86/msr-index.h b/xen/include/asm-x86/msr-index.h
index 0b81710c6a253fa8f5145b12c90b871be5812135..e123ab7ec0445be1590bb388e79bb5292d6e4293 100644 (file)
--- a/xen/include/asm-x86/msr-index.h
+++ b/xen/include/asm-x86/msr-index.h
@@ -245,6 +245,7 @@
 
 /* AMD64 MSRs */
 #define MSR_AMD64_NB_CFG               0xc001001f
+#define MSR_AMD64_LS_CFG               0xc0011020
 #define MSR_AMD64_IC_CFG               0xc0011021
 #define MSR_AMD64_DC_CFG               0xc0011022
 #define AMD64_NB_CFG_CF8_EXT_ENABLE_BIT        46