uint32_t hvf_get_supported_cpuid(uint32_t func, uint32_t idx, int reg);
void hvf_handle_io(CPUState *, uint16_t, void *, int, int, int);
-void hvf_simulate_rdmsr(CPUX86State *env);
-void hvf_simulate_wrmsr(CPUX86State *env);
+void hvf_simulate_rdmsr(CPUState *cpu);
+void hvf_simulate_wrmsr(CPUState *cpu);
/* Host specific functions */
int hvf_inject_interrupt(CPUArchState *env, int vector);
.write_mem = hvf_write_mem,
.read_segment_descriptor = hvf_read_segment_descriptor,
.handle_io = hvf_handle_io,
+ .simulate_rdmsr = hvf_simulate_rdmsr,
+ .simulate_wrmsr = hvf_simulate_wrmsr,
};
int hvf_arch_init_vcpu(CPUState *cpu)
macvm_set_rip(cs, env->eip);
}
-void hvf_simulate_rdmsr(CPUX86State *env)
+void hvf_simulate_rdmsr(CPUState *cs)
{
- X86CPU *cpu = env_archcpu(env);
- CPUState *cs = env_cpu(env);
+ X86CPU *cpu = X86_CPU(cs);
+ CPUX86State *env = &cpu->env;
uint32_t msr = ECX(env);
uint64_t val = 0;
RDX(env) = (uint32_t)(val >> 32);
}
-void hvf_simulate_wrmsr(CPUX86State *env)
+void hvf_simulate_wrmsr(CPUState *cs)
{
- X86CPU *cpu = env_archcpu(env);
- CPUState *cs = env_cpu(env);
+ X86CPU *cpu = X86_CPU(cs);
+ CPUX86State *env = &cpu->env;
uint32_t msr = ECX(env);
uint64_t data = ((uint64_t)EDX(env) << 32) | EAX(env);
{
hvf_load_regs(cpu);
if (exit_reason == EXIT_REASON_RDMSR) {
- hvf_simulate_rdmsr(env);
+ hvf_simulate_rdmsr(cpu);
} else {
- hvf_simulate_wrmsr(env);
+ hvf_simulate_wrmsr(cpu);
}
env->eip += ins_len;
hvf_store_regs(cpu);
static void exec_rdmsr(CPUX86State *env, struct x86_decode *decode)
{
- hvf_simulate_rdmsr(env);
+ emul_ops->simulate_rdmsr(env_cpu(env));
env->eip += decode->len;
}
static void exec_wrmsr(CPUX86State *env, struct x86_decode *decode)
{
- hvf_simulate_wrmsr(env);
+ emul_ops->simulate_wrmsr(env_cpu(env));
env->eip += decode->len;
}
enum X86Seg seg);
void (*handle_io)(CPUState *cpu, uint16_t port, void *data, int direction,
int size, int count);
+ void (*simulate_rdmsr)(CPUState *cs);
+ void (*simulate_wrmsr)(CPUState *cs);
};
extern const struct x86_emul_ops *emul_ops;