Fix int/float inconsistencies.

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3672 c046a42c-6fe2-441c-8c8c-71466251a162

diff --git a/target-mips/fop_template.c b/target-mips/fop_template.c
index 8ee0525130b11cfa6f559f30282dedf7b61b7886..c5941d121637f802022b6572668c1c7683824565 100644 (file)
--- a/target-mips/fop_template.c
+++ b/target-mips/fop_template.c
@@ -24,14 +24,14 @@
 #define OP_WLOAD_FREG(treg, tregname, FREG)              \
     void glue(glue(op_load_fpr_,tregname), FREG) (void)  \
     {                                                    \
-        treg = env->fpu->fpr[FREG].fs[FP_ENDIAN_IDX];    \
+        treg = env->fpu->fpr[FREG].w[FP_ENDIAN_IDX];    \
         FORCE_RET();                                     \
     }
 
 #define OP_WSTORE_FREG(treg, tregname, FREG)             \
     void glue(glue(op_store_fpr_,tregname), FREG) (void) \
     {                                                    \
-        env->fpu->fpr[FREG].fs[FP_ENDIAN_IDX] = treg;    \
+        env->fpu->fpr[FREG].w[FP_ENDIAN_IDX] = treg;    \
         FORCE_RET();                                     \
     }
 
@@ -50,10 +50,10 @@ OP_WSTORE_FREG(WT2, WT2_fpr, FREG)
     void glue(glue(op_load_fpr_,tregname), FREG) (void)  \
     {                                                    \
         if (env->hflags & MIPS_HFLAG_F64)                \
-            treg = env->fpu->fpr[FREG].fd;               \
+            treg = env->fpu->fpr[FREG].d;                \
         else                                             \
-            treg = (uint64_t)(env->fpu->fpr[FREG | 1].fs[FP_ENDIAN_IDX]) << 32 | \
-                   env->fpu->fpr[FREG & ~1].fs[FP_ENDIAN_IDX]; \
+            treg = (uint64_t)(env->fpu->fpr[FREG | 1].w[FP_ENDIAN_IDX]) << 32 | \
+                   env->fpu->fpr[FREG & ~1].w[FP_ENDIAN_IDX]; \
         FORCE_RET();                                     \
     }
 
@@ -61,10 +61,10 @@ OP_WSTORE_FREG(WT2, WT2_fpr, FREG)
     void glue(glue(op_store_fpr_,tregname), FREG) (void) \
     {                                                    \
         if (env->hflags & MIPS_HFLAG_F64)                \
-            env->fpu->fpr[FREG].fd = treg;               \
+            env->fpu->fpr[FREG].d = treg;                \
         else {                                           \
-            env->fpu->fpr[FREG | 1].fs[FP_ENDIAN_IDX] = treg >> 32; \
-            env->fpu->fpr[FREG & ~1].fs[FP_ENDIAN_IDX] = treg;      \
+            env->fpu->fpr[FREG | 1].w[FP_ENDIAN_IDX] = treg >> 32; \
+            env->fpu->fpr[FREG & ~1].w[FP_ENDIAN_IDX] = treg;      \
         }                                                \
         FORCE_RET();                                     \
     }
@@ -81,14 +81,14 @@ OP_DSTORE_FREG(DT2, DT2_fpr, FREG)
 #define OP_PSLOAD_FREG(treg, tregname, FREG)             \
     void glue(glue(op_load_fpr_,tregname), FREG) (void)  \
     {                                                    \
-        treg = env->fpu->fpr[FREG].fs[!FP_ENDIAN_IDX];   \
+        treg = env->fpu->fpr[FREG].w[!FP_ENDIAN_IDX];   \
         FORCE_RET();                                     \
     }
 
 #define OP_PSSTORE_FREG(treg, tregname, FREG)            \
     void glue(glue(op_store_fpr_,tregname), FREG) (void) \
     {                                                    \
-        env->fpu->fpr[FREG].fs[!FP_ENDIAN_IDX] = treg;   \
+        env->fpu->fpr[FREG].w[!FP_ENDIAN_IDX] = treg;   \
         FORCE_RET();                                     \
     }
 

diff --git a/target-mips/op.c b/target-mips/op.c
index 4b3e01b4baff2086ce1f272680576550afb4d535..0ecc93081903d61fbd89260f9a17ed783c4db8d3 100644 (file)
--- a/target-mips/op.c
+++ b/target-mips/op.c
@@ -2682,7 +2682,7 @@ FLOAT_OP(n ## name1 ## name2, d)    \
 {                                   \
     FDT0 = float64_ ## name1 (FDT0, FDT1, &env->fpu->fp_status);    \
     FDT2 = float64_ ## name2 (FDT0, FDT2, &env->fpu->fp_status);    \
-    FDT2 ^= 1ULL << 63;             \
+    FDT2 = float64_chs(FDT2);       \
     DEBUG_FPU_STATE();              \
     FORCE_RET();                    \
 }                                   \
@@ -2690,7 +2690,7 @@ FLOAT_OP(n ## name1 ## name2, s)    \
 {                                   \
     FST0 = float32_ ## name1 (FST0, FST1, &env->fpu->fp_status);    \
     FST2 = float32_ ## name2 (FST0, FST2, &env->fpu->fp_status);    \
-    FST2 ^= 1 << 31;                \
+    FST2 = float32_chs(FST2);       \
     DEBUG_FPU_STATE();              \
     FORCE_RET();                    \
 }                                   \
@@ -2700,8 +2700,8 @@ FLOAT_OP(n ## name1 ## name2, ps)   \
     FSTH0 = float32_ ## name1 (FSTH0, FSTH1, &env->fpu->fp_status); \
     FST2 = float32_ ## name2 (FST0, FST2, &env->fpu->fp_status);    \
     FSTH2 = float32_ ## name2 (FSTH0, FSTH2, &env->fpu->fp_status); \
-    FST2 ^= 1 << 31;                \
-    FSTH2 ^= 1 << 31;               \
+    FST2 = float32_chs(FST2);       \
+    FSTH2 = float32_chs(FSTH2);     \
     DEBUG_FPU_STATE();              \
     FORCE_RET();                    \
 }

diff --git a/target-mips/op_helper.c b/target-mips/op_helper.c
index 31d062ad4d4f461acc663c17b28778e2cebc67c8..7d74efc45b3068a2ca949fa0236b434842afbb2f 100644 (file)
--- a/target-mips/op_helper.c
+++ b/target-mips/op_helper.c
@@ -626,8 +626,6 @@ void do_unassigned_access(target_phys_addr_t addr, int is_write, int is_exec,
 
 /* Complex FPU operations which may need stack space. */
 
-#define FLOAT_SIGN32 (1 << 31)
-#define FLOAT_SIGN64 (1ULL << 63)
 #define FLOAT_ONE32 (0x3f8 << 20)
 #define FLOAT_ONE64 (0x3ffULL << 52)
 #define FLOAT_TWO32 (1 << 30)
@@ -1054,7 +1052,7 @@ FLOAT_OP(name, d)         \
     FDT2 = float64_ ## name (FDT0, FDT1, &env->fpu->fp_status);    \
     update_fcr31();                                                \
     if (GET_FP_CAUSE(env->fpu->fcr31) & FP_INVALID)                \
-        FDT2 = FLOAT_QNAN64;                                       \
+        DT2 = FLOAT_QNAN64;                                        \
 }                         \
 FLOAT_OP(name, s)         \
 {                         \
@@ -1062,7 +1060,7 @@ FLOAT_OP(name, s)         \
     FST2 = float32_ ## name (FST0, FST1, &env->fpu->fp_status);    \
     update_fcr31();                                                \
     if (GET_FP_CAUSE(env->fpu->fcr31) & FP_INVALID)                \
-        FST2 = FLOAT_QNAN32;                                       \
+        WT2 = FLOAT_QNAN32;                                        \
 }                         \
 FLOAT_OP(name, ps)        \
 {                         \
@@ -1071,8 +1069,8 @@ FLOAT_OP(name, ps)        \
     FSTH2 = float32_ ## name (FSTH0, FSTH1, &env->fpu->fp_status); \
     update_fcr31();       \
     if (GET_FP_CAUSE(env->fpu->fcr31) & FP_INVALID) {              \
-        FST2 = FLOAT_QNAN32;                                       \
-        FSTH2 = FLOAT_QNAN32;                                      \
+        WT2 = FLOAT_QNAN32;                                        \
+        WTH2 = FLOAT_QNAN32;                                       \
     }                     \
 }
 FLOAT_BINOP(add)
@@ -1086,14 +1084,14 @@ FLOAT_OP(recip2, d)
 {
     set_float_exception_flags(0, &env->fpu->fp_status);
     FDT2 = float64_mul(FDT0, FDT2, &env->fpu->fp_status);
-    FDT2 = float64_sub(FDT2, FLOAT_ONE64, &env->fpu->fp_status) ^ FLOAT_SIGN64;
+    FDT2 = float64_chs(float64_sub(FDT2, FLOAT_ONE64, &env->fpu->fp_status));
     update_fcr31();
 }
 FLOAT_OP(recip2, s)
 {
     set_float_exception_flags(0, &env->fpu->fp_status);
     FST2 = float32_mul(FST0, FST2, &env->fpu->fp_status);
-    FST2 = float32_sub(FST2, FLOAT_ONE32, &env->fpu->fp_status) ^ FLOAT_SIGN32;
+    FST2 = float32_chs(float32_sub(FST2, FLOAT_ONE32, &env->fpu->fp_status));
     update_fcr31();
 }
 FLOAT_OP(recip2, ps)
@@ -1101,8 +1099,8 @@ FLOAT_OP(recip2, ps)
     set_float_exception_flags(0, &env->fpu->fp_status);
     FST2 = float32_mul(FST0, FST2, &env->fpu->fp_status);
     FSTH2 = float32_mul(FSTH0, FSTH2, &env->fpu->fp_status);
-    FST2 = float32_sub(FST2, FLOAT_ONE32, &env->fpu->fp_status) ^ FLOAT_SIGN32;
-    FSTH2 = float32_sub(FSTH2, FLOAT_ONE32, &env->fpu->fp_status) ^ FLOAT_SIGN32;
+    FST2 = float32_chs(float32_sub(FST2, FLOAT_ONE32, &env->fpu->fp_status));
+    FSTH2 = float32_chs(float32_sub(FSTH2, FLOAT_ONE32, &env->fpu->fp_status));
     update_fcr31();
 }
 
@@ -1111,7 +1109,7 @@ FLOAT_OP(rsqrt2, d)
     set_float_exception_flags(0, &env->fpu->fp_status);
     FDT2 = float64_mul(FDT0, FDT2, &env->fpu->fp_status);
     FDT2 = float64_sub(FDT2, FLOAT_ONE64, &env->fpu->fp_status);
-    FDT2 = float64_div(FDT2, FLOAT_TWO64, &env->fpu->fp_status) ^ FLOAT_SIGN64;
+    FDT2 = float64_chs(float64_div(FDT2, FLOAT_TWO64, &env->fpu->fp_status));
     update_fcr31();
 }
 FLOAT_OP(rsqrt2, s)
@@ -1119,7 +1117,7 @@ FLOAT_OP(rsqrt2, s)
     set_float_exception_flags(0, &env->fpu->fp_status);
     FST2 = float32_mul(FST0, FST2, &env->fpu->fp_status);
     FST2 = float32_sub(FST2, FLOAT_ONE32, &env->fpu->fp_status);
-    FST2 = float32_div(FST2, FLOAT_TWO32, &env->fpu->fp_status) ^ FLOAT_SIGN32;
+    FST2 = float32_chs(float32_div(FST2, FLOAT_TWO32, &env->fpu->fp_status));
     update_fcr31();
 }
 FLOAT_OP(rsqrt2, ps)
@@ -1129,8 +1127,8 @@ FLOAT_OP(rsqrt2, ps)
     FSTH2 = float32_mul(FSTH0, FSTH2, &env->fpu->fp_status);
     FST2 = float32_sub(FST2, FLOAT_ONE32, &env->fpu->fp_status);
     FSTH2 = float32_sub(FSTH2, FLOAT_ONE32, &env->fpu->fp_status);
-    FST2 = float32_div(FST2, FLOAT_TWO32, &env->fpu->fp_status) ^ FLOAT_SIGN32;
-    FSTH2 = float32_div(FSTH2, FLOAT_TWO32, &env->fpu->fp_status) ^ FLOAT_SIGN32;
+    FST2 = float32_chs(float32_div(FST2, FLOAT_TWO32, &env->fpu->fp_status));
+    FSTH2 = float32_chs(float32_div(FSTH2, FLOAT_TWO32, &env->fpu->fp_status));
     update_fcr31();
 }
 
@@ -1164,8 +1162,8 @@ void do_cmp_d_ ## op (long cc)                 \
 void do_cmpabs_d_ ## op (long cc)              \
 {                                              \
     int c;                                     \
-    FDT0 &= ~FLOAT_SIGN64;                     \
-    FDT1 &= ~FLOAT_SIGN64;                     \
+    FDT0 = float64_chs(FDT0);                  \
+    FDT1 = float64_chs(FDT1);                  \
     c = cond;                                  \
     update_fcr31();                            \
     if (c)                                     \
@@ -1222,8 +1220,8 @@ void do_cmp_s_ ## op (long cc)                 \
 void do_cmpabs_s_ ## op (long cc)              \
 {                                              \
     int c;                                     \
-    FST0 &= ~FLOAT_SIGN32;                     \
-    FST1 &= ~FLOAT_SIGN32;                     \
+    FST0 = float32_abs(FST0);                  \
+    FST1 = float32_abs(FST1);                  \
     c = cond;                                  \
     update_fcr31();                            \
     if (c)                                     \
@@ -1285,10 +1283,10 @@ void do_cmp_ps_ ## op (long cc)                \
 void do_cmpabs_ps_ ## op (long cc)             \
 {                                              \
     int cl, ch;                                \
-    FST0 &= ~FLOAT_SIGN32;                     \
-    FSTH0 &= ~FLOAT_SIGN32;                    \
-    FST1 &= ~FLOAT_SIGN32;                     \
-    FSTH1 &= ~FLOAT_SIGN32;                    \
+    FST0 = float32_abs(FST0);                  \
+    FSTH0 = float32_abs(FSTH0);                \
+    FST1 = float32_abs(FST1);                  \
+    FSTH1 = float32_abs(FSTH1);                \
     cl = condl;                                \
     ch = condh;                                \
     update_fcr31();                            \