portio_list_add(&s->port_list, isa_address_space_io(&s->parent_obj),
s->iobase);
- DMA_init(1);
+ DMA_init(isa_bus_from_device(ISA_DEVICE(dev)), 1);
memset(s->commands, 0, sizeof(s->commands));
}
}
};
-void DMA_init(int high_page_enable)
+void DMA_init(ISABus *bus, int high_page_enable)
{
dma_init2(&dma_controllers[0], 0x00, 0, 0x80, high_page_enable ? 0x480 : -1);
dma_init2(&dma_controllers[1], 0xc0, 1, 0x88, high_page_enable ? 0x488 : -1);
port92 = isa_create_simple(isa_bus, "port92");
port92_init(port92, &a20_line[1]);
- DMA_init(0);
+ DMA_init(isa_bus, 0);
for(i = 0; i < MAX_FD; i++) {
fd[i] = drive_get(IF_FLOPPY, 0, i);
/* init other devices */
pit = pit_init(isa_bus, 0x40, 0, NULL);
- DMA_init(0);
+ DMA_init(isa_bus, 0);
/* Super I/O */
isa_create_simple(isa_bus, "i8042");
/* ISA devices */
i8259 = i8259_init(isa_bus, env->irq[4]);
isa_bus_irqs(isa_bus, i8259);
- DMA_init(0);
+ DMA_init(isa_bus, 0);
pit = pit_init(isa_bus, 0x40, 0, NULL);
pcspk_init(isa_bus, pit);
smbus_eeprom_init(smbus, 8, smbus_eeprom_buf, smbus_eeprom_size);
g_free(smbus_eeprom_buf);
pit = pit_init(isa_bus, 0x40, 0, NULL);
- DMA_init(0);
+ DMA_init(isa_bus, 0);
/* Super I/O */
isa_create_simple(isa_bus, "i8042");
void DMA_release_DREQ (int nchan) {}
void DMA_schedule(void) {}
-void DMA_init(int high_page_enable)
+void DMA_init(ISABus *bus, int high_page_enable)
{
}
void DMA_release_DREQ (int nchan) {}
void DMA_schedule(void) {}
-void DMA_init(int high_page_enable)
+void DMA_init(ISABus *bus, int high_page_enable)
{
}
void DMA_hold_DREQ (int nchan);
void DMA_release_DREQ (int nchan);
void DMA_schedule(void);
-void DMA_init(int high_page_enable);
+void DMA_init(ISABus *bus, int high_page_enable);
void DMA_register_channel (int nchan,
DMA_transfer_handler transfer_handler,
void *opaque);