]> xenbits.xensource.com Git - ovmf.git/commitdiff
UefiCpuPkg/CpuPageTableLib:Initialize some LocalVariable at beginning
authorDun Tan <dun.tan@intel.com>
Thu, 16 Mar 2023 02:30:53 +0000 (10:30 +0800)
committermergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
Mon, 27 Mar 2023 08:21:58 +0000 (08:21 +0000)
Move some local variable initialization to the beginning of the
function. Also delete duplicated calculation for RegionLength.

Signed-off-by: Dun Tan <dun.tan@intel.com>
Cc: Eric Dong <eric.dong@intel.com>
Reviewed-by: Ray Ni <ray.ni@intel.com>
Cc: Rahul Kumar <rahul1.kumar@intel.com>
Tested-by: Gerd Hoffmann <kraxel@redhat.com>
Acked-by: Gerd Hoffmann <kraxel@redhat.com>
UefiCpuPkg/Library/CpuPageTableLib/CpuPageTableMap.c

index 218068a3e1fcdbcfc2846205a71b6466a44eb7d8..127b65183f549f916784394c1479897bf489ad13 100644 (file)
@@ -258,6 +258,7 @@ PageTableLibMapInLevel (
   UINTN               BitStart;\r
   UINTN               Index;\r
   IA32_PAGING_ENTRY   *PagingEntry;\r
+  UINTN               PagingEntryIndex;\r
   IA32_PAGING_ENTRY   *CurrentPagingEntry;\r
   UINT64              RegionLength;\r
   UINT64              SubLength;\r
@@ -288,6 +289,14 @@ PageTableLibMapInLevel (
   LocalParentAttribute.Uint64 = ParentAttribute->Uint64;\r
   ParentAttribute             = &LocalParentAttribute;\r
 \r
+  //\r
+  // RegionLength: 256T (1 << 48) 512G (1 << 39), 1G (1 << 30), 2M (1 << 21) or 4K (1 << 12).\r
+  //\r
+  BitStart         = 12 + (Level - 1) * 9;\r
+  PagingEntryIndex = (UINTN)BitFieldRead64 (LinearAddress + Offset, BitStart, BitStart + 9 - 1);\r
+  RegionLength     = REGION_LENGTH (Level);\r
+  RegionMask       = RegionLength - 1;\r
+\r
   //\r
   // ParentPagingEntry ONLY is deferenced for checking Present and MustBeOne bits\r
   // when Modify is FALSE.\r
@@ -353,8 +362,7 @@ PageTableLibMapInLevel (
       //\r
       PageTableLibSetPnle (&ParentPagingEntry->Pnle, &NopAttribute, &AllOneMask);\r
 \r
-      RegionLength = REGION_LENGTH (Level);\r
-      PagingEntry  = (IA32_PAGING_ENTRY *)(UINTN)IA32_PNLE_PAGE_TABLE_BASE_ADDRESS (&ParentPagingEntry->Pnle);\r
+      PagingEntry = (IA32_PAGING_ENTRY *)(UINTN)IA32_PNLE_PAGE_TABLE_BASE_ADDRESS (&ParentPagingEntry->Pnle);\r
       for (SubOffset = 0, Index = 0; Index < 512; Index++) {\r
         PagingEntry[Index].Uint64 = OneOfPagingEntry.Uint64 + SubOffset;\r
         SubOffset                += RegionLength;\r
@@ -425,15 +433,10 @@ PageTableLibMapInLevel (
   }\r
 \r
   //\r
-  // RegionLength: 256T (1 << 48) 512G (1 << 39), 1G (1 << 30), 2M (1 << 21) or 4K (1 << 12).\r
   // RegionStart:  points to the linear address that's aligned on RegionLength and lower than (LinearAddress + Offset).\r
   //\r
-  BitStart     = 12 + (Level - 1) * 9;\r
-  Index        = (UINTN)BitFieldRead64 (LinearAddress + Offset, BitStart, BitStart + 9 - 1);\r
-  RegionLength = LShiftU64 (1, BitStart);\r
-  RegionMask   = RegionLength - 1;\r
-  RegionStart  = (LinearAddress + Offset) & ~RegionMask;\r
-\r
+  Index                   = PagingEntryIndex;\r
+  RegionStart             = (LinearAddress + Offset) & ~RegionMask;\r
   ParentAttribute->Uint64 = PageTableLibGetPnleMapAttribute (&ParentPagingEntry->Pnle, ParentAttribute);\r
 \r
   //\r