x86: blacklist new AMD CPUID bits for PV domains

there are some new CPUID bits (and leaves) which Dom0 and PV domains
should not see to avoid trouble, since we don't emulate the features.
The most prominent one is a topology leaf, which contains information
specific to the physical CPU, not the virtual one. To avoid confusion
(and possibly crashes) due to a confused Dom0 scheduler simply disable
these bits.

Signed-off-by: Andre Przywara <andre.przywara@amd.com>
Signed-off-by: Keir Fraser <keir@xen.org>
xen-unstable changeset:   22815:4785c70c2b6d
xen-unstable date:        Wed Jan 26 08:45:40 2011 +0000

diff --git a/tools/libxc/xc_cpufeature.h b/tools/libxc/xc_cpufeature.h
index 397cfbcb15a185f4a1bfa66b3e6a6945e1eb3c71..96ba4a66b5040fa5a397c606838f0e29114c6d75 100644 (file)
--- a/tools/libxc/xc_cpufeature.h
+++ b/tools/libxc/xc_cpufeature.h
@@ -114,5 +114,10 @@
 #define X86_FEATURE_SSE5       (6*32+ 11) /* AMD Streaming SIMD Extensions-5 */
 #define X86_FEATURE_SKINIT     (6*32+ 12) /* SKINIT, STGI/CLGI, DEV */
 #define X86_FEATURE_WDT                (6*32+ 13) /* Watchdog Timer */
+#define X86_FEATURE_LWP         (6*32+15) /* Light Weight Profiling */
+#define X86_FEATURE_FMA4        (6*32+16) /* 4 operands MAC instructions */
+#define X86_FEATURE_NODEID_MSR  (6*32+19) /* NodeId MSR */
+#define X86_FEATURE_TBM         (6*32+21) /* trailing bit manipulations */
+#define X86_FEATURE_TOPOEXT     (6*32+22) /* topology extensions CPUID leafs */
 
 #endif /* __LIBXC_CPUFEATURE_H */

diff --git a/tools/libxc/xc_cpuid_x86.c b/tools/libxc/xc_cpuid_x86.c
index 54174a297d54efee68e852c73661d53169332b99..ebb0ef6118c1a5cc1d9148f147f5d659dff98d0a 100644 (file)
--- a/tools/libxc/xc_cpuid_x86.c
+++ b/tools/libxc/xc_cpuid_x86.c
@@ -341,11 +341,16 @@ static void xc_cpuid_pv_policy(
         clear_bit(X86_FEATURE_IBS, regs[2]);
         clear_bit(X86_FEATURE_SKINIT, regs[2]);
         clear_bit(X86_FEATURE_WDT, regs[2]);
+        clear_bit(X86_FEATURE_LWP, regs[2]);
+        clear_bit(X86_FEATURE_NODEID_MSR, regs[2]);
+        clear_bit(X86_FEATURE_TOPOEXT, regs[2]);
         break;
     case 5: /* MONITOR/MWAIT */
     case 0xa: /* Architectural Performance Monitor Features */
     case 0x8000000a: /* SVM revision and features */
     case 0x8000001b: /* Instruction Based Sampling */
+    case 0x8000001c: /* Light Weight Profiling */
+    case 0x8000001e: /* Extended topology reporting */
         regs[0] = regs[1] = regs[2] = regs[3] = 0;
         break;
     }

diff --git a/xen/arch/x86/traps.c b/xen/arch/x86/traps.c
index ce5edf564ac566f9a82fdaccf50761d66088c718..53c240c69ef7ac0a5f5082aac6429fb322888e0b 100644 (file)
--- a/xen/arch/x86/traps.c
+++ b/xen/arch/x86/traps.c
@@ -813,11 +813,16 @@ static void pv_cpuid(struct cpu_user_regs *regs)
         __clear_bit(X86_FEATURE_IBS % 32, &c);
         __clear_bit(X86_FEATURE_SKINIT % 32, &c);
         __clear_bit(X86_FEATURE_WDT % 32, &c);
+        __clear_bit(X86_FEATURE_LWP % 32, &c);
+        __clear_bit(X86_FEATURE_NODEID_MSR % 32, &c);
+        __clear_bit(X86_FEATURE_TOPOEXT % 32, &c);
         break;
     case 5: /* MONITOR/MWAIT */
     case 0xa: /* Architectural Performance Monitor Features */
     case 0x8000000a: /* SVM revision and features */
     case 0x8000001b: /* Instruction Based Sampling */
+    case 0x8000001c: /* Light Weight Profiling */
+    case 0x8000001e: /* Extended topology reporting */
         a = b = c = d = 0;
         break;
     default:

diff --git a/xen/include/asm-x86/cpufeature.h b/xen/include/asm-x86/cpufeature.h
index 6e7b3983414810aef7aa3a1260c2bf5d6347c817..cfe05593dc4e7e419e9bdcc350e12ef1ea7a320a 100644 (file)
--- a/xen/include/asm-x86/cpufeature.h
+++ b/xen/include/asm-x86/cpufeature.h
@@ -129,6 +129,11 @@
 #define X86_FEATURE_SSE5       (6*32+ 11) /* AMD Streaming SIMD Extensions-5 */
 #define X86_FEATURE_SKINIT     (6*32+ 12) /* SKINIT, STGI/CLGI, DEV */
 #define X86_FEATURE_WDT                (6*32+ 13) /* Watchdog Timer */
+#define X86_FEATURE_LWP         (6*32+15) /* Light Weight Profiling */
+#define X86_FEATURE_FMA4        (6*32+16) /* 4 operands MAC instructions */
+#define X86_FEATURE_NODEID_MSR  (6*32+19) /* NodeId MSR */
+#define X86_FEATURE_TBM         (6*32+21) /* trailing bit manipulations */
+#define X86_FEATURE_TOPOEXT     (6*32+22) /* topology extensions CPUID leafs */
 
 #define cpu_has(c, bit)                test_bit(bit, (c)->x86_capability)
 #define boot_cpu_has(bit)      test_bit(bit, boot_cpu_data.x86_capability)