GIC base addr of the chromebook.

diff --git a/xen/arch/arm/arm32/mode_switch.S b/xen/arch/arm/arm32/mode_switch.S
index 411eb924cb976d04804757c0bf4c3c357b98eedf..8add8c01167093a0bffab931cae620a93c0dee73 100644 (file)
--- a/xen/arch/arm/arm32/mode_switch.S
+++ b/xen/arch/arm/arm32/mode_switch.S
@@ -76,7 +76,7 @@ enter_hyp_mode:
         mcr   CP32(r0, CNTFRQ)
         ldr   r0, =0x40c00           /* SMP, c11, c10 in non-secure mode */
         mcr   CP32(r0, NSACR)
-        mov   r0, #GIC_BASE_ADDRESS
+        ldr   r0, =GIC_BASE_ADDRESS
         add   r0, r0, #GIC_DR_OFFSET
         /* Disable the GIC distributor, on the boot CPU only */
         mov   r1, #0
@@ -93,7 +93,7 @@ enter_hyp_mode:
         streq r2, [r0, #4]           /* Interrupts 32-63 (SPI) */
         streq r2, [r0, #8]           /* Interrupts 64-95 (SPI) */
         /* Disable the GIC CPU interface on all processors */
-        mov   r0, #GIC_BASE_ADDRESS
+        ldr   r0, =GIC_BASE_ADDRESS
         add   r0, r0, #GIC_CR_OFFSET
         mov   r1, #0
         str   r1, [r0]

diff --git a/xen/include/asm-arm/config.h b/xen/include/asm-arm/config.h
index 2a05539143bb6cef09476021b9752e651f31682b..f8a88c45c5f60170838c5b8ac84b9f487fd5a0db 100644 (file)
--- a/xen/include/asm-arm/config.h
+++ b/xen/include/asm-arm/config.h
@@ -116,7 +116,7 @@ extern unsigned long frametable_virt_end;
 /* Board-specific: base address of PL011 UART */
 #define EARLY_UART_ADDRESS 0x1c090000
 /* Board-specific: base address of GIC + its regs */
-#define GIC_BASE_ADDRESS 0x2c000000
+#define GIC_BASE_ADDRESS 0x10480000
 #define GIC_DR_OFFSET 0x1000
 #define GIC_CR_OFFSET 0x2000
 #define GIC_HR_OFFSET 0x4000 /* Guess work http://lists.infradead.org/pipermail/linux-arm-kernel/2011-September/064219.html */