]> xenbits.xensource.com Git - people/sstabellini/xen-unstable.git/.git/commitdiff
xen: match VTCR_EL2 SL0 attribute in TTBCR
authorStefano Stabellini <stefano.stabellini@xilinx.com>
Thu, 6 Sep 2018 17:52:41 +0000 (10:52 -0700)
committerStefano Stabellini <sstabellini@kernel.org>
Wed, 4 Dec 2019 23:58:09 +0000 (15:58 -0800)
The SL0 attribute in TTBCR, which specifies the entry level in the page
table lookup, should be the same as the SL0 attribute in VTCR_EL2, given
that pagetables are shared between MMU and SMMU.

Make it so, by reading the value from VTCR_EL2, and setting reg
accordingly.

Signed-off-by: Stefano Stabellini <stefanos@xilinx.com>
Tested-by: Upender Cherukupally <upender@xilinx.com>
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
xen/drivers/passthrough/arm/smmu.c

index 94662a850187b2d07e788a69027ac67e0e5b848d..2bcecc7ac68e565e51233feeaa00a7c6616bb929 100644 (file)
@@ -1151,8 +1151,11 @@ static void arm_smmu_init_context_bank(struct arm_smmu_domain *smmu_domain)
              (TTBCR_RGN_WBWA << TTBCR_ORGN0_SHIFT) |
              (TTBCR_RGN_WBWA << TTBCR_IRGN0_SHIFT);
 
-       if (!stage1)
-               reg |= (TTBCR_SL0_LVL_1 << TTBCR_SL0_SHIFT);
+       /* Xen: Match VTCR_EL2 SL0 attribute */
+       if (!stage1) {
+               u32 vtcr = READ_SYSREG32(VTCR_EL2);
+               reg |= vtcr & (TTBCR_SL0_MASK << TTBCR_SL0_SHIFT);
+       }
 
        writel_relaxed(reg, cb_base + ARM_SMMU_CB_TTBCR);