tools/mce: add more MCE types to xen-mceinj

Add a non-fatal MCE for AMD CPUs.

Add a fatal (PCC set) MCE for Intel CPUs.

Signed-off-by: David Vrabel <david.vrabel@citrix.com>
Acked-by: Christoph Egger <chegger@amazon.de>
Acked-by: Ian Campbell <ian.campbell@citrix.com>

diff --git a/tools/tests/mce-test/tools/xen-mceinj.c b/tools/tests/mce-test/tools/xen-mceinj.c
index 1f872a50967072e6e07fec452b6acd70f9e00800..8ad045f66ae70a50f5af4e6ec0e1e353815ea3ee 100644 (file)
--- a/tools/tests/mce-test/tools/xen-mceinj.c
+++ b/tools/tests/mce-test/tools/xen-mceinj.c
@@ -93,6 +93,22 @@ static struct mce_info mce_table[] = {
         .mci_misc = 0x86ull,
         .cmci = true,
     },
+    /* AMD L1 instruction cache data or tag parity. */
+    {
+        .description = "AMD L1 icache parity",
+        .mcg_stat = 0x5,
+        .bank = 1,
+        .mci_stat = 0x9400000000000151ull,
+        .mci_misc = 0x86ull,
+    },
+    /* LLC (Last Level Cache) EWB (Explicit Write Back) SRAO MCE */
+    {
+        .description = "MCE_SRAO_MEM (Fatal)",
+        .mcg_stat = 0x5,
+        .bank = 7,
+        .mci_stat = 0xBF2000008000017Aull,
+        .mci_misc = 0x86ull,
+    },
 };
 #define MCE_TABLE_SIZE (sizeof(mce_table)/sizeof(mce_table[0]))