#endif
static void inject_undef_exception(struct cpu_user_regs *regs,
- int instr_len)
+ const union hsr hsr)
{
if ( is_32bit_domain(current->domain) )
inject_undef32_exception(regs);
#ifdef CONFIG_ARM_64
else
- inject_undef64_exception(regs, instr_len);
+ inject_undef64_exception(regs, hsr.len);
#endif
}
case HSR_CPREG32(CNTP_CTL):
case HSR_CPREG32(CNTP_TVAL):
if ( !vtimer_emulate(regs, hsr) )
- goto undef_cp15_32;
+ return inject_undef_exception(regs, hsr);
break;
case HSR_CPREG32(ACTLR):
if ( psr_mode_is_user(regs) )
- goto undef_cp15_32;
+ return inject_undef_exception(regs, hsr);
if ( cp32.read )
*r = v->arch.actlr;
break;
case HSR_CPREG32(PMUSERENR):
/* RO at EL0. RAZ/WI at EL1 */
if ( psr_mode_is_user(regs) && !hsr.cp32.read )
- goto undef_cp15_32;
+ return inject_undef_exception(regs, hsr);
goto cp15_32_raz_wi;
case HSR_CPREG32(PMINTENSET):
case HSR_CPREG32(PMINTENCLR):
/* EL1 only, however MDCR_EL2.TPM==1 means EL0 may trap here also. */
if ( psr_mode_is_user(regs) )
- goto undef_cp15_32;
+ return inject_undef_exception(regs, hsr);
goto cp15_32_raz_wi;
case HSR_CPREG32(PMCR):
case HSR_CPREG32(PMCNTENSET):
* emulate that register as 0 above.
*/
if ( psr_mode_is_user(regs) )
- goto undef_cp15_32;
+ return inject_undef_exception(regs, hsr);
cp15_32_raz_wi:
if ( cp32.read )
*r = 0;
cp32.op1, cp32.reg, cp32.crn, cp32.crm, cp32.op2, regs->pc);
gdprintk(XENLOG_ERR, "unhandled 32-bit CP15 access %#x\n",
hsr.bits & HSR_CP32_REGS_MASK);
- undef_cp15_32:
- inject_undef_exception(regs, hsr.len);
+ inject_undef_exception(regs, hsr);
return;
}
advance_pc(regs, hsr);
case HSR_CPREG64(CNTPCT):
case HSR_CPREG64(CNTP_CVAL):
if ( !vtimer_emulate(regs, hsr) )
- goto undef_cp15_64;
+ return inject_undef_exception(regs, hsr);
break;
default:
{
cp64.op1, cp64.reg1, cp64.reg2, cp64.crm, regs->pc);
gdprintk(XENLOG_ERR, "unhandled 64-bit CP15 access %#x\n",
hsr.bits & HSR_CP64_REGS_MASK);
- undef_cp15_64:
- inject_undef_exception(regs, hsr.len);
+ inject_undef_exception(regs, hsr);
return;
}
}
* is set to 0, which we emulated below.
*/
if ( !cp32.read )
- goto undef_cp14_32;
+ return inject_undef_exception(regs, hsr);
/* Implement the minimum requirements:
* - Number of watchpoints: 1
* is set to 0, which we emulated below.
*/
if ( !cp32.read )
- goto undef_cp14_32;
+ return inject_undef_exception(regs, hsr);
*r = 0;
break;
case HSR_CPREG32(DBGDSCREXT):
if ( usr_mode(regs) )
- goto undef_cp14_32;
+ return inject_undef_exception(regs, hsr);
/* Implement debug status and control register as RAZ/WI.
* The OS won't use Hardware debug if MDBGen not set
case HSR_CPREG32(DBGBCR1):
case HSR_CPREG32(DBGOSDLR):
if ( usr_mode(regs) )
- goto undef_cp14_32;
+ return inject_undef_exception(regs, hsr);
/* RAZ/WI */
if ( cp32.read )
*r = 0;
case HSR_CPREG32(DBGOSLAR):
if ( usr_mode(regs) )
- goto undef_cp14_32;
+ return inject_undef_exception(regs, hsr);
/* WO */
if ( cp32.read )
- goto undef_cp14_32;
+ return inject_undef_exception(regs, hsr);
/* else: ignore */
break;
default:
cp32.op1, cp32.reg, cp32.crn, cp32.crm, cp32.op2, regs->pc);
gdprintk(XENLOG_ERR, "unhandled 32-bit cp14 access %#x\n",
hsr.bits & HSR_CP32_REGS_MASK);
- undef_cp14_32:
- inject_undef_exception(regs, hsr.len);
+ inject_undef_exception(regs, hsr);
return;
}
gdprintk(XENLOG_ERR, "unhandled 64-bit CP14 access %#x\n",
hsr.bits & HSR_CP64_REGS_MASK);
- inject_undef_exception(regs, hsr.len);
+ inject_undef_exception(regs, hsr);
}
static void do_cp(struct cpu_user_regs *regs, const union hsr hsr)
ASSERT(!cp.tas); /* We don't trap SIMD instruction */
gdprintk(XENLOG_ERR, "unhandled CP%d access\n", cp.coproc);
- inject_undef_exception(regs, hsr.len);
+ inject_undef_exception(regs, hsr);
}
#ifdef CONFIG_ARM_64
* undef.
*/
if ( psr_mode_is_user(regs) )
- goto undef_sysreg;
+ return inject_undef_exception(regs, hsr);
goto sysreg_raz_wi;
case HSR_SYSREG_MDCCSR_EL0:
* register as RAZ/WI above. So RO at both EL0 and EL1.
*/
if ( !hsr.sysreg.read )
- goto undef_sysreg;
+ return inject_undef_exception(regs, hsr);
*x = 0;
break;
case HSR_SYSREG_PMUSERENR_EL0:
/* RO at EL0. RAZ/WI at EL1 */
if ( psr_mode_is_user(regs) && !hsr.sysreg.read )
- goto undef_sysreg;
+ return inject_undef_exception(regs, hsr);
goto sysreg_raz_wi;
case HSR_SYSREG_PMCR_EL0:
case HSR_SYSREG_PMCNTENSET_EL0:
* emulate that register as 0 above.
*/
if ( psr_mode_is_user(regs) )
- goto undef_sysreg;
+ return inject_undef_exception(regs, hsr);
sysreg_raz_wi:
if ( hsr.sysreg.read )
*x = 0;
/* Write only, Write ignore registers: */
case HSR_SYSREG_OSLAR_EL1:
if ( hsr.sysreg.read )
- goto undef_sysreg;
+ return inject_undef_exception(regs, hsr);
/* else: write ignored */
break;
case HSR_SYSREG_CNTP_CTL_EL0:
case HSR_SYSREG_CNTP_TVAL_EL0:
case HSR_SYSREG_CNTP_CVAL_EL0:
if ( !vtimer_emulate(regs, hsr) )
- goto undef_sysreg;
+ return inject_undef_exception(regs, hsr);
break;
case HSR_SYSREG_ICC_SGI1R_EL1:
if ( !vgic_emulate(regs, hsr) )
sysreg.reg, regs->pc);
gdprintk(XENLOG_ERR, "unhandled 64-bit sysreg access %#x\n",
hsr.bits & HSR_SYSREG_REGS_MASK);
- undef_sysreg:
- inject_undef_exception(regs, hsr.sysreg.len);
+ inject_undef_exception(regs, hsr);
return;
}
}