]> xenbits.xensource.com Git - xen.git/commitdiff
svm: Do not intercept RDTSC(P) when TSC scaling is supported by hardware
authorBoris Ostrovsky <boris.ostrovsky@amd.com>
Wed, 25 Apr 2012 12:53:14 +0000 (13:53 +0100)
committerBoris Ostrovsky <boris.ostrovsky@amd.com>
Wed, 25 Apr 2012 12:53:14 +0000 (13:53 +0100)
When running in TSC_MODE_ALWAYS_EMULATE mode on processors that
support TSC scaling we don't need to intercept RDTSC/RDTSCP
instructions.

Signed-off-by: Boris Ostrovsky <boris.ostrovsky@amd.com>
Acked-by: Wei Huang <wei.huang2@amd.com>
Tested-by: Wei Huang <wei.huang2@amd.com>
Committed-by: Keir Fraser <keir@xen.org>
xen/arch/x86/hvm/svm/svm.c

index 5d9db5694d0f0b4f151ff2d830d4eb55b539ec72..6b7b653c211f96d359b447f4f494dcfe51386f9b 100644 (file)
@@ -724,12 +724,19 @@ static void svm_set_rdtsc_exiting(struct vcpu *v, bool_t enable)
 {
     struct vmcb_struct *vmcb = v->arch.hvm_svm.vmcb;
     u32 general1_intercepts = vmcb_get_general1_intercepts(vmcb);
+    u32 general2_intercepts = vmcb_get_general2_intercepts(vmcb);
 
     general1_intercepts &= ~GENERAL1_INTERCEPT_RDTSC;
-    if ( enable )
+    general2_intercepts &= ~GENERAL2_INTERCEPT_RDTSCP;
+
+    if ( enable && !cpu_has_tsc_ratio )
+    {
         general1_intercepts |= GENERAL1_INTERCEPT_RDTSC;
+        general2_intercepts |= GENERAL2_INTERCEPT_RDTSCP;
+    }
 
     vmcb_set_general1_intercepts(vmcb, general1_intercepts);
+    vmcb_set_general2_intercepts(vmcb, general2_intercepts);
 }
 
 static unsigned int svm_get_insn_bytes(struct vcpu *v, uint8_t *buf)